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8477 Commits

Author SHA1 Message Date
José Roberto de Souza f5a58b8886 anv: Split i915 specific parts of anv_queue_submit_simple_batch() 
This will make easier to spot more places where the code can
simplified after the hasvk split.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18942>
 2022-10-04 18:35:50 +00:00
José Roberto de Souza 35ed40f356 anv: Move fetch of i915 physical device parameters 
Move everything that depends on i915_drm.h to its own function,
in a future MR will move the parameters that are also needed by
Iris to intel_device_info.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18942>
 2022-10-04 18:35:50 +00:00
José Roberto de Souza a17783b066 intel/dev: Split i915 specific parts of intel_get_device_info_from_fd() 
Continuing the work to split i915_drm.h specific code.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18942>
 2022-10-04 18:35:50 +00:00
José Roberto de Souza 03b959286e intel: Make engine related functions and types not i915 dependent 
There is too much i915_drm.h code spread, this patch start to fix that
by re-organizing engine related code.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18942>
 2022-10-04 18:35:50 +00:00
Tapani Pälli 1cf1a94f97 intel: revert preemption disable via VFG changes 
This register will not be whitelisted and this change will be
done in kernel instead.

This change reverts commits d5d4604a, ddcd6b38, 27c5b93d.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18897>
 2022-10-04 10:38:49 +00:00
Emma Anholt 0ae3eb834d ci/iris: Update iris traces checksums. 
The previous commits in this MR caused a minor rendering change for
Unvanquished.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18466>
 2022-10-03 17:18:31 +00:00
José Roberto de Souza 1e87834980 intel: Share code to read render timestamp 
Timestamp read is not in any hot path so there is no down-sides in
share the same function between iris, crocus, anv and hasvk.

Also while at it also dropping the functions to read MMIO from kernel,
the only use is read render timestamp so we don't need it.

v2:
- fix compilaton of ds

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18920>
 2022-10-03 06:26:50 -07:00
Dylan Baker 1f0a0a46d9 meson: run genxml sort tests 
Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker 3f0da1bbfa intel/genxml: run gen_sort_tags on all of the xml 
Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker 106da29196 intel/genxml: add a validation mode to gen_sort_tags 
Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker 1386fd6a7b intel/genxml: add 'nonzero' to gen_sort_tags 
which was added in ebe2a2b5f6.

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker 92857fd5c9 intel/genxml: don't overwrite the input of gen_sort_tags in place 
otherwise we can be left with garbage

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker c0aeeb93a8 intel/genxml: remove unused variable in gen_sort_tags.py 
Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker 27d89a673d intel/genxml: use a not in {x, y} instead of a != x or a != y 
It's faster, less code, and more idiomatic

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker 4fd2e15855 intel/genxml: add type annotations to gen_sort_tags.py 
let static analysis help us out

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker 3f9fe21988 intel/genxml: don't use parens with python assert statement 
assert is a statement in python, not a function. Useing parens with it
leads to madness, because assert takes two arguments in the form `assert
expression: bool, message: str`. With parens though it's tempting to
write `assert(expression, message)`, which results in an assert that is
*always* true, because a non-empty tuple (which is what is written) is
*never* false.

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker f286451ada intel/genxml: use a set for lookups 
Python will pre-compute the set since it's const, and the performance of
a set search is significantly better than that of a list search

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker e04ece53d7 intel/genxml: use a single pattern for res 
regex is expensive, do less of it.

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Caio Oliveira 6cda887ac6 intel/compiler: Explicitly include build-id when linking intel_clc 
Ensure that the program will have a build-id.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18924>
 2022-10-01 16:42:07 +00:00
Tapani Pälli 60be71aeaa anv: limit to default fast clear color when image used for transfer 
v2: use vk_image_layout_to_usage_flags for detecting
    transfer usage (Nanley)

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7189
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18836>
 2022-09-30 10:14:01 +00:00
Kenneth Graunke b61b1d5a4c Revert "intel/compiler: Vectorize gl_TessLevelInner/Outer[] writes" 
This reverts commit abba55382f.
The assertions I added late in the process broke shader-db, and my
quick fix broke CI, so let's just revert it for now and I'll resubmit
this later when it's working better.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7385
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18895>
 2022-09-29 17:39:18 -07:00
Marcin Ślusarz 9bac88856d intel/compiler: fix loading of draw_id from task & mesh payload 
Previously both destination and source were floats, so no casting was
performed, but with 7664c85b1d source register was reinterpreted as
unsigned integer, so MOV started casting that integer to float.

Fixes: 7664c85b1d ("intel/compiler: Create and use struct for TASK and MESH thread payloads")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18886>
 2022-09-29 17:17:25 +00:00
Jason Ekstrand 10bc2cd3ae vulkan: Rename viewport_state::negative_one_to_one 
This makes it a bit clearer what it's for.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18878>
 2022-09-29 05:00:10 +00:00
Lionel Landwerlin 582bf4d9f7 anv: flag BO for write combine when CPU visible and potentially in lmem 
This should fix a performance regression with the internal kernel
branch which does not support the upstream I915_MMAP_OFFSET_FIXED.

With I915_MMAP_OFFSET_FIXED we defer the mapping flags to the kernel
since it knows better where buffers are going to end up (lmem or smem).

The internal kernel doesn´t have that and there we should use write
combined for anything that can be in lmem.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18841>
 2022-09-28 09:51:31 +00:00
Mark Janes c8f563b633 anv: Allocate buffers with write-combined local memory 
Marginally improves DG1 performance (< 1%)

v2: Only on local mem (Lionel)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18841>
 2022-09-28 09:51:31 +00:00
Mark Janes 5c62ad34b6 anv: Use WC mapped local memory for block pool BO 
Improve DG1 performance:

  Fallout: +7%
  Talos:  +15%

v2: Don't drop SNOOP (Lionel)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18841>
 2022-09-28 09:51:31 +00:00
Mark Janes 755b413ffa anv: Track BOs that need a write-combined mapping 
v2: simplify logic a bit (Lionel)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18841>
 2022-09-28 09:51:31 +00:00
Kenneth Graunke a778f3edd3 blorp: Fix typo in blorp_xy_block_copy_blt 
suppotred -> supported (Thanks to Tapani for catching this.)

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15183>
 2022-09-28 08:41:35 +00:00
Kenneth Graunke 759d51c367 blorp: Implement blitter clears via XY_FAST_COLOR_BLT 
Vulkan transfer queues need this functionality.  A lot of the code is
pretty similar to what we have for XY_BLOCK_COPY_BLT.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15183>
 2022-09-28 08:41:35 +00:00
Kenneth Graunke 5f4ad65daf blorp: Make blitter_supports_aux accessible from multiple files. 
We'll want it in blorp_clear.c shortly.

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15183>
 2022-09-28 08:41:35 +00:00
Kenneth Graunke 98bd984977 intel/genxml: Add XY_FAST_COLOR_BLT 
We'll need to use this for VkCmdFillBuffer on transfer queues.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15183>
 2022-09-28 08:41:35 +00:00
Jason Ekstrand 647773a094 intel/devinfo: DG2 supports ray-tracing 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:37 +00:00
Jason Ekstrand 4c0dbe6420 anv: Advertise ray-tracing on DG2 
Also disable ray-tracing support if with_intel_vk_rt is not set.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:37 +00:00
Jordan Justen e565d1e4ea anv/meson: Use anv_flags and anv_cpp_flags in genX compiles 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:37 +00:00
Lionel Landwerlin 64e8b0d255 anv: use the right dispatch size for tracing shaders 
We assumed the trampoline shader would always be SIMD8.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:37 +00:00
Lionel Landwerlin 044cf4e75d anv: bump client visible address heap to 32GiB 
Some raytracing tests are allocating lots of buffer and because of our
2Mb alignment restriction on local memory, we're running our of VMA...

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:37 +00:00
Lionel Landwerlin 5ad803840d anv: setup scratch space correctly for RT shaders 
Things are a bit confusing because we use the term "scratch" for 2
different things :
  * the buffer for register allocation spilling
  * the buffer for storing live values between splitted shaders around shader calls

Here we're fixing the missing register allocation spilling buffer.

v2: update comments (Caio)
    fix scratch bo size computation with pipeline libraries (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:37 +00:00
Jason Ekstrand f3ddfd81b4 anv: Build BVHs on the GPU with GRL 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:37 +00:00
Jason Ekstrand dc1aedef2b intel/grl: Parse GRL files and generate C 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:37 +00:00
Jason Ekstrand 20f291c5f9 anv/grl: Add a helper for dispatching our pre-built kernels 
v2: Use the default pipeline cache (Lionel)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:37 +00:00
Jason Ekstrand 639665053f anv/grl: Build OpenCL kernels 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:37 +00:00
Iván Briano 37663438f7 anv/grl: Add a GRL file parser 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:37 +00:00
Jason Ekstrand 5f948503e4 anv: Import GRL 
GRL, or Graphics Library for Ray-tracing is a library we share with the
Windows drivers for doing BVH builds on the GPU.  It consists of a few
headers shared between CL and C code, a bunch of CL kernels, and some
GRL meta-kernels in their own format.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:37 +00:00
Lionel Landwerlin 49976b23e9 anv: add new command buffer space allocation 
To be used for acceleration structure building.

v2: fix missing u_vector_finish
    Free all BOs

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@linux.intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:37 +00:00
Jason Ekstrand 6c76ceb613 anv: Add support for OpenCL-style kernel dispatch 
v2: Use brw_cs_get_dispatch_info() (Lionel)
    Merge barrier fixes (Lionel)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:37 +00:00
Jason Ekstrand eb249f125d anv: Add support for compiling OpenCL-style kernels 
v2: remove unused definitions

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:37 +00:00
Jason Ekstrand 6ad1a5b57a anv: Add extern "C" guards 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:37 +00:00
Lionel Landwerlin 23c7142cd6 anv: disable SIMD16 for RT shaders 
Since divergence is a lot more likely in RT than compute, it makes
sense to limit ourselves to SIMD8.

The trampoline shader defaults to SIMD16 since this one is uniform.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:37 +00:00
Jason Ekstrand 5814436159 anv: Set up the memory-backed FIFO buffer 
v2: Fix incorrect goto (Caio)
    Comment 3DSTATE_BTD programming (Caio)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:36 +00:00
Jason Ekstrand 93526c89c5 anv: Implement VK_KHR_pipeline_library 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:36 +00:00