Commit Graph

7940 Commits

Author SHA1 Message Date
Kenneth Graunke b637f6c3db intel/decoder: Fix binding table pointer decoding with large offsets
XeHP supports a 20:5 pointer format, so the offset can legitimately
be more than UINT16_MAX.  Likewise, with 256B binding table mode on
Icelake/Tigerlake, we might have 18:8 pointers that exceed UINT16_MAX.

Thanks to Felix DeGrood for catching this!

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16538>
2022-05-17 08:52:00 +00:00
David Heidelberg d22eeb5ae0 ci/iris: skqp: remove flaking atlastext for TGL
Example:
 - https://gitlab.freedesktop.org/mesa/mesa/-/jobs/22380389#L4349
 - https://mesa.pages.freedesktop.org/-/mesa/-/jobs/22380389/artifacts///results/gles/report.html

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6460
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16407>
2022-05-17 06:57:19 +00:00
David Heidelberg 317496ba8a ci/iris: skqp: add default GLES rendertests for TGL
Import the intact whole rendertest file from skqp (branch
android-cts-12.1_r1) to be able remove the offending test line in the
following commit.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16407>
2022-05-17 06:57:19 +00:00
Timothy Arceri d7a071a28f gallium/drivers: set force_indirect_unrolling_sampler for all required drivers
This is set to true for all drivers that have a GLSL level
of support lower than 4.00. This matches the rule for setting the
GLSL IR option EmitNoIndirectSampler.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
2022-05-17 02:12:21 +00:00
Lionel Landwerlin 17fc7b20b1 anv: fix primitives generated queries values
Numbers in some situations are incorrect because we don't stall
properly before capturing the register value.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6412
Fixes: a468f26ca5 ("anv: implement VK_EXT_primitives_generated_query")
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16505>
2022-05-14 10:47:29 +00:00
Marcin Ślusarz 1542ab70eb anv: handle primitive shading rate for mesh
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16030>
2022-05-13 13:05:51 +00:00
Marcin Ślusarz 9acb30c8c4 intel/compiler: implement primitive shading rate for mesh
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16030>
2022-05-13 13:05:51 +00:00
Marcin Ślusarz aa1c128b54 anv: disable streamout before emitting mesh shading state
Fixes tests which use secondary command buffers.

Fixes: ef04caea9b ("anv: Implement Mesh Shading pipeline")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16493>
2022-05-13 09:43:02 +00:00
Marcin Ślusarz 29a778fa6b intel/compiler: print name of the unhandled intrinsic
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16493>
2022-05-13 09:43:02 +00:00
Marcin Ślusarz f083df8710 anv: update task/mesh distribution with the recommended values
Fixes: ef04caea9b ("anv: Implement Mesh Shading pipeline")

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16493>
2022-05-13 09:43:02 +00:00
Marcin Ślusarz 65ff6932dc intel/compiler: handle gl_Viewport and gl_Layer in FS URB setup
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16493>
2022-05-13 09:43:02 +00:00
Marcin Ślusarz 040062df41 intel/compiler: handle VARYING_SLOT_CULL_PRIMITIVE in mesh
It's needed for gl_MeshPerPrimitiveNV[].gl_ViewportMask

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16493>
2022-05-13 09:43:02 +00:00
Vadym Shovkoplias 55c71217ec driconf: Add a limit_trig_input_range option
With this option enabled range of input values for fsin and fcos is
limited to [-2*pi : 2*pi] by calculating the reminder after 2*pi modulo
division. This helps to improve calculation precision for large input
arguments on Intel.

-v2: Add limit_trig_input_range option to prog_key to update shader
     cache (Lionel)

Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16388>
2022-05-13 06:47:53 +00:00
Kenneth Graunke ad537edc7c anv: Fix INTEL_DEBUG=bat on XeHP
We no longer emit STATE_BASE_ADDRESS in every batch on XeHP, so the
decoder might not know what the various base addresses are if it's only
looking at a single batch.  Fortunately, they also never change, so we
can just emit them once here.

On earlier platforms, initializing them here should be harmless.  We'll
emit STATE_BASE_ADDRESS if we change them, which will update these.

Thanks to Iván Briano for catching this.

Fixes: 8831cb38aa ("anv: Stop updating STATE_BASE_ADDRESS on XeHP")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16287>
2022-05-12 11:10:25 -07:00
Jordan Justen ad565f6b70 intel/dev: Enable first set of DG2 PCI IDs
Mostly Matt Roper's kernel patch commit message:

The IDs added here are the subset reserved for 'motherboard down'
designs of DG2. We have all the necessary support upstream to enable
these now.

The remaining DG2 IDs for add-in cards will be enabled in a future
patch once some additional required functionality has fully landed.

Ref: https://patchwork.freedesktop.org/patch/msgid/20220425211251.77154-3-matthew.d.roper@intel.com
Cc: 22.1 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16449>
2022-05-12 03:03:57 -07:00
Jordan Justen 4456209ce5 intel/dev: Add INTEL_PLATFORM_DG2_G12
Cc: 22.1 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16449>
2022-05-12 03:03:57 -07:00
Jason Ekstrand 352e32e5ba nir/builder: Add a nir_trim_vector helper
This pattern pops up a bunch and the semantics of nir_channels() aren't
very convenient much of the time.  Let's add a nir_trim_vector() which
matches nir_pad_vector().

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>
2022-05-11 14:47:33 +00:00
Iván Briano 2e46f38902 anv: re-alloc push constants after secondary command buffers
If the secondary command buffer executed used push constants on a
different set of stages than the primary is using, we may end up not
reallocating them for the primary, getting misrender artifacts at best,
or a nice GPU hang at worst.

Fixes the tests from a CTS from the future:
dEQP-VK.dynamic_rendering.random.*

Cc: mesa-stable

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16439>
2022-05-10 21:56:49 +00:00
Karol Herbst 9c5fd100cc nir: add a nir_remove_non_entrypoints helper
This code just got duplicated a lot. There is still more, but the
remaining instances do a bit more than just removing other functions.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16348>
2022-05-10 03:37:44 +00:00
Emma Anholt af76f0bcfc ci/iris: Cut the glk-deqp test coverage in half.
It's taking 13-14 minutes of deqp-runner time, not counting booting, or
the LAVA-side job getting being queued behind other jobs.  Well past our
10-minute runtime target, and we saw load on these boards causing the
queue to get quite long
(https://gitlab.freedesktop.org/mesa/mesa/-/issues/6409#note_1368750)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16359>
2022-05-10 02:16:04 +00:00
Chia-I Wu b2b810ebff anv: advertise rectangularLines only for Gen10+
We use the non-strict algorithm (with parallelograms) prior to Gen10 for
wide lines.  We can not advertise rectangularLines.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Fixes: f6e7de41d7 ("anv: Implement VK_EXT_line_rasterization")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15432>
2022-05-06 18:22:19 +00:00
Lionel Landwerlin 969512d696 intel: fix stall debug option
Missing the parsing bit.

Fixes: 317512e038 ("anv/intel: add a new debug flag for stalling after every draw/dispatch")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16338>
2022-05-06 08:27:47 +00:00
Emma Anholt 3a42e92a4f glsl: Drop the dead MOD_TO_FLOOR path.
It's now called lower_fmod in NIR.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8044>
2022-05-05 22:25:03 +00:00
Emma Anholt 72dba615be ci/iris: Add a bunch of APL and KBL flakes recently.
I got hit by one of them trying to merge !8044.  Just update the list.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8044>
2022-05-05 22:25:03 +00:00
Emma Anholt 3c0e4be89b ci/iris: Demote APL deqp to manual-only for now.
it's been flaking with "2022-05-05 16:29:49.055151: [0m[31mERROR - Failure
getting run results: parsing results: Reading from dEQP: timed out waiting
for fd to be ready (See \"//results/c32.r1.log\")" and a pile of missings
since the brief "whoops, HW CI failed to listen to the test exit code"
regression.

The only ways I know of to hit this case would be:

1) The deqp binary abruptly wedges on its own.  This happens with NFS
failures sometimes, but the rest of the run went fine and we never got the
kernel complaining about NFS, so that seems unlikely.

2) The stderr pipe filled up before stdout was completed, and deqp got
wedged trying to output stderr (happens sometimes when you do like
NIR_DEBUG=print in your run).

Both of these seem unlikely, given that we've got a big .qpa file that
made it all the way to writing out test case durations at the end of the
run before abruptly terminating.  Why didn't we have at least some of the
test results parsed?

The next deqp-runner release we integrate will solve #2, and cleans up
these error paths a bunch, so I'm hoping we get more information soon.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16350>
2022-05-05 18:20:12 +00:00
Lionel Landwerlin 797a8850b9 anv: remove static_state_mask
This is now unnecessary. Either an instruction is never dynamic and
it's emitted in genX_pipeline.c or it can be and it's emitted in
genX_cmd_buffer.c/gfx8_cmd_buffer/gfx7_cmd_buffer.c

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
2022-05-03 17:12:45 +00:00
Lionel Landwerlin 74a27a6ccb anv: don't emit 3DSTATE_VF_TOPOLOGY in pipeline batch
v2: drop primitive_topology = 0xffffffff (Tapani)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
2022-05-03 17:12:45 +00:00
Lionel Landwerlin 48229d11ba anv: don't emit 3DSTATE_DEPTH_BOUNDS in pipeline batch
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
2022-05-03 17:12:45 +00:00
Lionel Landwerlin 76e735d09c anv: don't emit 3DSTATE_BLEND_STATE_POINTERS in pipeline batch
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
2022-05-03 17:12:45 +00:00
Lionel Landwerlin e9d000a831 anv: don't emit 3DSTATE_WM in pipeline batch
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
2022-05-03 17:12:44 +00:00
Lionel Landwerlin 065242d623 anv: don't emit 3DSTATE_STREAMOUT in pipeline batch
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
2022-05-03 17:12:44 +00:00
Lionel Landwerlin ce8bb29342 anv: never emit 3DSTATE_CPS in the pipeline batch
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
2022-05-03 17:12:44 +00:00
Lionel Landwerlin 168b13364f anv: rework sample location
On Gfx7 we can only give the sample location for a given multisample
number. This means everytime the multisampling value changes, we have
to re-emit the locations. It's fine because it's also where
(3DSTATE_MULTISAMPLE) the number of samples is stored.

On Gfx8+ though, 3DSTATE_MULTISAMPLE only holds the number of samples
and all the sample locations for all number of samples are located in
3DSTATE_SAMPLE_PATTERN. So to be more effecient there, we need to
track the locations for all sample numbers and compare new values with
the relevant sample count when touching the dynamic state.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
2022-05-03 17:12:44 +00:00
Lionel Landwerlin 810518fda7 Revert "anv: fix dynamic state emission"
This reverts commit f348103fce. The
change was causing performance regressions.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
2022-05-03 17:12:44 +00:00
Lionel Landwerlin 69e6417e19 anv: add missing logic op set in pipeline dyn state
v2: add ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP check (Tapani)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 75ad0e4b08 ("anv: support blending logic op dynamic state")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
2022-05-03 17:12:44 +00:00
Lionel Landwerlin 5048f15737 anv: reset all dynamic state after secondary execution
We don't know in what state the secondary buffer will leave the HW
when it ends. It's easier to consider everything needs to be reemitted
for now.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
2022-05-03 17:12:44 +00:00
Lionel Landwerlin 4efc997472 anv: fix invalid utrace memcpy l3 config on gfx < 11
device->l3_config is only valid on Gfx11+

This only fixes using GPU_TRACE=1

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 02a4d622ed ("anv: expose a couple of emit helper to build utrace buffer copies")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16291>
2022-05-03 13:18:48 +00:00
Rob Clark c4b5ebe1fc drm-shim: Better mmap offsets
Using the bo pointer address as the offset doesn't go over well when
someone is fuzzing you.  But we already have the mem_addr, we can simply
use that instead.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16250>
2022-05-02 19:50:33 +00:00
Caio Oliveira 7cd9adeb41 intel/compiler: In XeHP prefer <1;1,0> regions before compacting
Ken performed some tests with shader-db to evaluate the effects

```
Across all 145,848 shaders generated, the results were:

Total bytes compacted before: 3,326,224
Total bytes compacted after: 60,963,280
```

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15399>
2022-05-02 18:03:01 +00:00
Lionel Landwerlin 0be9cac742 anv: limit clflush usage
Discrete platforms don't have LLC, but on those, we mmap our buffers
with WC. So we shouldn't need to clflush there.

Anv already had a boolean field on the physical device to know whether
we need to use clflush(), based off the memory heaps available. So use
that instead.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15780>
2022-05-02 12:07:01 +00:00
Lionel Landwerlin 44e93b4c6f anv: fix clflush usage on utrace copy batch
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: cc5843a573 ("anv: implement u_trace support")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15780>
2022-05-02 12:07:01 +00:00
Francisco Jerez 14cad38b19 intel/dev: Compute pixel pipe information based on geometry topology DRM query.
This changes the intel_device_info calculation to call an additional
DRM query requesting the geometry topology from the kernel, which may
differ from the result of the current topology query on XeHP+
platforms with compute-only and 3D-only DSSes.  This seems more
reliable than the current guesswork done in intel_device_info.c trying
to figure out which DSSes are available for the render CS.

Cc: 22.1 <mesa-stable>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143>
2022-04-30 00:00:58 +00:00
Jordan Justen de99a11172 intel_dev_info: Add --hwconfig command line parameter
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14511>
2022-04-28 21:56:32 +00:00
Jordan Justen d9ff9ea9c3 intel/dev: Read hwconfig from i915
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14511>
2022-04-28 21:56:32 +00:00
Emma Anholt 536c8ee96d nir/lower_tex: Make the adding a 0 LOD to nir_op_tex in the VS optional.
This controls the whole lowering of "make tex ops with implicit
derivatives on non-implicit-derivative stages be tex ops with an explicit
lod of 0 instead", but it's really hard to describe that in a git commit
summary.

All existing callers get it added except:
- nir_to_tgsi which didn't want it.
- nouveau, which didn't want it (fixes regressions in shadowcube and
  shadow2darray with NIR, since the shading languages don't expose txl of
  those sampler types and thus it's not supported in HW)
- optional lowering passes in mesa/st (lower_rect, YUV lowering, etc)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16156>
2022-04-28 21:26:08 +00:00
Nanley Chery b023f18bad isl,iris: Add DG2 CCS modifier support for XeHP
Cc: 22.1 <mesa-stable>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14521>
2022-04-28 20:02:14 +00:00
Nanley Chery a53abeb7fb intel/isl: Add a score for I915_FORMAT_MOD_4_TILED
Enables the modifier in anv.

Cc: 22.1 <mesa-stable>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14521>
2022-04-28 20:02:14 +00:00
Anuj Phogat ac441d0953 isl,iris: Add I915_FORMAT_MOD_4_TILED support for XeHP
This patch adds Tile 4 modifier support to Mesa and allows Mesa to
use Tile 4 on gen12-hp with GBM.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: 22.1 <mesa-stable>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14521>
2022-04-28 20:02:14 +00:00
Tapani Pälli d3ef3657b2 isl: disable mcs (and mcs+ccs) for color msaa on DG2
Fixes lots of various test failures in:
   dEQP-VK.pipeline.multisample.min_sample_shading_disabled.*
   dEQP-GLES3.functional*multisample.*
   KHR-GL*sample_variables.*

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13991>
2022-04-28 05:31:52 +00:00
Lionel Landwerlin f4f350a06c anv: reemit 3DSTATE_STREAMOUT after memcpy
This doesn't fix anything because memcpy is only used before secondary
buffer execution and we dirty everything after that.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16189>
2022-04-27 18:43:00 +00:00