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180215 Commits

Author SHA1 Message Date
Mary Guillemard dee5223262 panfrost: Move occlusion query allocation to create_query 
Also ensure to check if resource allocation failed.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30553>
 2024-09-09 09:15:59 +02:00
Mary Guillemard 302127fe9d pan/kmod: Add timestamp uapi support 
This adds support for timestamp in kmod based on new uAPI changes.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30553>
 2024-09-09 09:15:47 +02:00
David Rosca 95d15406c4 radv/video: Don't use multiple tasks for one encode operation 
The begin op was sent as one task and encode op as another one.
This doesn't work on VCN2 and older, so just send both ops in same task.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31078>
 2024-09-09 06:55:03 +10:00
David Rosca 60c38b9886 radv/video: Don't use op_close in encode 
This should only be used on video session destroy, but at that point
we don't have command buffer. RENCODE_IB_OP_CLOSE_SESSION is optional,
so it's okay not using it at all.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31078>
 2024-09-09 06:54:47 +10:00
Caio Oliveira 2a5a12cb71 intel/executor: Small fixes to the help message 
Add missing @eot to the example.
Reword INTEL_DEBUG=color description.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31076>
 2024-09-07 16:32:50 +00:00
David Rosca e509139f61 radeonsi/vcn: Add support for H264 8x8 transform on VCN5 
Enabling this gives slight increase in quality.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31020>
 2024-09-07 04:48:18 +00:00
David Rosca 22d98e35cd radeonsi/vcn: Stop hardcoding values in VCN version overrides 
It only makes it more likely to forget updating all functions when
implementing these features and cause issues.
Also fixes H264 constrained_intra_pred on VCN5.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31020>
 2024-09-07 04:48:18 +00:00
David Rosca cd2562117a frontends/va: Parse more H264 PPS for transform_8x8_mode_flag 
Also use constrained_intra_pred_flag from pic params.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31020>
 2024-09-07 04:48:18 +00:00
Marek Olšák 1537b9355a ac,radeonsi: update comments related to the L2 cache, use "L2", not "TC" 
"GL2" is also OK. "TC-compatible" is also OK.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30869>
 2024-09-07 01:51:23 +00:00
Marek Olšák 1b94137039 ac/nir/meta: move the "skip compute if no DCC image stores" condition to common 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30869>
 2024-09-07 01:51:23 +00:00
Marek Olšák 5250128c6a ac: fix WAVES_PER_SH value for gfx12 
not a serious issue because we only use it for PRIME without SDMA IIRC

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30869>
 2024-09-07 01:51:23 +00:00
Alyssa Rosenzweig 1753bf599c ci: update traces 
🤕

thanks Mike

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig b7542c4390 nir: CSE comparisons in atan2 
Same code generated on AGX but simplified NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 7546ae96a7 nir: drop NaN fixup for atan 
this existed due to the min/max, per the comment. now that we don't do min/max,
the whole routine is NaN correct so the fixup is pointless.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Suggested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig ab8547a002 nir: push up abs in atan2 calculation 
everybody has abs on fmul, not everyone has abs on bcsel. should help agx and
bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 398e1ad46c nir: fuse ffma for atan range fixup 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 47e7cd268c nir: negate an expression in atan 
we're going to fix up the sign immediately anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 5318b8868b nir: simplify atan range reduction fixup 
the original version sure is creative.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 87b99d5797 nir: use copysign for atan 
this does two things:

* ignores sign of negative numbers which let us play fast and loose later in th
  series
* avoids an expensive fsign instruction in favour of a cheap bitwise op

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 95215a094a nir: extend copysign for no-integer hw 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 0a4a0df283 nir: push down fabs for atan 
worse in terms of NIR instruction count but lets the fabs fold easier. (on agx,
which has fabs on comparisons and fmul but not on bcsel. should be no worse if
ISA has fabs on all 3.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 8579375777 nir: simplify atan range reduction 
just implement what the comment says, don't be clever. the clever thing is worse
on all architectures i'm familiar with, because the fdiv will turn into
fmul+frcp.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig a32b1a975d nir: correct comment for atan range reduction 
the code did not match the comment, blew a sign.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 4fc3e34f2f nir: use Horner's method for atan 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 0c81a29db6 virgl: set no_integers 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig a52f606647 svga: set no_integers 
for vgpu9 but not 10

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 4b95fb2988 freedreno/a2xx: set no_integers 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 531538f678 etnaviv: set no_integers 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig f79f63f8b8 lima: set no_integers 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Boyuan Zhang 8bf7562416 radeonsi/vcn: fix loop filter across slices 
PPS header should use pps_loop_filter_across_slices_enabled_flag instead
of slice_loop_filter_across_slices_enabled_flag according to HEVC SPEC.

Slice header should also use pps_loop_filter_across_slices_enabled_flag
as one of the condition to determine if slice flag needs to be present.

V2: Apply pps_loop_filter_across_slices_enabled_flag to loop_filter as well
So modify loop_filter_across_slices_enabled value to be pps one instead

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31064>
 2024-09-06 22:48:17 +00:00
Mohamed Ahmed af15cceff4 nvk: Use stride in the explicit modifier case for linear images 
Fixes: f1fdffa1b2 (nvk: Support image creation with modifiers)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31045>
 2024-09-06 19:37:09 +00:00
Sil Vilerino fed08a4ac8 Fix definitions of PIPE_BIND_VIDEO_DECODE/ENCODE_DPB as they conflict with PIPE_BIND_SCANOUT and PIPE_BIND_SHARED 
Fixes: f8145fe691 ("pipe: Add PIPE_BIND_VIDEO_DECODE_DPB/PIPE_BIND_VIDEO_ENCODE_DPB")

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31067>
 2024-09-06 18:53:11 +00:00
Samuel Pitoiset eab5b453cd radv: fix allocating sparse descriptor buffers in the 32-bit addr space 
There are two bugs:
- VK_KHR_maintenance5 added VkBufferUsageFlags2CreateInfoKHR, so
checking for pCreateInfo->usage is incomplete
- this was also missing the usage flag for descriptor buffer with samplers

This fixes recent VKCTS coverage in
dEQP-VK.binding_model.descriptor_buffer.*.

Fixes: 059391b631 ("radv: use 32bit va range for sparse descriptor buffers")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31054>
 2024-09-06 18:27:37 +00:00
Mike Blumenkrantz b6f201b173 meson: require dri3 modifiers 
the year is 2024 and we have the technology

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31044>
 2024-09-06 17:34:17 +00:00
Tapani Pälli 0489df9a51 glsl: set a version to standalone compiler context 
Upcoming more strict context vs glsl version checks will fail otherwise.
Since standalone compiler requires ARB_ES3_2_compatibility that requires
GL 4.5 we simply set that as the context version.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31061>
 2024-09-06 14:32:33 +00:00
Tapani Pälli 62799fcdd5 iris: initialize pixel struct to zero when setting clear color 
Otherwise we can end up with uninitialized values, this fixes following
valgrind warning:

==71705== Uninitialised byte(s) found during client check request
==71705==    at 0x73B6DB8: util_bitpack_uint (bitpack_helpers.h:55)
==71705==    by 0x73B6DB8: GFX11_PIPE_CONTROL_pack (gen11_pack.h:19885)
==71705==    by 0x73B6DB8: iris_emit_raw_pipe_control (iris_state.c:10022)
==71705==    by 0x6F93386: iris_emit_pipe_control_write (iris_pipe_control.c:97)
==71705==    by 0x6FBCCAA: iris_resource_update_indirect_color (iris_resolve.c:1241)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30990>
 2024-09-06 13:19:04 +00:00
Tapani Pälli 39a1f53890 anv: initialize pixel struct to zero when setting clear color 
Otherwise we can end up with uninitialized values, this fixes following
valgrind warning:

==31283== Uninitialised byte(s) found during client check request
==31283==    at 0x503E4DE: anv_batch_bo_finish (anv_batch_chain.c:345)
==31283==    by 0x504220A: anv_cmd_buffer_end_batch_buffer (anv_batch_chain.c:1103)
==31283==    by 0x55A0E4F: end_command_buffer (genX_cmd_buffer.c:3455)
==31283==    by 0x55A0E82: gfx11_EndCommandBuffer (genX_cmd_buffer.c:3466)
==31283==    by 0x11233A: ??? (in /usr/bin/vkcube)
==31283==    by 0x10BDEE: ??? (in /usr/bin/vkcube)
==31283==    by 0x49B5149: (below main) (in /usr/lib64/libc.so.6)
==31283==  Address 0xc10c4d8 is 1,240 bytes inside a block of size 8,192 client-defined
==31283==    at 0x5036EF6: anv_bo_pool_alloc (anv_allocator.c:1284)
==31283==    by 0x503E0E1: anv_batch_bo_create (anv_batch_chain.c:262)
==31283==    by 0x5040D3F: anv_cmd_buffer_init_batch_bo_chain (anv_batch_chain.c:868)
==31283==    by 0x504F9C1: anv_create_cmd_buffer (anv_cmd_buffer.c:147)
==31283==    by 0x6B718C4: vk_common_AllocateCommandBuffers (vk_command_pool.c:206)
==31283==    by 0x4FB06B2: vkAllocateCommandBuffers (trampoline.c:1996)
==31283==    by 0x111E6B: ??? (in /usr/bin/vkcube)
==31283==    by 0x10BDEE: ??? (in /usr/bin/vkcube)
==31283==    by 0x49B5149: (below main) (in /usr/lib64/libc.so.6)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30990>
 2024-09-06 13:19:04 +00:00
Danylo Piliaiev 3886a3014d tu: Fix ZPASS_DONE having stale value with generic clear+early frag test 
If the next renderpass uses the same depth attachment, clears it
with generic clear - ZPASS_DONE may somehow read stale values that
are apparently invalidated by CCU_INVALIDATE_DEPTH.

Fixes:
 dEQP-VK.fragment_operations.early_fragment.sample_count_early_fragment_tests_depth_alpha_to_coverage_samples_2_maintenance5
 dEQP-VK.fragment_operations.early_fragment.sample_count_early_fragment_tests_depth_alpha_to_coverage_samples_4_maintenance5
 dEQP-VK.fragment_operations.early_fragment.sample_count_early_fragment_tests_depth_samples_2_maintenance5
 dEQP-VK.fragment_operations.early_fragment.sample_count_early_fragment_tests_depth_samples_4_maintenance5

When running them with TU_DEBUG=sysmem

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30858>
 2024-09-06 10:01:49 +00:00
Georg Lehmann 6ac576ceb0 radv/ci: update trace checksums 
Single pixel differences that are indistinguishable to my eyes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28676>
 2024-09-06 09:16:21 +00:00
Timur Kristóf 6e000d2817 radv: Determine linked I/O info after nir_opt_varyings. 
This makes it possible to not allocate I/O space
(such as LDS or VRAM) for I/O slots that were eliminated
by nir_opt_varyings.

Fossil DB stats on Rembrandt:

Totals from 896 (1.13% of 79395) affected shaders:
MaxWaves: 19452 -> 19488 (+0.19%)
Instrs: 443693 -> 443711 (+0.00%); split: -0.01%, +0.01%
CodeSize: 2331788 -> 2330904 (-0.04%); split: -0.04%, +0.01%
VGPRs: 43088 -> 42992 (-0.22%)
Inputs: 10344 -> 9198 (-11.08%)
Outputs: 7991 -> 6845 (-14.34%)
LDS: 3537408 -> 3184128 (-9.99%)
Latency: 1636786 -> 1636899 (+0.01%); split: -0.01%, +0.01%
InvThroughput: 359066 -> 358825 (-0.07%); split: -0.08%, +0.01%
VClause: 12106 -> 12109 (+0.02%); split: -0.02%, +0.05%
SClause: 6770 -> 6766 (-0.06%); split: -0.07%, +0.01%
Copies: 26532 -> 26540 (+0.03%); split: -0.02%, +0.05%
PreVGPRs: 32345 -> 32342 (-0.01%); split: -0.01%, +0.00%
VALU: 288476 -> 288501 (+0.01%); split: -0.00%, +0.01%
SALU: 44527 -> 44530 (+0.01%); split: -0.00%, +0.01%

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28676>
 2024-09-06 09:16:21 +00:00
Timur Kristóf 17f6ab28cc radv: Add new linking step and use nir_opt_varyings. 
The nir_opt_varyings pass is the new NIR solution for shader
linking, with new features including better I/O compaction,
packing 16-bit I/O, inter-stage code motion and more.

Fossil DB stats on Rembrandt:

Totals from 34585 (43.56% of 79395) affected shaders:
MaxWaves: 873362 -> 873260 (-0.01%); split: +0.11%, -0.12%
Instrs: 21543639 -> 21526956 (-0.08%); split: -0.27%, +0.19%
CodeSize: 115077568 -> 115015536 (-0.05%); split: -0.25%, +0.20%
VGPRs: 1465152 -> 1464192 (-0.07%); split: -0.29%, +0.22%
Inputs: 161776 -> 158711 (-1.89%); split: -1.90%, +0.00%
Outputs: 46532551993 -> 46532548680 (-0.00%); split: -0.00%, +0.00%
LDS: 70597120 -> 70794752 (+0.28%); split: -0.04%, +0.32%
Latency: 162963576 -> 162785055 (-0.11%); split: -0.25%, +0.14%
InvThroughput: 37356298 -> 37261700 (-0.25%); split: -0.37%, +0.12%
VClause: 427827 -> 427105 (-0.17%); split: -0.35%, +0.18%
SClause: 669989 -> 668623 (-0.20%); split: -0.36%, +0.15%
Copies: 1582166 -> 1582592 (+0.03%); split: -0.36%, +0.39%
Branches: 523203 -> 523789 (+0.11%); split: -0.04%, +0.15%
PreSGPRs: 1272992 -> 1273228 (+0.02%); split: -0.05%, +0.07%
PreVGPRs: 1164295 -> 1161623 (-0.23%); split: -0.43%, +0.20%
VALU: 13733432 -> 13714109 (-0.14%); split: -0.35%, +0.21%
SALU: 2828974 -> 2831841 (+0.10%); split: -0.12%, +0.22%
VMEM: 748396 -> 748500 (+0.01%); split: -0.16%, +0.18%
SMEM: 1263487 -> 1263329 (-0.01%); split: -0.03%, +0.02%

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28676>
 2024-09-06 09:16:21 +00:00
Timur Kristóf fcb2c62b63 radv: Add NIR XFB IO intrinsic info to legacy stages not just NGG. 
Some NIR passes (such as nir_opt_varyings) rely on having the
XFB info in explicit I/O intrinsics. If we want to use those,
we need to add this info.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28676>
 2024-09-06 09:16:21 +00:00
Timur Kristóf 79df320463 ac/nir: Move varying cost functions from radeonsi to common code. 
This code will be shared between RADV and RadeonSI.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28676>
 2024-09-06 09:16:21 +00:00
Samuel Pitoiset 5fd3be6f1b radv: stop relying on the VS for emitting VBO descriptors in DGC 
This is required for experimenting indirect graphics pipelines with DGC.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31040>
 2024-09-06 07:04:59 +00:00
Samuel Pitoiset 53c760c388 radv: pass vb_desc_usage_mask in radv_dgc_params 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31040>
 2024-09-06 07:04:59 +00:00
Samuel Pitoiset 4bd4f037b5 radv: emit all VBO descriptors in the prepare DGC shader 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31040>
 2024-09-06 07:04:59 +00:00
Samuel Pitoiset 8397e15019 radv: use radv_vbo_info for emitting descriptors with DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31040>
 2024-09-06 07:04:59 +00:00
Samuel Pitoiset a1646f468d radv: compute rsrc3 for VBO descriptors in NIR for DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31040>
 2024-09-06 07:04:59 +00:00
Samuel Pitoiset 91fdce3f5a radv: add a helper to get VBO info for emitting descriptors 
This will be used to rework VBO in DGC.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31040>
 2024-09-06 07:04:59 +00:00
Caio Oliveira ce9e2dbc62 vk/runtime: Allow "require full subgroups" for Mesh/Task 
Per description of VkPipelineShaderStageCreateFlags

```
  VK_PIPELINE_SHADER_STAGE_CREATE_REQUIRE_FULL_SUBGROUPS_BIT specifies
  that the subgroup sizes must be launched with all invocations active in
  the task, mesh, or compute stage.
```

Future CTS tests will use that.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31023>
 2024-09-06 05:49:07 +00:00