WSI extensions are implemented on the Venus driver side, layering on top
of external memory extensions. So we have to filter out WSI extensions
during device creation, otherwise the headless driver on the venus
renderer side can fail the device creation with _EXTENSION_NOT_PRESENT.
Fixes: 11195eb8de ("vulkan: Add KHR_swapchain_maintenance1 promotions.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38763>
Dynamic descriptors are mapped an array of offsets provided through
vkCmdBindDescriptorSets*() commands.
When pipelines are compiled with independent sets layouts, the
implementation might have to do additional runtime calculation to
figure out what offset in the contiguous array maps to what dynamic
descriptor in the pipeline layout.
For graphics pipelines you can always compute that information when
binding the shaders. There is always a limited amount of shaders (5
max).
For ray tracing pipelines, there could be lots of shaders to process
at every pipeline binding call. Besides there is no interface from the
runtime to the driver to list all the shaders used at the moment.
So do that tracking in the runtime and pass the information down to
the driver through the cmd_set_rt_state() vfunc.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 69a04151db ("vulkan/runtime: add ray tracing pipeline support")
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38678>
`comps <= (1 << subword_shift)` cannot be guarantee.
Here is an example:
```
8x2 %27 = @load_ssbo (%26 (0x1000001), %4) (access=readonly|reorderable, align_mul=2, align_offset=0, offset_shift=0)
8x2 %32 = ior %25, %31
32 %34 = ult32 %33 (0x7), %12
8x2 %35 = b32csel %34.xx, %27, %32
```
When processing `%34.xx` in `bi_emit_alu` (for `instr->src[0]`),
`comps` is computed from the instr definition (`%35`), but
`subword_shift` from the src bitsize.
In that case comps is greater than `1 << subword_shift`, but this is
supported by `bi_alu_src_index`.
This example is extracted from `dEQP-VK.spirv_assembly.type.vec2.i8.bit_field_insert_offset16_count16_comp`
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36638>
When v4i8 instruction are using to compute a v2i8, it puts the 2
result values in b0 & b2, thus we need to swizzle the destination to
have them in b0 & b1 as expected by the consumer of the v2i8 produced.
example: dEQP-VK.spirv_assembly.type.vec2.i8.mul_frag
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36638>
Otherwise, the following error is observed:
src/util/cache_ops_x86_clflushopt.c:40:22:
error: arithmetic on a pointer to void is a GNU extension [-Werror,-Wgnu-pointer-arith]
40 | void *end = start + size;
| ~~~~~ ^
src/util/cache_ops_x86_clflushopt.c:44:9:
error: arithmetic on a pointer to void is a GNU extension [-Werror,-Wgnu-pointer-arith]
44 | p += cpu_caps->cacheline;
| ~ ^
This works with GNU extension enabled, but does lead to warnings
with Clang.
v2: Add to trial_c + trial_cpp checks (Erik)
v3: use c_msvc_compat_args to avoid fixing other instances of this issue (Erik)
Fixes: 555881e574 ("util/cache_ops: Add some cache flush helpers")
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38752>
25.3.1 was planned for the day before the US Thanksgiving holiday, but
it slipped due to that holiday. The current plan puts 25.3.3 on
Christmas Eve, which will be missed for the same reason. To attempt to
fix this, I've updated the plan to move the missed release to this week,
with all releases re-aligned with that date. This moves the Christmas
Eve release to New Years Eve. We could possibly slip that by a week into
the new years as there is likely to be less work than normal done at
that time.
Due to the change in schedule I've removed one planned release, as we
should reach 25.3.Last and 26.0.1 at roughly the same time with one less
release.
Also update the last 25.2 release to match.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38757>
Fixes things like:
GfxStreamVulkanMapper.cpp:45:10:
error: no previous prototype for function 'chooseGfxQueueFamily'[-Werror,-Wmissing-prototypes]
Reviewed-by: David Gilhooley <djgilhooley.gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38751>
DXVK's DXGI implementation can create extra instances used for
enumerating physical devices besides the games' instance. When reserving
VMIDs for SPM, the DXGI instances may snatch the VMID reservation early,
making VMID reservation for the instance that actually needs it fail.
This starts being a problem on kernels 6.18+ where only one user may
reserve a VMID at a time.
Move reserving VMIDs to SQTT initialization inside vkCreateDevice so
that only the instances that actually create logical devices try
reserving VMIDs.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38746>
According to AV1 spec, force_integer_mv=1 on intra frames. However, VCN
FW does not expect integer mv to be set unless screen content tools are
enabled. This also aligns the code to the radeonsi logic.
Cc: mesa-stable
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38716>
When a vertex shader does not load any input attributes after any store
of output attributes, we can enable bit 25 of SPH ("ISBE space sharing")
Effectively this seems to allow input and output attributes to live in
the same allocated space in ISBE and could improve occupancy.
Found while researching geometry passthrough and mesh shaders.
Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38729>
Required so that uint array formats don't incorrectly wrap to last array
slice instead of the first one. For some reason this only happens with
uint texture formats while int and float formats work as expected.
Acked-by: Arcady Goldmints-Orlov <arcady@lunarg.com>
Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38713>
Since we only support 1 L0/L1 ref, the default num refs in the PPS
should always be 0. With that there never any need to set the override
flag in the slice header (until more references are supported).
Also the ref pic list modifications should be clamped to the size of the
ref pic list.
This fixes an issue seen with dEQP-VK.video.encode.h264.i_p_b_13_*.
Cc: mesa-stable
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38686>
Mel Henning