dbcdededb2
intel: Add missing dep of gen_*_header.py on utils.py.
...
Reviewed-by: Dylan Baker <dylan@pnwbakers.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14725 >
2022-02-02 11:21:57 -08:00
3d5ee08c15
freedreno/isaspec: Add missing dep of encode.py/decode.py calls on isa.py
...
Fixes : #5921
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14725 >
2022-02-02 11:21:56 -08:00
242c7a6513
anv: Add experimental support for VK_NV_mesh_shader
...
Enable setting ANV_EXPERIMENTAL_NV_MESH_SHADER=1 environment variable.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
d9416cd8bd
intel/dev: Enable Mesh Shading for DG2
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
da273b2b7b
anv: Put first few push constants directly into Task/Mesh InlineData
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
27c32fd14b
anv: include ClipDistance array in mesh shader per-vertex output
...
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
c95b4ac2eb
anv: tell the hardware about gl_[Clip|Cull]Distance in mesh shaders
...
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
bbde9f2448
anv: Implement indirect dispatch for Mesh pipeline
...
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
18e628135d
anv: Add support for UBOs, SSBOs and push constants in Mesh pipeline
...
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
f12f5ae2f8
anv: Add support for non-zero firstTask in vkCmdDrawMeshTasksNV
...
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
97da3e0814
anv: Enable conditional rendering in vkCmdDrawMeshTasksNV
...
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
ef04caea9b
anv: Implement Mesh Shading pipeline
...
The Mesh pipeline is implemented as a variant of the
regular (primitive) Graphics Pipeline.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
325ac235a7
anv: Add boilerplate for VK_NV_mesh_shader
...
Use minimum values for the properties.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
c93cbc77f7
intel/common: Add helper for URB allocation in Mesh pipeline
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
b01c73fd0a
intel: Add INTEL_URB_DEREF_BLOCK_SIZE_MESH
...
And corresponding value in XML.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
4c38229ac1
pan/va: Add ARM_shader_framebuffer_fetch asm test
...
This is a nontrivial chunk of code that makes for a nice dis/assembler test
case (and caught a bug already...). Add it to the observatory.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833 >
2022-02-02 17:42:01 +00:00
a99eac8a49
pan/va: Handle shift lanes in assembler
...
Noticed in a program using ARM_shader_framebuffer_fetch.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833 >
2022-02-02 17:42:01 +00:00
b3c7159308
pan/va: Add lots of swizzle assembler tests
...
The swizzle handling in ISA.xml was broken in a bunch of place. Now that
we've fixed these issues, let's add tons of tests to validate.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833 >
2022-02-02 17:42:01 +00:00
57bb3c7158
pan/va: Add 2-channel 8-bit swizzles for conversions
...
Instructions like V2S8_TO_V2S16 need a special 4-bit special selecting any two
bytes. The definition is the same as Bifrost. Let's call this a half-swizzle
since we need a name, and it is indeed half a swizzle...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833 >
2022-02-02 17:42:01 +00:00
cdb7c4e42d
pan/va: Vectorize 8->16-bit conversions
...
Matches Bifrost, too.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833 >
2022-02-02 17:42:01 +00:00
441c47ff74
pan/va: Fix lane select for [US]_TO_[USF]32
...
The lane select is in bit 28, this is covered by the "16-bit swizzle" mode.
However, the source type isn't inferred from the name in valhall.py, so
explicitly annotate the source as 16-bit.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833 >
2022-02-02 17:42:01 +00:00
46cd0ddcb6
pan/va: Fix MKVEC.v2i16 lane select
...
The lanes are at bit 28 and bit 26 respectively. This matches the 16-bit "swizzle" encoding. In general the handling of widens/swizzles/lane/lanes on Valhall is rather confused but... one problem at a time.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833 >
2022-02-02 17:42:01 +00:00
a95ca2402c
pan/va: Test LD_TILE assembly
...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833 >
2022-02-02 17:42:01 +00:00
dc61e362f4
pan/va: Add missing fields to LD_TILE
...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833 >
2022-02-02 17:42:01 +00:00
0f9007985d
pan/va: Add missing <clamp/> to V2F32_TO_V2F16
...
For parity with Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833 >
2022-02-02 17:42:01 +00:00
3fff018c98
pan/va: Add .absolute bit to BRANCHZI
...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833 >
2022-02-02 17:42:01 +00:00
665ffd4bf9
anv: Update VK_KHR_fragment_shading_rate for newer HW
...
Per primitive & attachment shading rate support added.
v2: Rebase on KHR_dynamic_rendering
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739 >
2022-02-02 17:09:46 +00:00
fc837e9f8b
anv/pass: rely on precomputed dynamic rendering pass/subpass more
...
For instance, the current code in genX_cmd_buffer.c assumes that the
depth/stencil attachments & resolves will be at the end of all
attachments, but that won't be the case anymore with fragment rate
shading.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739 >
2022-02-02 17:09:46 +00:00
16763e8b8e
anv: force primitive shading rate write in last geometry stage
...
v2: Use new helper to check if stage supports variable shading rate
setting
v3: Update comment & iterate backward (Caio)
Apply only to relevant platforms (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739 >
2022-02-02 17:09:46 +00:00
0cd93c59ef
intel/compiler: add primitive rate output support
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739 >
2022-02-02 17:09:46 +00:00
cebf284ac1
intel/compiler: add a new pass to lower shading rate into HW format
...
Rework:
* Jason: Modernize brw_nir_lower_shading_rate_output:
1. Use nir_shader_instructions_pass()
2. Use *_imm builder helpers.
3. Use nir_intrinsic_base() instead of ->const_index[0]
v2: Also lower loads (Caio)
v3: Update stage check to trigger lowering (Caio)
v4: Assert on != MESH (Caio)
v5: Fixup instruction insertion (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739 >
2022-02-02 17:09:46 +00:00
e227bb9fd5
nir/builder: add ishl_imm helper
...
v2: add (y >= x->bit_size) condition (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739 >
2022-02-02 17:09:46 +00:00
3ab7f4471c
isl: disable CPB surface compression
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739 >
2022-02-02 17:09:46 +00:00
dff08cbf8e
isl: add support for coarse pixel control surfaces
...
Those surfaces are used as attachment to rendering passes and describe
the rate of coarse pixel shading for the pass.
v2: Move CPB_BIT tile filtering to isl_gfx125_filter_tiling() (Nanley)
v3: Drop unused macro (Nanley)
s/isl_to_gen/isl_encode/ (Nanley)
Remove pitch alignment 128B constraint already covered by tiling (Nanley)
Move some asserts together (Nanley)
v4: Disable miptail for now (Nanley)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739 >
2022-02-02 17:09:46 +00:00
8d90fe587f
intel/dev: details CPS feature support
...
DG2 introduces per primitive coarse pixel settings (in stages
preceding the PS shader) and also a control surface specifying the
rate at through the resulting surface.
v2: update comment (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739 >
2022-02-02 17:09:46 +00:00
8bdbc93a9d
genxml: add new 3DSTATE_PS_EXTRA bit
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739 >
2022-02-02 17:09:46 +00:00
ea71fb0b4b
genxml: gen12.5 changes for CPS
...
v2: Make genxml look more like BSpec (Caio)
Fixup X_Focal/Y_Focal entries (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739 >
2022-02-02 17:09:46 +00:00
7d8884800e
compiler: add VARYING bit for primitive shading rate
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739 >
2022-02-02 17:09:46 +00:00
9322b76fc4
r300: replace recursive calls with loops
...
Recursive "loops" tend to be more difficult to follow
and understand. Additionally iterative approach should be
nicer for compiler. (Less to allocate on stack and easier to optimize)
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13226 >
2022-02-02 16:50:03 +00:00
f724f95542
intel/isl: Add more PRM text for HiZ/STC requirement
...
Add text describing why HierarchicalDepthBufferEnable must be set along
with SeparateStencilBufferEnable.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825 >
2022-02-02 16:25:10 +00:00
bc9ce9705c
intel/isl: Fix depth buffer TiledSurface programming
...
The assert for the TiledSurface field caught a programming error, but
with a segfault instead of the usual route of assert-failing. We only
set this field when we have a depth surface, but we also need to set it
when one isn't provided. Fix this issue and drop the assert.
Fixes: b77d694223https://gitlab.freedesktop.org/mesa/mesa/-/issues/5950
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825 >
2022-02-02 16:25:10 +00:00
146213d0ee
intel/isl: Simplify Z-buffer tiling config during emit
...
For SNB and prior, assert that the surface is Y-tiled and use constants
when configuring the tiling parameters. This makes a follow-on commit
clearer.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825 >
2022-02-02 16:25:10 +00:00
b41adbf211
venus: update venus-protocol to 1.3.204
...
There should be no visible functional change. Although an unrelated
change in the codegen replaced vn_info_extension_spec_version by
vn_info_extension_get. We have to adapt to that.
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org >
Reviewed-by: Ryan Neph <ryanneph@google.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14782 >
2022-02-02 06:57:24 +00:00
d4b6d03408
r300/r600: Add drm-shim support.
...
I was tired of swapping gpus around just to check shader-db results of MRs
for these. I put it in src/amd since it doesn't make sense in either of
r300 or r600.
Reviewed-by: Matt Turner <mattst88@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14809 >
2022-02-02 00:59:08 +00:00
be78087655
r300: Disable fp16 and int16 in swtcl vertex shaders.
...
We already had them disabled for hwtcl, but in the swtcl case gallivm's
param query would return (nir) support even though nir-to-tgsi couldn't
handle it because TGSI doesn't do fp16/int16.
Fixes: 7d2ea9b0edmattst88@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14809 >
2022-02-02 00:59:08 +00:00
965d58b058
anv: Report the right conformance version
...
Fixes: df8ac77af8dylan@pnwbakers.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14827 >
2022-02-01 14:36:18 -08:00
ea0fa5c6bc
anv: Handle resolveImageLayout on dynamic rendering
...
Fixes: 5d9e8bc9behttps://gitlab.freedesktop.org/mesa/mesa/-/issues/5942
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14812 >
2022-02-01 19:51:23 +00:00
cda3c22a01
zink: ARB_sparse_texture_clamp
...
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14813 >
2022-02-01 18:55:50 +00:00
1cadd19197
radv/winsys: fix missing buffer_make_resident() for the null winsys
...
With latest Fossilize everything should now be captured correctly
but without this, all Fossilize databases that need
VK_EXT_custom_border_color would just crash.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14821 >
2022-02-01 18:18:28 +00:00
8bab8f6422
compiler, intel: Add gl_shader_stage_is_mesh()
...
And replace the previous Intel-specific function.
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14823 >
2022-02-01 17:41:25 +00:00
Emma Anholt