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187396 Commits

Author SHA1 Message Date
Simon Ser d951ca056a lavapipe: replace dup() with os_dupfd_cloexec() 
dup() will leak the new FD into any child process after fork().

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26203>
 2025-02-26 00:45:51 +00:00
Simon Ser 0be6b65f41 iris: replace dup() with os_dupfd_cloexec() 
dup() will leak the new FD into any child process after fork().

Signed-off-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26203>
 2025-02-26 00:45:51 +00:00
Simon Ser bbb3069d05 freedreno: replace dup() with os_dupfd_cloexec() 
dup() will leak the new FD into any child process after fork().

Signed-off-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26203>
 2025-02-26 00:45:51 +00:00
Simon Ser 9859283aa0 pvr: replace dup() with os_dupfd_cloexec() 
dup() will leak the new FD into any child process after fork().

Signed-off-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26203>
 2025-02-26 00:45:51 +00:00
Sagar Ghuge 6f7a76e9d9 intel/compiler: Zero out the header for texel fetch 
It looks like even if we pass the header not present in the sampler descriptor,
it's not helping with the correct behavior of texelFetch.

Experiment on real HW shows that if we just zero out the header and include it
in the message, it helps with the correct behavior. I'm not sure if there is a
valid HW workaround for this one.

We can skip masking the sampler message header bits 4:0 but masking them out
doesn't hurt in this case.

Increasing number of parameter impact sampler performance, For example,
a sample message using 5 parameters will not be able to sustain the same
throughput as a sample message with only 4 valid parameters. We should
look out for any perf impact with respect to texel fetch.

This patch fixes ~3k tests involving texelFetch instruction on Xe3+

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33562>
 2025-02-26 00:23:49 +00:00
Alyssa Rosenzweig c0beb79145 hk: drop silly 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33743>
 2025-02-26 00:03:52 +00:00
Alyssa Rosenzweig c8ee0895e3 asahi: drop silly 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33743>
 2025-02-26 00:03:52 +00:00
Alyssa Rosenzweig 1100c2328a asahi: rename wip modifier 
this is gpu-tiled, not twiddled.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33743>
 2025-02-26 00:03:52 +00:00
Alyssa Rosenzweig 42bc9f6400 ail: split compression up 
this better describes the hw.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33743>
 2025-02-26 00:03:52 +00:00
Alyssa Rosenzweig 99e346ef15 ail: rename twiddled -> gpu tiled 
got the names flipped >_<

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33743>
 2025-02-26 00:03:52 +00:00
Lionel Landwerlin 91f36ba5b6 anv: fix missing 3DSTATE_PS:Kernel0MaximumPolysperThread programming 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 815d2e3e8b ("anv: move 3DSTATE_PS to partial packing")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33712>
 2025-02-25 23:42:01 +00:00
Benjamin Lee 3b5d5c072a panfrost: remove NIR_PASS_V usage for noperspective lowering 
The rest of the NIR_PASS_V usage in panfrost was dropped in
34beb93635, but this one was added in an
MR that was merged after.

Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>
Fixes: 081438ad39 ("panfrost: add nir pass to lower noperspective varyings")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33728>
 2025-02-25 23:17:43 +00:00
Caio Oliveira a030acd7c3 brw: Reformat brw_gram.y and brw_lex.l 
Change to use Mesa space indentation.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33739>
 2025-02-25 22:57:51 +00:00
Vasily Khoruzhick 2eb34c86f2 lima: ppir: add compactification pass 
If we have a single instruction that uses only combiner unit and previous
instruction doesn't use this unit, two instructions can be safely merged.

Implement compactification pass to do that.

The pass doesn't update instruction dependencies, so it should be run
right before codegen.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33570>
 2025-02-25 21:59:18 +00:00
Xaver Hugl 1433955420 vulkan/wsi: handle the compositor not supporting extended target volume better 
Instead of unconditionally ignoring the HDR metadata, just attempt to create the image
description, and if it fails, fall back to creating it without HDR metadata.

Signed-off-by: Xaver Hugl <xaver.hugl@kde.org>
Reviewed-by: Sebastian Wick <sebastian.wick@redhat.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32038>
 2025-02-25 21:24:11 +00:00
Xaver Hugl 4b663d561b vulkan/wsi: implement support for VK_EXT_hdr_metadata on Wayland 
Signed-off-by: Xaver Hugl <xaver.hugl@kde.org>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Sebastian Wick <sebastian.wick@redhat.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32038>
 2025-02-25 21:24:11 +00:00
Colin Marc 789507c99c vulkan/wsi: implement the Wayland color management protocol 
This allows applications to use color spaces other than sRGB, if the compositor
supports them.

The color management surface is only created if a non-sRGB and non-passthrough
colorspace is set on the surface, so applications can still use the protocol
directly if they prefer.

Co-authored-by: Xaver Hugl <xaver.hugl@kde.org>
Reviewed-by: Sebastian Wick <sebastian.wick@redhat.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32038>
 2025-02-25 21:24:11 +00:00
Georg Lehmann 9f40d06d2d radv: use nir_opt_phi_to_bool 
Foz-DB Navi21:
Totals from 5238 (6.60% of 79377) affected shaders:
MaxWaves: 112653 -> 112805 (+0.13%)
Instrs: 8008658 -> 8008518 (-0.00%); split: -0.18%, +0.18%
CodeSize: 42632748 -> 42650584 (+0.04%); split: -0.16%, +0.20%
VGPRs: 293296 -> 292672 (-0.21%); split: -0.22%, +0.01%
SpillSGPRs: 1958 -> 2066 (+5.52%); split: -0.66%, +6.18%
SpillVGPRs: 2934 -> 2896 (-1.30%)
Latency: 77959669 -> 77957296 (-0.00%); split: -0.10%, +0.10%
InvThroughput: 20650753 -> 20585680 (-0.32%); split: -0.39%, +0.08%
VClause: 164769 -> 164979 (+0.13%); split: -0.14%, +0.27%
SClause: 237718 -> 237731 (+0.01%); split: -0.03%, +0.03%
Copies: 643403 -> 634147 (-1.44%); split: -1.83%, +0.39%
Branches: 234353 -> 233990 (-0.15%); split: -0.30%, +0.15%
PreSGPRs: 291935 -> 293893 (+0.67%); split: -0.01%, +0.68%
PreVGPRs: 245802 -> 245241 (-0.23%); split: -0.23%, +0.00%
VALU: 5145144 -> 5133006 (-0.24%); split: -0.38%, +0.14%
SALU: 1178442 -> 1189578 (+0.94%); split: -0.19%, +1.13%
VMEM: 343288 -> 343994 (+0.21%); split: -0.02%, +0.23%
SMEM: 354275 -> 354273 (-0.00%); split: -0.00%, +0.00%

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33498>
 2025-02-25 20:38:09 +00:00
Georg Lehmann a237a3def8 nir/opt_algebraic: optimize b2i(a) != -b2i(b) 
Foz-DB Navi21:
Totals from 4 (0.01% of 79377) affected shaders:
Instrs: 881 -> 861 (-2.27%)
CodeSize: 4968 -> 4836 (-2.66%)
Latency: 6127 -> 6006 (-1.97%)
InvThroughput: 1128 -> 1068 (-5.32%)
VALU: 564 -> 534 (-5.32%)
SALU: 111 -> 121 (+9.01%)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33498>
 2025-02-25 20:38:09 +00:00
Georg Lehmann 4141043295 nir/opt_algebraic: optimize constant shift of DXBC booleans 
Can be combined with further iand.

Foz-DB Navi21:
Totals from 190 (0.24% of 79377) affected shaders:
Instrs: 100628 -> 100225 (-0.40%); split: -0.41%, +0.01%
CodeSize: 567828 -> 565884 (-0.34%); split: -0.35%, +0.00%
Latency: 968415 -> 968052 (-0.04%); split: -0.09%, +0.06%
InvThroughput: 285804 -> 285210 (-0.21%); split: -0.25%, +0.04%
VClause: 1959 -> 1958 (-0.05%)
Copies: 5696 -> 5711 (+0.26%)
PreSGPRs: 7567 -> 7569 (+0.03%)
VALU: 77161 -> 76751 (-0.53%); split: -0.54%, +0.01%
SALU: 7831 -> 7840 (+0.11%); split: -0.09%, +0.20%

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33498>
 2025-02-25 20:38:09 +00:00
Georg Lehmann 1e522e7d75 nir/opt_algebraic: optimize dxbc boolean not 
Foz-DB Navi21:
Totals from 237 (0.30% of 79377) affected shaders:
Instrs: 486690 -> 486146 (-0.11%); split: -0.11%, +0.00%
CodeSize: 2629516 -> 2626052 (-0.13%); split: -0.13%, +0.00%
VGPRs: 18744 -> 18736 (-0.04%)
Latency: 7404763 -> 7399806 (-0.07%); split: -0.07%, +0.01%
InvThroughput: 1800282 -> 1798388 (-0.11%); split: -0.11%, +0.00%
VClause: 12101 -> 12106 (+0.04%); split: -0.01%, +0.05%
Copies: 34225 -> 34170 (-0.16%); split: -0.21%, +0.05%
PreSGPRs: 14634 -> 14639 (+0.03%)
PreVGPRs: 16713 -> 16706 (-0.04%)
VALU: 317523 -> 316693 (-0.26%); split: -0.26%, +0.00%
SALU: 53814 -> 54097 (+0.53%); split: -0.38%, +0.90%

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33498>
 2025-02-25 20:38:09 +00:00
Georg Lehmann f9722e35be nir/opt_algebraic: optimize more boolean bcsel with constants 
Foz-DB Navi21:
Totals from 667 (0.84% of 79377) affected shaders:
Instrs: 3890980 -> 3886878 (-0.11%); split: -0.11%, +0.00%
CodeSize: 21088576 -> 21065848 (-0.11%); split: -0.11%, +0.00%
SpillSGPRs: 458 -> 446 (-2.62%); split: -3.49%, +0.87%
Latency: 26160728 -> 26162856 (+0.01%); split: -0.02%, +0.02%
InvThroughput: 6999254 -> 7000593 (+0.02%); split: -0.01%, +0.03%
VClause: 103745 -> 103743 (-0.00%)
SClause: 93113 -> 93109 (-0.00%)
Copies: 344097 -> 344794 (+0.20%); split: -0.05%, +0.25%
Branches: 134546 -> 134764 (+0.16%); split: -0.01%, +0.17%
PreSGPRs: 40677 -> 40298 (-0.93%); split: -0.93%, +0.00%
PreVGPRs: 40185 -> 40190 (+0.01%)
VALU: 2584477 -> 2584468 (-0.00%); split: -0.00%, +0.00%
SALU: 573587 -> 569353 (-0.74%); split: -0.75%, +0.01%
SMEM: 124794 -> 124790 (-0.00%)

v2 (idr): Remove a pattern that is made redundant by this commit
combined with the previous commit.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33498>
 2025-02-25 20:38:09 +00:00
Georg Lehmann 9785fa460c nir/opt_algebraic: optimize DXBC boolean bcsel 
Foz-DB Navi21:
Totals from 1749 (2.20% of 79377) affected shaders:
Instrs: 1695408 -> 1685149 (-0.61%); split: -0.68%, +0.07%
CodeSize: 9241312 -> 9174180 (-0.73%); split: -0.79%, +0.06%
VGPRs: 90688 -> 90664 (-0.03%); split: -0.04%, +0.01%
SpillSGPRs: 278 -> 298 (+7.19%)
Latency: 9560167 -> 9540386 (-0.21%); split: -0.29%, +0.08%
InvThroughput: 2236022 -> 2220411 (-0.70%); split: -0.72%, +0.02%
VClause: 29910 -> 29917 (+0.02%)
Copies: 146365 -> 145230 (-0.78%); split: -1.03%, +0.25%
Branches: 59545 -> 59560 (+0.03%)
PreSGPRs: 78858 -> 79242 (+0.49%); split: -0.10%, +0.59%
PreVGPRs: 78643 -> 78560 (-0.11%); split: -0.11%, +0.00%
VALU: 1127861 -> 1113990 (-1.23%); split: -1.24%, +0.01%
SALU: 249535 -> 253237 (+1.48%); split: -0.15%, +1.63%

v2 (idr): Remove a pattern that is now redundant.

v3 (idr): Don't undistribute ineg from bcsel. On platforms where ineg
is a free source modifier, this can be harmful.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33498>
 2025-02-25 20:38:09 +00:00
Georg Lehmann 674d970861 nir/opt_algebraic: 0 >= a -> 0 == a 
Foz-DB Navi21:
Totals from 2179 (2.75% of 79377) affected shaders:
MaxWaves: 40987 -> 40917 (-0.17%); split: +0.00%, -0.18%
Instrs: 5950981 -> 5949310 (-0.03%); split: -0.04%, +0.01%
CodeSize: 32120808 -> 32110328 (-0.03%); split: -0.04%, +0.00%
VGPRs: 141704 -> 141768 (+0.05%); split: -0.01%, +0.05%
SpillSGPRs: 1750 -> 1746 (-0.23%)
Latency: 56667295 -> 56562916 (-0.18%); split: -0.19%, +0.00%
InvThroughput: 13292128 -> 13288691 (-0.03%); split: -0.03%, +0.00%
VClause: 151845 -> 151755 (-0.06%); split: -0.06%, +0.00%
SClause: 172316 -> 172443 (+0.07%); split: -0.02%, +0.09%
Copies: 458724 -> 458951 (+0.05%); split: -0.08%, +0.13%
Branches: 195239 -> 195351 (+0.06%); split: -0.00%, +0.06%
PreSGPRs: 135304 -> 135317 (+0.01%); split: -0.01%, +0.02%
PreVGPRs: 122430 -> 122428 (-0.00%); split: -0.01%, +0.01%
VALU: 3924585 -> 3924062 (-0.01%); split: -0.02%, +0.01%
SALU: 820666 -> 819414 (-0.15%); split: -0.17%, +0.02%
SMEM: 247036 -> 247142 (+0.04%); split: -0.00%, +0.04%

v2 (idr): Remove a pattern that is now redundant. This was originaly
removed in a commit later in the MR.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33498>
 2025-02-25 20:38:09 +00:00
Georg Lehmann 000f14f7fd nir/opt_algebraic: optimize ineg(a) == #b 
No Foz-DB changes.

v2 (idr): Remove some patterns that are now redundant. These were
originally removed in a commit later in the MR.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33498>
 2025-02-25 20:38:08 +00:00
Georg Lehmann 3e4ac92298 nir/opt_algebraic: optimize ineg(a) == ineg(b) 
DXBC boolean cleanup.

Foz-DB Navi21:
Totals from 19 (0.02% of 79188) affected shaders:
Instrs: 9720 -> 9652 (-0.70%)
CodeSize: 54056 -> 53640 (-0.77%)
Latency: 95357 -> 94377 (-1.03%); split: -1.03%, +0.00%
InvThroughput: 17331 -> 16939 (-2.26%)
Copies: 604 -> 605 (+0.17%)
PreSGPRs: 832 -> 838 (+0.72%)
PreVGPRs: 701 -> 699 (-0.29%)
VALU: 6551 -> 6485 (-1.01%)
SALU: 893 -> 891 (-0.22%); split: -1.68%, +1.46%

v2 (idr): Remove a pattern that is now redundant. The version without
ineg already exists much earlier in the file. Search for b2iN.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33498>
 2025-02-25 20:38:08 +00:00
Georg Lehmann dd1a7f0e8c nir: add a pass to optimize phis to 1bit 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33498>
 2025-02-25 20:38:08 +00:00
Gurchetan Singh a5f5d26080 gallium: drop const qualifier on return type 
Observed the following error with -Werror enabled:

nir_to_tgsi.c:550:8: error: 'const' type qualifier on return type has no effect [-Werror,-Wignored-qualifiers]

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33741>
 2025-02-25 19:39:37 +00:00
Dylan Baker c33ebf09f5 iris: fix handling of GL_*_VERTEX_CONVENTION 
By actually setting the state packets according to the program data.
Also ensure that we correctly flag that the program may be dirty when
the geometry shader state changes

Fixes piglit tests: `spec@!opengl 3.2@gl-3.2-adj-prims * pv-first`

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Backport-to: 25.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33658>
 2025-02-25 19:18:25 +00:00
Dylan Baker 0477ee660f iris: Correctly set NOS for geometry shader state changes 
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Backport-to: 25.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33658>
 2025-02-25 19:18:25 +00:00
Vasily Khoruzhick aefe6cca8d lima: ci: update deqp CI expectations 
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33636>
 2025-02-25 18:51:56 +00:00
Vasily Khoruzhick 9c1a31cb55 lima: ppir: try scheduling root nodes into the same instruction 
Root nodes do not have dependencies, so it is safe to attempt scheduling
them into the same instruction

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33636>
 2025-02-25 18:51:56 +00:00
Vasily Khoruzhick d6987daef9 lima: ppir: introduce an optimizer 
Introduce an optimizer for ppir with 3 passes:

1) remove empty blocks: this one currently doesn't have any effect on
   code generation, but it's required by other passes
2) remove redundant mov that is generated for store_output intrinsic when
   possible
3) dead code elimination

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33636>
 2025-02-25 18:51:56 +00:00
Vasily Khoruzhick 0471b438d6 lima: ppir: assign an index for discard block 
Discard block is the only block that we generate internally, and it
currently just gets an index of 0 which collides with the very first
block. It is not an issue for compiler, but an eyesore for debug output
for a program with discard_if.

Assign INT_MAX index for it.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33636>
 2025-02-25 18:51:55 +00:00
Vasily Khoruzhick 8905ee3a03 lima: ppir: fix regalloc bugs 
Currently regalloc doesn't mark write destinations in the single
instructions as conflicting, as a result regalloc may assign the same
register to a multiple write destinations.

Before we started scheduling multiple root nodes into a single instruction
it was pretty much hidden. Fix it by marking destination registers as
conflicting if instruction has multiple writes.

Also stop handling a special case for output registers in regalloc and just
mark them as live in the last instruction of "stop" block(s)

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33636>
 2025-02-25 18:51:55 +00:00
Samuel Pitoiset c58655b999 vulkan: filter duplicate pNext struct at device creation 
Recently, Indiana Jones and The Great Circle messed up this by adding
duplicates and this was causing the game to crash at launch.

Of course, this was an application bug that VVL was also able to catch
but I think maybe Mesa should ignore those instead of failing to create
the logical device.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33705>
 2025-02-25 16:55:03 +00:00
Christian Gmeiner eb1f163848 zink/ntv: Only emit GeometryStreams cap if multiple streams are used 
From the SPIR-V spec:
  GeometryStreams: Uses multiple numbered streams for geometry-stage output.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33723>
 2025-02-25 16:20:04 +00:00
Pavel Ondračka 6b7b8738b3 r300: do not include newline in the error messages 
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33529>
 2025-02-25 15:57:35 +00:00
Pavel Ondračka 62507a2aa7 r300: forward all compile failures to state tracker 
Additionally an environment variable RADEON_DEBUG=dummysh is introduced
to force the old behavior, i.e., to just silently use a dummy shader (or
skip the draw altogether) instead.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33529>
 2025-02-25 15:57:35 +00:00
Pavel Ondračka 5e0369d8bb r300: stop reporting compile failures in finalize_nir 
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33529>
 2025-02-25 15:57:35 +00:00
Valentine Burley b88b7f9294 lavapipe: Update driverVersion 
Use vk_get_driver_version instead of hardcoding the driver version to 1.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Antonio Ospite <antonio.ospite@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33730>
 2025-02-25 14:14:54 +00:00
Samuel Pitoiset c3884f7f1e radv: reserve bits explicitly for cache key structs 
Having explicit reserved bits for those structs will make compiler
change backports easier and more robust regarding precompiled shaders
on SteamDeck.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33706>
 2025-02-25 13:52:18 +00:00
Zan Dobersek 710e74a082 tu: make tu_debug_flags enum 64-bit 
Soon tu_debug_flags will overgrow its 32-bit capacity. To avoid issues the
enum is resized to 64 bits and handling of these flag values is adjusted
accordingly.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Reviewed-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33663>
 2025-02-25 13:05:48 +00:00
Hans-Kristian Arntzen 13a3f9a972 radv: Always set 0 dispatch offset for indirect CS. 
Fixes severe glitching in Avowed.

Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33732>
 2025-02-25 12:17:11 +00:00
Erik Faye-Lund 21aa58e9b6 pan/bi: remove unused debug output 
There's no more users left of this switch or macro, so let's just get
rid of it.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33710>
 2025-02-25 11:08:24 +00:00
Erik Faye-Lund fee6e51c14 pan/bi: use unreachable instead of DBG + assert 
This error isn't particularly interesting to be able to toggle at
runtime. Let's just use the unreachable macro instead.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33710>
 2025-02-25 11:08:24 +00:00
Samuel Pitoiset 67c150bf9e radv: fix missing SQTT barriers for fbfetch color/depth decompressions 
SQTT layout transitions need to be inside SQTT barrier. Otherwise, this
throws an assertion in RADV and might also crash when the capture is
opened with RGP.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12664
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33719>
 2025-02-25 10:18:42 +00:00
Marek Olšák aff6b63d10 radeonsi: print why draws are rejected 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27736>
 2025-02-25 09:24:25 +00:00
Marek Olšák 695cd8f41a radeonsi: simplify bind_vertex_elements due to being before set_vertex_buffers 
The unaligned checking is unnecessary because si_bind_vertex_elements
always unbinds all vertex buffers.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27736>
 2025-02-25 09:24:25 +00:00
Marek Olšák c4414324a1 radeonsi: don't set num_vertex_buffers and don't unbind in set_vertex_buffers 
The number of bound vertex buffers is now always equal to the number of
used buffers in the vertex elements state even if some buffers are NULL.

set_vertex_buffers doesn't unbind [count..last_count-1] buffers anymore.
bind_vertex_elements_state does that. It lets us remove code from
si_set_vertex_buffers.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27736>
 2025-02-25 09:24:25 +00:00