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611 Commits

Author SHA1 Message Date
Jason Ekstrand 87efb9c3b3 intel/isl: Support Yf/Ys/Tile-64 in isl_surf_get_image_offset_sa 
All that's really needed here is to handle the array offsetting by using
an Z or array offset instead of the Y offset.

This patch originally changed get_image_offset_sa_gfx9_1d(), but since
we only use linear with the 1d case, it was dropped.

Rework:
 * Jordan: Include ISL_TILING_64 as well
 * Jordan: Drop change to get_image_offset_sa_gfx9_1d as
   recommended by Nanley

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21113>
 2023-03-22 08:32:52 +00:00
Eric Engestrom f5d3d1e7ed meson: inline gtest_test_protocol now that it's always 'gtest' 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21485>
 2023-03-10 07:20:29 +00:00
Tapani Pälli 5fdbc4a23e intel/isl: disable TILE64 for YCRCB formats 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21723>
 2023-03-09 13:50:39 +00:00
Daniel Stone daa1468b54 intel/isl: Don't scream FINISHME into logs for 3D vs. CCS 
This would probably be a nice optimisation to have, but it really does
make the CTS logs awful:
    https://gitlab.freedesktop.org/mesa/mesa/-/jobs/37692447

Just demote this isl_finishme() to a comment; given it's been unfinished
since 2019, we can probably live without it.

Fixes: 126c9562d9 ("isl: Redefine the CCS layout for Gen12")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21788>
 2023-03-09 01:36:54 +00:00
Faith Ekstrand 7e1b62ea5b isl: Set Depth to array len for 3D storage images 
This is necessary for RESINFO to work properly.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21376>
 2023-03-04 06:12:46 +00:00
Dylan Baker a0fa31bcdd intel/dev: create a helper dependency for libintel_dev 
This ensures that users of libintel_dev.a won't be compiled until
include files are generated, and that they are recompiled when the
header changes.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20825>
 2023-03-02 00:01:27 +00:00
Yonggang Luo 669a68489d meson: Use sse2_arg and sse2_args to replace usage of c and c_sse2_args 
And now c_sse2_arg and c_sse2_args are remvoed

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21375>
 2023-02-27 13:50:11 +00:00
David Heidelberg b52917f9fc intel: use c_see2_arg instead of explicit -msse2 
This allows us to also inherit `-mfpmath=sse` added in previous commit.

Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21371>
 2023-02-25 15:34:33 +01:00
Rohan Garg 80790f50db isl: fix some documentation 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21283>
 2023-02-14 16:55:21 +00:00
Jordan Justen 5df50292d6 intel/isl: Disable CCS on MTL until B0 (Wa_14017353530) 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20322>
 2022-12-15 11:43:00 -08:00
Jianxun Zhang 78a4b6deed intel/isl: Support 1MB alignment for AUX mapping 
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20259>
 2022-12-14 18:11:13 +00:00
Nanley Chery e4e4ba2304 intel: Allow CCS_E on R11G11B10_FLOAT for TGL+ 
We now support blorp_copy with this format.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19937>
 2022-12-14 03:05:24 +00:00
Nanley Chery e862626031 intel/isl: Bump format_info entries from 100 to 110 
The new format support is only tested on Ice Lake and onward. Makes the
next patch clearer.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19937>
 2022-12-14 03:05:24 +00:00
Nanley Chery 2b2141d193 intel/isl: Lessen CCS_E-compatibility checks for TGL+ 
Tiger Lake and onward allow drivers to specify a compression format
independently from the surface format. So, even if the surface format
changes, hardware is still able to determine how to access the CCS.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19937>
 2022-12-14 03:05:24 +00:00
Nanley Chery 2add57d0c2 intel: Hook up RENDER_SURFACE_STATE::DecompressInL3 
The sampler's decompressor seems to lack support for some types of
format re-interpretation. Use the more capable decompressor for these
cases. This will be needed to avoid regressing piglit's
arb_texture_view-rendering-formats in later commits.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19937>
 2022-12-14 03:05:24 +00:00
Lionel Landwerlin 89a550a37b isl: make Wa_1806565034 conditional to non robust access 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20280>
 2022-12-13 18:05:19 +00:00
Lionel Landwerlin 0626b68c88 isl: don't report I915_FORMAT_MOD_Y_TILED_CCS on Gfx8 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852>
 2022-12-02 09:18:16 +00:00
Aditya Swarup 6080dce4d8 intel/isl: Add MOCS settings for MTL platforms 
Add MOCS settings for Xe platforms based on cache settings for L3/L4
and display.

Rework:
 * Jordan: Use intel_device_info_is_mtl()

BSpec: 45101
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20045>
 2022-11-29 00:36:41 -08:00
Jordan Justen 4db33adf9d intel/isl: Disable CCS on MTL 
MTL requires some ccs/aux-map changes from Jianxun Zhang, which are
still in progress. So, for now we disable ccs on MTL.

Rework:
 * Drop change in isl_surf_supports_ccs (Nanley)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20046>
 2022-11-28 17:09:52 -08:00
Philippe Lecluse bd2dd03937 intel: Disable SSE2 instruction set if building for non x86 architectures 
Signed-off-by: Philippe Lecluse <philippe.lecluse@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19812>
 2022-11-23 16:57:23 +00:00
Matt Coster afb8308087 intel: Use common CONCAT/PASTE macros 
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16945>
 2022-11-15 11:54:42 +00:00
Matt Coster 7a84473344 intel: Unify naming of CONCAT/PASTE macros 
In isl/isl_priv.h:
 - __PASTE2 => PASTE2
 - __PASTE => CONCAT2

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Lionel Landwerlin <lionel.g.landwerlin@intel.com>

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16945>
 2022-11-15 11:54:42 +00:00
Lionel Landwerlin 4172596382 isl: add new MOCS field for protected buffers 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8092>
 2022-10-27 10:53:18 +00:00
Lionel Landwerlin 2db45f713a isl: avoid gfx version switch cases on the hot path 
Some of the surface state packing functions are called from the hot
path in Anv. We can use function pointers to avoid repeatedly going
through switch/case.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>
 2022-10-14 23:03:16 +00:00
Lionel Landwerlin d53682e1a9 intel/utrace: make blorp tracepoints more readable 
With the operation name and some formats.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17467>
 2022-09-21 12:38:34 +00:00
Lionel Landwerlin 4ab38112f3 anv: fixup assertions on lowered storage formats 
With VK_FORMAT_B10G11R11_UFLOAT_PACK32 in particular, we're seeing
applications create image views with swizzle = R,G,B,0

But since the format has no alpha channel, the swizzle value for it
does not matter for the equivalence we're trying to verify.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a9edc268b9 ("anv: validate image view lowered storage formats for storage")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18081>
 2022-08-23 08:29:51 +00:00
sjfricke 861167f41d isl: fix bug where sb.MOCS is not being set 
Currently the sb.MOCS is being reset to zero after struct init.

Signed-off-by: sjfricke <spencerfricke@gmail.com>
Fixes: c27fcb1d3b ("isl: Fill in MOCS for NULL depth, stencil, and HiZ buffers.")
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17985>
 2022-08-12 12:35:54 +00:00
Sagar Ghuge d4b2b769d1 intel/isl: Setting L1 caching policy to Write-back mode 
For a RW L1 cache, both reads and writes are cached in the L1, at high
priority (MRU position). For a RO L1 cache, reads are cached at higher
priority and writes bypass the cache.

v1: (Ken)
- Set caching policy for buffer surfaces too

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16905>
 2022-08-05 10:43:50 +03:00
Lionel Landwerlin ab4beaf3fb isl: add new helper for format component compatibility 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17329>
 2022-07-11 14:57:26 +00:00
Jason Ekstrand bc5e77a9f2 isl: Use util_sign_extend 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17214>
 2022-07-06 11:23:18 +00:00
Marcin Ślusarz f4386b81e6 intel: fix typos found by codespell 
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17191>
 2022-06-27 10:20:55 +00:00
Erik Faye-Lund df4fe7c4a2 intel/isl: remove needless c99_compat.h includes 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>
 2022-06-02 13:09:16 +00:00
Kenneth Graunke f052e00a58 isl: Add an isl_format_supports_typed_atomics() helper. 
v2: Add a fields in isl_format with per gen support (Lionel)

v3: Fixup R32_FLOAT from 80 to 90
    Fixup R32_[SU]INT from 80 to 70 (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14712>
 2022-06-01 10:05:19 +00:00
Jason Ekstrand faa51a10ed isl: Add some asserts about multisampled surfaces 
This isn't really necessary because the API doesn't allow MSAA and
mipmapping at the same time but people forget that pretty often so it's
good to have it as documentation if nothing else.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14129>
 2022-05-31 13:42:28 +00:00
Jason Ekstrand a19ed1f46a intel/isl: Add isl_view::min_lod_clamp for IVB+ 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14129>
 2022-05-31 13:42:28 +00:00
Nanley Chery b023f18bad isl,iris: Add DG2 CCS modifier support for XeHP 
Cc: 22.1 <mesa-stable>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14521>
 2022-04-28 20:02:14 +00:00
Nanley Chery a53abeb7fb intel/isl: Add a score for I915_FORMAT_MOD_4_TILED 
Enables the modifier in anv.

Cc: 22.1 <mesa-stable>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14521>
 2022-04-28 20:02:14 +00:00
Anuj Phogat ac441d0953 isl,iris: Add I915_FORMAT_MOD_4_TILED support for XeHP 
This patch adds Tile 4 modifier support to Mesa and allows Mesa to
use Tile 4 on gen12-hp with GBM.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: 22.1 <mesa-stable>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14521>
 2022-04-28 20:02:14 +00:00
Tapani Pälli d3ef3657b2 isl: disable mcs (and mcs+ccs) for color msaa on DG2 
Fixes lots of various test failures in:
   dEQP-VK.pipeline.multisample.min_sample_shading_disabled.*
   dEQP-GLES3.functional*multisample.*
   KHR-GL*sample_variables.*

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13991>
 2022-04-28 05:31:52 +00:00
Jason Ekstrand 257a20f40d intel/isl: Add a helper for swizzling color values 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15624>
 2022-04-04 21:42:23 +00:00
Mike Blumenkrantz 65ec846f77 intel/isl: fix 2d view of 3d textures 
according to KHR_gl_texture_3D_image:

    If <target> is EGL_GL_TEXTURE_3D_KHR, <buffer> must be the name of a
    complete, nonzero, GL_TEXTURE_3D (or equivalent in GL extensions) target
    texture object, cast
    into the type EGLClientBuffer.  <attr_list> should specify the mipmap
    level (EGL_GL_TEXTURE_LEVEL_KHR) and z-offset (EGL_GL_TEXTURE_ZOFFSET_KHR)
    which will be used as the EGLImage source; the specified mipmap level must
    be part of <buffer>, and the specified z-offset must be smaller than the
    depth of the specified mipmap level.

thus a 2d view of a 3d surface is not only legal, it's part of the spec and
must be supported when available

cc: mesa-stable

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15584>
 2022-03-29 21:44:51 +00:00
Kenneth Graunke 49dd707ca2 intel: Add INTEL_DEBUG=noccs alias for INTEL_DEBUG=norbc 
When CCS compression first came out on Skylake, we referred to it as
"renderbuffer compression", or RBC for short.  However, that name has
long since fallen out of favor, and we refer to it as CCS nearly
everywhere.

This patch renames DEBUG_NO_RBC to DEBUG_NO_CCS inside the codebase
for clarity, and adds INTEL_DEBUG=noccs.  The legacy INTEL_DEBUG=norbc
name continues to work, because it's one line of code and having both
names makes our lives easier in the interim.

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15447>
 2022-03-22 06:23:10 +00:00
Nanley Chery 85a7fb1e19 intel/isl: Add format assertions for surfaces using CCS 
This caught some invalid CCS surface states created by iris.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>
 2022-02-10 04:47:14 +00:00
Lionel Landwerlin 3ab7f4471c isl: disable CPB surface compression 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Lionel Landwerlin dff08cbf8e isl: add support for coarse pixel control surfaces 
Those surfaces are used as attachment to rendering passes and describe
the rate of coarse pixel shading for the pass.

v2: Move CPB_BIT tile filtering to isl_gfx125_filter_tiling() (Nanley)

v3: Drop unused macro (Nanley)
    s/isl_to_gen/isl_encode/ (Nanley)
    Remove pitch alignment 128B constraint already covered by tiling (Nanley)
    Move some asserts together (Nanley)

v4: Disable miptail for now (Nanley)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Nanley Chery f724f95542 intel/isl: Add more PRM text for HiZ/STC requirement 
Add text describing why HierarchicalDepthBufferEnable must be set along
with SeparateStencilBufferEnable.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
 2022-02-02 16:25:10 +00:00
Nanley Chery bc9ce9705c intel/isl: Fix depth buffer TiledSurface programming 
The assert for the TiledSurface field caught a programming error, but
with a segfault instead of the usual route of assert-failing. We only
set this field when we have a depth surface, but we also need to set it
when one isn't provided. Fix this issue and drop the assert.

Fixes: b77d694223 ("intel/isl: Allow HiZ with Tile4/64 surfaces")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5950
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
 2022-02-02 16:25:10 +00:00
Nanley Chery 146213d0ee intel/isl: Simplify Z-buffer tiling config during emit 
For SNB and prior, assert that the surface is Y-tiled and use constants
when configuring the tiling parameters. This makes a follow-on commit
clearer.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
 2022-02-02 16:25:10 +00:00
Nanley Chery 7f46e569e5 intel/isl: Support the XeHP media compression format 
The format on this platform is slightly different from the one used on
TGL. Also it's part of the surface state instead of an aux-map.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14355>
 2022-01-28 00:30:55 +00:00
Nanley Chery fde43bb194 intel: Rename a RenderCompressionFormat field 
The name of the bit field is CompressionFormat. The format subsections
of the field specify the alternate names of RenderCompressionFormat or
MediaCompressionFormat depending on the compression type.

We're going to start programming this field for media compression, so
we'd like to use either the bit field name or a new
MediaCompressionFormat field. Either option seems fine, so we go with
the first.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14355>
 2022-01-28 00:30:55 +00:00