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Author SHA1 Message Date
Qiang Yu 6c44d92362 ac/llvm,radeonsi: lower attribute ring intrinsics in nir 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010>
 2022-12-02 07:34:32 +00:00
Qiang Yu daaa8ddb8e ac/llvm,radeonsi: lower nir primitive counter add intrinsics 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010>
 2022-12-02 07:34:31 +00:00
Qiang Yu bb837bf6ef nir,ac/llvm: add nir_buffer_atomic_add_amd 
Used by radeonsi for lower nir_atomic_add_gen/xfb_prim_count_amd.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010>
 2022-12-02 07:34:31 +00:00
Qiang Yu 7cec2e7520 ac/llvm,radeonsi: lower nir_load_streamout_buffer_amd 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010>
 2022-12-02 07:34:31 +00:00
Qiang Yu daf5d30b59 ac/llvm,radeonsi: lower nir_load_user_clip_plane in abi 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010>
 2022-12-02 07:34:31 +00:00
Qiang Yu 84abc307a5 ac/llvm: remove lowered abi->intrinsic_load() intrinsics 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010>
 2022-12-02 07:34:31 +00:00
Qiang Yu 2a5fcf42c9 radeonsi: remove si_llvm_load_intrinsic intrinsics lowered 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010>
 2022-12-02 07:34:31 +00:00
Qiang Yu a5bd39c7ed radeonsi: add si_nir_lower_abi pass 
This pass is for lower intrinsics to driver spec nir instructions,
so that each compiler backend don't need to implement their own.
Like radv_nir_lower_abi().

Currently only lower intrinsics in si_llvm_load_intrinsic().

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010>
 2022-12-02 07:34:31 +00:00
Qiang Yu e9f08d8193 ac/nir: add ac_nir_unpack_arg 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010>
 2022-12-02 07:34:31 +00:00
Qiang Yu 8030fbcf16 nir,ac/llvm: add nir_load_smem_buffer_amd 
Used by radeonsi to load const buffer.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010>
 2022-12-02 07:34:31 +00:00
Qiang Yu 73ea7d651a ac/llvm: nir_load_smem_amd support 32bit base address 
For radeonsi which use 32bit address in ac_build_load_to_sgpr().

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010>
 2022-12-02 07:34:31 +00:00
Qiang Yu 0007c10c1e radeonsi: separate shader args from llvm 
Move shader args out of llvm context, so that we can init
it before get nir. This is for creating a nir lower abi pass
which load args directly in nir.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010>
 2022-12-02 07:34:31 +00:00
Qiang Yu 003cbddfee radeonsi: use native shader info when init streamout args 
We are going to init shader args earlier, there is no such
pipe_stream_output_info when that time.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010>
 2022-12-02 07:34:31 +00:00
Alyssa Rosenzweig c445c29263 asahi: Use PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY 
The hardware only supports aligned loads and stores. That applies to vertex
buffer loads as well. As such, we need to ensure that the base address of vertex
buffers, the stride, and the offset are all aligned to the vertex buffer format,
ensuring that the load itself is aligned. Mesa has a CAP for that,
PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY, which ensures that these conditions
are met and will rewrite a vertex buffer on the CPU in the off chance that
they're not.

This is a bug fix compared to the old code, because it requires that offsets and
base addresses are aligned (not just the strides like before). It's also an
optimization compared to the old code, because it does not require 4 byte
alignment for 8-bit and 16-bit formats. In fact, it doesn't require any
alignment for 8-bit formats. This will avoid needless CPU work for smaller
formats.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19996>
 2022-12-02 06:25:20 +00:00
Alyssa Rosenzweig 8dcf7648f1 agx: Lower VBOs in NIR 
Now we support all the vertex formats! This means we don't hit u_vbuf for format
translation, which helps performance in lots of applications. By doing the
lowering in NIR, the vertex fetch code itself can be optimized by NIR (e.g.
nir_opt_algebraic) which can improve generated code quality.

In my first implementation of this, I had a big switch statement mapping format
enums to interchange formats and post-processing code. This ends up being really
unwieldly, the combinatorics of bit packing + conversion + swizzles is
enormous and for performance we want to support everything (no u_vbuf
fallbacks). To keep the combinatorics in check, we rely on parsing the
util_format_description to separate out the issues of bit packing, conversion,
and swizzling, allowing us to handle bizarro formats like B10G10R10A2_SNORM with
no special casing.

In an effort to support everything in one shot, this handles all the formats
needed for the extensions EXT_vertex_array_bgra, ARB_vertex_type_2_10_10_10_rev,
and ARB_vertex_type_10f_11f_11f_rev.

Passes dEQP-GLES3.functional.vertex_arrays.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19996>
 2022-12-02 06:25:20 +00:00
Alyssa Rosenzweig fb49715a2c agx: Lower UBOs in NIR 
Simpler than lowering in the backend and makes the sysvals obvious in the NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19996>
 2022-12-02 06:25:20 +00:00
Alyssa Rosenzweig 6b4ed663a8 agx: Implement 8-bit sign extensions 
Long term, I think having i2i16 and i2i32 available with 8-bit sources should
make lowering the rest of 8-bit away a bit easier. Short term, this avoids
special casing 8-bit in the VBO lowering code.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19996>
 2022-12-02 06:25:20 +00:00
Alyssa Rosenzweig 8127737c1e agx: Allow some 8-bit sources 
8-bit sources are useful for int8->float32 conversions, which we can do in a
single hardware instruction.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19996>
 2022-12-02 06:25:20 +00:00
Alyssa Rosenzweig ba209fe493 agx: Implement formatted loads 
These will be generated by the UBO and VBO lowerings. (and eventually by other
lowerings too?)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19996>
 2022-12-02 06:25:20 +00:00
Alyssa Rosenzweig 580f25a266 agx: Add shift to device_load 
We'll use this as an optimization soon. This acts in addition to the format's
shift.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19996>
 2022-12-02 06:25:20 +00:00
Alyssa Rosenzweig 19a0db31eb asahi: Use NIR_PASS_V for agx_nir_lower_tilebuffer 
This ensures that printing shaders before and after the NIR pass still works
with the standard NIR debug options.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19996>
 2022-12-02 06:25:20 +00:00
Alyssa Rosenzweig 0af08acca5 nir: Add intrinsics for lowering UBOs/VBOs on AGX 
We'll use formatted loads and some system values to lower UBOs and VBOs to
global memory in NIR, using the AGX-specific format support and addressing
arithmetic to optimize the emitted code.

Add the intrinsics and teach nir_opt_preamble how to move them so we don't
regress UBO pushing.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19996>
 2022-12-02 06:25:20 +00:00
Lionel Landwerlin a855bdbf47 intel/nir/rt: switch to workgroup_id_zero_base 
RT don't use a base workgroup id so no reason of using workgroup_id.
Additionally the lowering introduced in b4dd3df227 requires something
provides base_workgroup_id which we don't have for RT as it's not
needed.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b4dd3df227 ("intel/nir: Set has_base_workgroup_id for lower_compute_system_values")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7812
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20115>
 2022-12-02 05:25:22 +00:00
Qiang Yu da4f49d0ad radeonsi: cleanup si_llvm_build_vs_exports gfx11 code 
It's now completely handled in ac_nir_lower_ngg.c
export_vertex_params_gfx11.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
 2022-12-02 04:37:23 +00:00
Qiang Yu 9b2ec290c4 ac/llvm: remove unused llvm cull 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
 2022-12-02 04:37:23 +00:00
Qiang Yu f758ffccb8 radeonsi: remove unused ngg llvm code 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
 2022-12-02 04:37:23 +00:00
Qiang Yu 853436bacd radeonsi: replace llvm ngg gs with nir lowering 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
 2022-12-02 04:37:23 +00:00
Qiang Yu 028d0590f8 radeonsi: replace llvm ngg vs/tes with nir lowering 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
 2022-12-02 04:37:23 +00:00
Qiang Yu 3542d5ce6b radeonsi: fix NGG VS primitive ID load 
When NGG VS need to export primitive ID, it will load it in GS
threads, so need to use gs_prim_id arg. Current nir to llvm
translator check vs_prim_id present to use vs_prim_id first.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
 2022-12-02 04:37:23 +00:00
Qiang Yu 7e1b804992 radeonsi: implement two lds base load intrinsics 
LDS will be accessed starting from esgs_ring which has offset 0.
So ngg_scratch and ngg_emit base address is just the offset from
the esgs_ring base.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
 2022-12-02 04:37:23 +00:00
Qiang Yu 7bc56911f8 radeonsi: implement export_vertex abi 
Used by ngg lower.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
 2022-12-02 04:37:23 +00:00
Qiang Yu 6cbb6e6397 radeonsi: implement nir_intrinsic_load_provoking_vtx_in_prim_amd 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
 2022-12-02 04:37:23 +00:00
Qiang Yu 3c1ebebeae radeonsi: use nir_lower_gs_intrinsics 
Replace some llvm code.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>
 2022-12-02 04:37:23 +00:00
David Heidelberg 224e9ce4a8 ci/zink: add missing spec@!opengl 1.1@masked-clear flake 
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20119>
 2022-12-02 03:16:31 +00:00
Giancarlo Devich d3753aa336 wgl: Fix build break when LLVMPIPE and SOFTPIPE are both off 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20114>
 2022-12-02 02:12:06 +00:00
Eric Engestrom 8140eca23b meson: replace deprecated meson.get_cross_property(...) with meson.get_external_property(...) 
According to the deprecation note:
> It's a pure subset of meson.get_external_property, and works strangely
> in host == build configurations, since it would be more accurately
> described as get_host_property.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19904>
 2022-12-01 22:09:55 +00:00
Rhys Perry 9b6ab40b3b aco: improve do_pack_2x16() with zero constants 
We can skip the v_or_b32 or use an instruction smaller than
v_alignbyte_b32.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19933>
 2022-12-01 21:43:28 +00:00
Rhys Perry 917cfd587c aco: use v_minmax/v_maxmin opcodes 
fossil-db (gfx1100):
Totals from 29868 (22.12% of 135032) affected shaders:
MaxWaves: 741336 -> 741344 (+0.00%)
Instrs: 34624902 -> 34539766 (-0.25%); split: -0.25%, +0.00%
CodeSize: 187196804 -> 187192100 (-0.00%); split: -0.01%, +0.01%
VGPRs: 1816860 -> 1816788 (-0.00%); split: -0.01%, +0.01%
Latency: 502597202 -> 502245627 (-0.07%); split: -0.08%, +0.01%
InvThroughput: 84813176 -> 84586122 (-0.27%); split: -0.28%, +0.01%
VClause: 633826 -> 633749 (-0.01%); split: -0.02%, +0.01%
SClause: 1317738 -> 1317047 (-0.05%); split: -0.06%, +0.01%
Copies: 2130610 -> 2130954 (+0.02%); split: -0.03%, +0.05%
Branches: 766093 -> 765969 (-0.02%); split: -0.02%, +0.00%
PreSGPRs: 1630250 -> 1630034 (-0.01%); split: -0.02%, +0.00%
PreVGPRs: 1590777 -> 1590664 (-0.01%); split: -0.01%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19933>
 2022-12-01 21:43:28 +00:00
Rhys Perry dfbc8e0192 aco: change order in combine_minmax() 
Prepare for future optimizations.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19933>
 2022-12-01 21:43:28 +00:00
Rhys Perry ce5838599d aco/gfx11: use v_cvt_i32_i16/v_cvt_u32_u16 
fossil-db (gfx1100):
Totals from 52753 (39.07% of 135032) affected shaders:
CodeSize: 153603860 -> 153163384 (-0.29%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19933>
 2022-12-01 21:43:28 +00:00
Danylo Piliaiev 8f0177b334 ir3: Reduce the maximum allowed imm offset for shared var load/store 
STL/LDL have 13 bits to store imm offset. However the most significant
bit in the offset is a sign bit, so the positive offset is limited by
12 bits.

nir_opt_offsets only has the upper limit and doesn't deal with
negative offsets, so shared_max should be changed to `(1 << 12) - 1`.

The issue was found in "Monster Hunter: World".

Fixes: 0b2da9d795
("ir3: Limit the maximum imm offset in nir_opt_offset for shared vars")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20100>
 2022-12-01 18:52:01 +00:00
Connor Abbott 96ec79c7e3 tu: Don't prefetch descriptors for inline uniforms 
This could result in hangs if the entire descriptor set was inline
uniforms. Fixes
dEQP-VK.binding_model.descriptorset_random.sets4.dynindexed.ubolimitlow.nosbo.nosampledimg.outimgonly.iublimitlow.nouab.comp.noia.0
after 0a0a04bd made us prefetch descriptors again and uncovered this.

Fixes: 37cde2c6 ("tu: Rewrite inline uniform implementation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20101>
 2022-12-01 18:28:05 +00:00
Jasber Chen 1d3cb3f188 frontends/va: partially updating RefPicList depends on slice type 
problem casused by one frame with multiple slices and different slices type.
Invalid referenced values came from slice P/I would overwrite previous update.

Signed-off-by: Jasber Chen <yipeng.chen@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19943>
 2022-12-01 18:14:23 +00:00
Chia-I Wu c0346ac170 Revert "freedreno/a6xx: Remove unneeded MSAA clear fallback" 
This reverts commit ded82cf4bd and fixes

$ deqp-gles31 --deqp-gl-config-name=rgba8888d24s8ms4 \
    -n dEQP-GLES31.functional.primitive_bounding_box.depth.*

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20085>
 2022-12-01 17:35:42 +00:00
Samuel Pitoiset ab7f518ed0 radv,driconf: fix static driconf by parsing 00-radv-defaults.conf 
Otherwise when xmlconfig is disabled, drirc workarounds aren't applied
with RADV.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7785
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20077>
 2022-12-01 16:55:31 +00:00
Samuel Pitoiset 60ff0df39b driconf: add support for multiple input files in the static script 
RADV has its own drirc file and this is required to fix the static
driconf path.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20077>
 2022-12-01 16:55:31 +00:00
Jordan Justen 686ada78cd intel/dev: Add (disabled) device info for MTL 
Reworks:
 * Jordan: INTEL_PLATFORM_MTL_M/INTEL_PLATFORM_MTL_P
 * Lionel: .has_coarse_pixel_primitive_and_cb
 * Jordan: .has_mesh_shading & .has_ray_tracing
 * Paulo: .has_64bit_float
 * José: .has_integer_dword_mul (BSpec: 47431)
 * Jordan: Comment pci device ids for now similar to DG2:
   * 70a4e64685 ("intel: Add *disabled* device ids for DG2")
   * ad565f6b70 ("intel/dev: Enable first set of DG2 PCI IDs")

Ref: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/drm/i915_pciids.h?h=v6.0-rc4#n736
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19658>
 2022-12-01 16:22:47 +00:00
Matt Coster d5740d85c4 pvr: debug: Print hexdump at the end of all sub buffers 
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20040>
 2022-12-01 15:05:59 +00:00
Matt Coster b530a6b055 pvr: debug: Add option to zero-alloc all buffer objects 
This is designed for use by the control stream dump debug option, but
can also be used any time deterministic buffer state is desired.

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20040>
 2022-12-01 15:05:59 +00:00
Matt Coster eb44597c2c pvr: debug: Print hexdump for referenced buffers with unknown encoding 
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20040>
 2022-12-01 15:05:59 +00:00