AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
123,981 Commits 1 Branch 0 Tags
d15369332ff400aabb008f9990f7b990b3c8643e
Commit Graph

5550 Commits

Author SHA1 Message Date
Lionel Landwerlin d15369332f intel/perf: compute number of passes for a set of counters 
We want to compute the number of passes required to gather performance
data about a set of counters.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin 3f0c4c2afe intel/perf: create a unique list of counters 
For a future extension we want to be able to list the counters. Our
existing sets counters might contain the same counters multiple times.
This is a side effect of the fixed OA counters in the HW. We track
thoses with a mask so that we know when a counter is available from
multiple metrics.

v2: Use BITFIELD64_BIT() (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin 65d242ff5e intel/perf: update generated code to ralloc all data 
Previously counter descriptions as well register values were written
in global static variables. This isn't really thread safe so instead
ralloc all the data back under the gen_perf_config object.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin a683e7f3dc intel/perf: store the appropriate OA formats in queries 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin 8b8eaa84a3 intel/perf: make pipeline statistic query loading optional 
On Vulkan most of those are already covered by standard queries so
add the ability to skip them.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin cc13bfbd05 intel/genxml: add PIPE_CONTROL command cache invalidate bit 
This new bit invalidates the cache/prefetch of commands in the command
streamer. This will be useful for self modifying batches.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin 34a0ce58c7 anv: add a new execution mode for secondary command buffers 
This change adds a call/return execution mode for secondary command
buffer rather than the existing copy into the primary batch mode.

v2: Rework convention to avoid burning an ALU register (Jason)

v3: Use anv_address_add() (Jason)

v4: Move command emissions to anv_batch_chain.c (Jason)

v5: Also move last MI_BBS emission in secondary command buffer to
    anv_batch_chain.c (Jason)

v6: Fix end secondary command buffer end (Jason)

v7: Refactor anv_batch_address() to remove additional emit functions

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin a96d92a689 anv: don't reserve a particular register for draw count 
By using the same mi_builder throughout the draw call, we can just
allocate a register from the mi_builder and unref it when we're done.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin 796fccce63 intel/mi-builder: add framework for self modifying batches 
v2: Use Jason's idea to store addresses to modify

v3: Add ALU flushes (Jason)

v4: Remove ALU flush from gen_mi_self_mod_barrier() (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v2)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin 570bd760d3 intel/genxml: fix bits generation for MI_LOAD_REGISTER_IMM 
This instruction has a group with the same name than another field above :

  <field name="Data DWord" start="64" end="95" type="uint"/>
  <group count="0" start="96" size="64">
    <field name="Register Offset" start="2" end="22" type="offset"/>
    <field name="Data DWord" start="32" end="63" type="uint"/>
  </group>

The script was replacing the offset of the field first with the second
one in the group.

This change ignore anything a group within an instruction.

v2: Drop unused variable (Rafael)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:26 +03:00
Ian Romanick fec36c0668 intel/drm-shim: Return correct values for I915_PARAM_HAS_ALIASING_PPGTT 
It sure looks like it should be a Boolean value, but it's not.  The
values that we really want for later platforms are either 2 or 3.  The
old intel_stub.c in shader-db just always returns 3
(I915_GEM_PPGTT_FULL).  This returns the same set of values per platform
that kernel 5.6.13 would.

When using the shim for ICL with i965 driver, this fixes:

    i965 requires softpin (Kernel 4.5) on Gen10+.

Fixes: 0f4f1d70bf ("intel: add stub_gpu tool")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5061>
 2020-05-19 18:55:29 +00:00
Ian Romanick c8635b6fd3 intel/drm-shim: Add noop ioctl handler for set_tiling 
When using the shim for HSW and earlier, this fixes:

    DRM_SHIM: unhandled driver DRM ioctl 33 (0xc0106461)

Fixes: 0f4f1d70bf ("intel: add stub_gpu tool")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5061>
 2020-05-19 18:55:29 +00:00
Jason Ekstrand 164aed6c81 anv:gpu_memcpy: Emit 3DSTATE_VF_INDEXING on Gen8+ 
If this gets run right after something which uses
VK_VERTEX_INPUT_RATE_INSTANCE on its first vertex binding, we could end
up in serious trouble.

Fixes: 3d9747780b "anv: Add a helper for doing buffer copies with..."

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5090>
 2020-05-18 21:42:05 +00:00
Caio Marcelo de Oliveira Filho 6a6c36e977 intel/fs: Use writes_memory from shader_info 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4815>
 2020-05-18 21:09:17 +00:00
Rafael Antognolli bb3545a6ee intel: Store the aperture size in devinfo. 
We will later use the devinfo from iris_bufmgr, where we don't have
access to the screen pointer. And since we are moving it, we can reuse
it in Anv and i965.

v2: return error code and check for it on Anv (Lionel).
v3: Remove anv_gem_get_aperture() from anv_private.h and stubs (Lionel).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5043>
 2020-05-15 16:57:04 +00:00
Ian Romanick ceae09da15 intel: Silence unused parameter warning in __intel_log_use_args 
...in every file that includes intel_log.h.

In file included from src/intel/vulkan/anv_private.h:93,
                 from src/intel/vulkan/genX_cmd_buffer.c:27:
src/intel/common/intel_log.h: In function ‘__intel_log_use_args’:
src/intel/common/intel_log.h:75:34: warning: unused parameter ‘format’ [-Wunused-parameter]

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4994>
 2020-05-14 16:47:08 +00:00
Ian Romanick 4cb2330e56 anv: Silence unused parameter warning in anv_image_get_clear_color_addr 
...in every file that includes anv_private.h.

In file included from src/intel/vulkan/genX_cmd_buffer.c:27:
src/intel/vulkan/anv_private.h: In function ‘anv_image_get_clear_color_addr’:
src/intel/vulkan/anv_private.h:3690:57: warning: unused parameter ‘device’ [-Wunused-parameter]

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4994>
 2020-05-14 16:47:08 +00:00
Ian Romanick b44eb50f2d anv/tests: Silence unused parameter warnings in main 
src/intel/vulkan/tests/block_pool_no_free.c: In function ‘main’:
src/intel/vulkan/tests/block_pool_no_free.c:147:14: warning: unused parameter ‘argc’ [-Wunused-parameter]
src/intel/vulkan/tests/block_pool_no_free.c:147:27: warning: unused parameter ‘argv’ [-Wunused-parameter]

src/intel/vulkan/tests/block_pool_grow_first.c: In function ‘main’:
src/intel/vulkan/tests/block_pool_grow_first.c:27:14: warning: unused parameter ‘argc’ [-Wunused-parameter]
src/intel/vulkan/tests/block_pool_grow_first.c:27:27: warning: unused parameter ‘argv’ [-Wunused-parameter]

src/intel/vulkan/tests/state_pool.c: In function ‘main’:
src/intel/vulkan/tests/state_pool.c:36:14: warning: unused parameter ‘argc’ [-Wunused-parameter]
src/intel/vulkan/tests/state_pool.c:36:27: warning: unused parameter ‘argv’ [-Wunused-parameter]

src/intel/vulkan/tests/state_pool_padding.c: In function ‘main’:
src/intel/vulkan/tests/state_pool_padding.c:27:14: warning: unused parameter ‘argc’ [-Wunused-parameter]
src/intel/vulkan/tests/state_pool_padding.c:27:27: warning: unused parameter ‘argv’ [-Wunused-parameter]

src/intel/vulkan/tests/state_pool_no_free.c: In function ‘main’:
src/intel/vulkan/tests/state_pool_no_free.c:115:14: warning: unused parameter ‘argc’ [-Wunused-parameter]
src/intel/vulkan/tests/state_pool_no_free.c:115:27: warning: unused parameter ‘argv’ [-Wunused-parameter]

src/intel/vulkan/tests/state_pool_free_list_only.c: In function ‘main’:
src/intel/vulkan/tests/state_pool_free_list_only.c:35:14: warning: unused parameter ‘argc’ [-Wunused-parameter]
src/intel/vulkan/tests/state_pool_free_list_only.c:35:27: warning: unused parameter ‘argv’ [-Wunused-parameter]

v2: Use 'int main(void)' instead.  Suggested by Jason.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4994>
 2020-05-14 16:47:08 +00:00
Ian Romanick f4638cfdad anv/tests: Don't rely on assert or changing NDEBUG in tests 
This is the last part of the fix for #2903.

v2: Add test_common.h.

Fixes: f7c56475d2 ("anv/tests: compile to something sensible in release builds")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4994>
 2020-05-14 16:47:08 +00:00
Jason Ekstrand 4151bddab5 anv: Fix descriptor set clean-up on BO allocation failure 
This was a bit of rebase fail when writing 682c81bdfb.  We stopped
freeing descriptor sets back to the pool and started calling
vk_object_base_finish.  This commit reverts a that hunk should have
never made its way into the final patch.

Fixes: 682c81bdfb "vulkan,anv: Add a base object struct type"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5032>
 2020-05-14 16:14:34 +00:00
Jason Ekstrand 3f74c6a881 anv: Call vk_object_base_finish for image views 
Fixes: 682c81bdfb "vulkan,anv: Add a base object struct type"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5032>
 2020-05-14 16:14:34 +00:00
Danylo Piliaiev 06b6c687e2 anv: Fix deadlock in anv_timelines_wait 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2945
Fixes: 34f32a6d66
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5005>
 2020-05-14 13:14:57 +00:00
Danylo Piliaiev 15dd7933bc anv: Translate relative timeout to absolute when calling anv_timelines_wait 
Fixes: 34f32a6d66
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5025>
 2020-05-14 00:52:37 +00:00
Jason Ekstrand 0b5288492b anv: Set MOCS in 3DSTATE_CONSTANT_* on Gen9+ 
While we're here, we add a nice detailed comment about why always
assuming internal is ok.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5022>
 2020-05-14 00:34:47 +00:00
Jason Ekstrand e3d8edf3e0 anv: Set 3DSTATE_VF_INSTANCING on the SVGS element 
It probably doesn't matter because that buffer should have a stride of
zero.  However, it still seems like a good idea just to be safe.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5022>
 2020-05-14 00:34:47 +00:00
Iván Briano 5425968d2e anv: Implement VK_EXT_custom_border_color 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4898>
 2020-05-13 23:20:50 +00:00
Iván Briano 5b07f142d7 anv: Add a way to reserve states from a pool 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4898>
 2020-05-13 23:20:50 +00:00
Iván Briano 32d631dcd2 anv: Disable B5G6R5_UNORM_PACK16 
It's not a required format and it causes issues with some features.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4898>
 2020-05-13 23:20:50 +00:00
Iván Briano 6ae0762f5c anv: use the correct format on Android 
Per https://android.googlesource.com/platform/frameworks/native/+/master/vulkan/libvulkan/swapchain.cpp#745
the format Android requires is R5G6B5, and we have it backwards here.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4898>
 2020-05-13 23:20:50 +00:00
Samuel Pitoiset ddfae50b67 anv: use the common code for generating extensions and dispatch tables 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4987>
 2020-05-13 08:45:28 +02:00
Arcady Goldmints-Orlov 95fd950d35 intel/compiler: fix alignment assert in nir_emit_intrinsic 
Fixes: c643979228 (intel/fs: Choose memory message type based on bit size)
Fixes: dEQP-VK.subgroups.ballot_broadcast.compute.subgroupbroadcast_i8vec2

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5000>
 2020-05-12 22:14:31 +00:00
Jason Ekstrand 51c6bc13ce anv,vulkan: Implement VK_EXT_private_data 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4882>
 2020-05-12 18:01:48 +00:00
Kenneth Graunke ab16bff97d intel: Delete hardcoded devinfo->urb.size values for Gen7+ (sans DG1). 
On all Gen7+ platforms except DG1, the URB is a subsection of the
configurable L3 cache, and so the size can vary.  The size listed
in the documentation on those platforms is an "example size", picked
by calculating it based on an arbitrarily chosen L3 config.

Hardcoding a value for those platforms provides no value and only
confuses people trying to fill out these tables when doing hardware
enabling.  anv and iris never use this field.  i965 uses it to
initialize brw->urb.size, but then updates that in update_urb_size()
to be the correct value, so the initial value doesn't matter.

Delete the values for Gen7+ and update the comment accordingly.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4969>
 2020-05-11 09:40:56 -07:00
Samuel Pitoiset 04718a9cd6 nir: do not vectorize load/store if offset can overflow and robustness enabled 
This prevents vectorization for loads/stores that can overflow if
the low offset is negative and the range greater or equal than 0.

The caller can pass the list of variable modes that matter for
robust access.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4881>
 2020-05-11 07:25:15 +00:00
Lionel Landwerlin 9e790fea7c genxml: pack: deal with default field not being simple integers 
Storing integers into enums doesn't seem to cause issues in C, but
with our builder tests written in C++ this causes warnings/errors.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4938>
 2020-05-09 07:20:48 +00:00
Lionel Landwerlin 942d4538a4 genxml: factor out utility functions 
v2: Use the regexp version (Jordan)
    Also fix regexp that missed the ' character replacement (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4938>
 2020-05-09 07:20:48 +00:00
Lionel Landwerlin d07f69413e genxml: fix invalid end value for video fields 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4938>
 2020-05-09 07:20:48 +00:00
Lionel Landwerlin af17e392b2 genxml: run sorting script 
Helps running diff/meld between generations :)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4938>
 2020-05-09 07:20:48 +00:00
Jordan Justen 45c33313e6 intel/dev: Add device info for RKL 
Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by : Lionel Landwerlin <lionel.g.landwerlin@intel.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4955>
 2020-05-09 01:39:43 +00:00
Jordan Justen 54996ad492 intel/dev: Split .num_subslices out of GEN12_FEATURES macro 
The .num_subslices field makes it problematic to reuse the
GEN12_FEATURES macro in other macros.

This also fixes the number of L3 banks for tgl gt1, except that this
was already fixed by Jason (dynamically) in:

86f67952d3 ("intel/devinfo: Compute the correct L3$ size for Gen12")

Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by : Lionel Landwerlin <lionel.g.landwerlin@intel.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4955>
 2020-05-09 01:39:43 +00:00
D Scott Phillips 6c998c7adf intel/dump_gpu: Fix name of LD_PRELOAD in env append logic 
Checking for the wrong environment variable name to be set causes
us to stomp any pre-existing LD_PRELOAD.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4970>
 2020-05-08 14:49:07 -07:00
Jason Ekstrand d11e4738a8 anv/allocator: Add a start_offset to anv_state_pool 
This allows a pool's allocations to start somewhere other than the base
address.  Our first real use of this will be to use a negative offset
for the binding table pool to make it so that the offset is baked into
the pool and the code in anv_batch_chain.c doesn't have to understand
pool offsetting.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4897>
 2020-05-08 16:54:17 +00:00
Lionel Landwerlin 8bcfce2fcd anv: fix alignments for uniform buffers 
We were not consistent with minimums reported in the physical device
properties.

Fixes a few CTS tests :
   dEQP-VK.memory.requirements.dedicated_allocation.buffer.regular
   dEQP-VK.memory.requirements.extended.buffer.regular
   dEQP-VK.memory.requirements.core.buffer.regular

v2: Use define for the limit

v3: Rename define

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a0de2e0090 ("anv: increase minUniformBufferOffsetAlignment to 64")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4940>
 2020-05-08 08:59:02 +00:00
Tapani Pälli ee2aef3ea5 anv: call base finish only if pass given in DestroyRenderPass 
Fixes: 682c81bdfb ("vulkan,anv: Add a base object struct type")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4936>
 2020-05-08 08:36:45 +03:00
Ian Romanick f46eabf84e nir/algebraic: Split ibfe and ubfe with two constant sources 
I also tried splitting ubfe instructions with one or zero constants,
and zero shaders in shader-db were affected.

The "lost" shader is a compute shader that was promoted from SIMD8 to
SIMD16, so is also counted as the gained shader.

v2: Further restrict bfe splitting.  bfe with multiple constants is
better on at least some Radeon GPUs.  Use -x instead of 32-x in shift
counts.

v3: Fix the outer shift count for ibfe lowering.  Add c=0 optimizations
to prevent bad lowering.  Both suggested by Rhys.  Add shift by -32
optimizations.

Tiger Lake
total instructions in shared programs: 17608764 -> 17596316 (-0.07%)
instructions in affected programs: 303765 -> 291317 (-4.10%)
helped: 113
HURT: 46
helped stats (abs) min: 1 max: 458 x̄: 120.67 x̃: 21
helped stats (rel) min: 0.09% max: 11.23% x̄: 3.47% x̃: 1.39%
HURT stats (abs)   min: 1 max: 201 x̄: 25.83 x̃: 6
HURT stats (rel)   min: 0.23% max: 5.18% x̄: 1.53% x̃: 1.11%
95% mean confidence interval for instructions value: -101.13 -55.45
95% mean confidence interval for instructions %-change: -2.61% -1.44%
Instructions are helped.

total cycles in shared programs: 338390770 -> 333530868 (-1.44%)
cycles in affected programs: 79438330 -> 74578428 (-6.12%)
helped: 112
HURT: 64
helped stats (abs) min: 2 max: 268955 x̄: 44261.93 x̃: 1452
helped stats (rel) min: <.01% max: 29.51% x̄: 4.72% x̃: 2.23%
HURT stats (abs)   min: 2 max: 17618 x̄: 1522.41 x̃: 84
HURT stats (rel)   min: <.01% max: 7.34% x̄: 1.35% x̃: 0.34%
95% mean confidence interval for cycles value: -37232.47 -17993.69
95% mean confidence interval for cycles %-change: -3.37% -1.65%
Cycles are helped.

total spills in shared programs: 8944 -> 8138 (-9.01%)
spills in affected programs: 3240 -> 2434 (-24.88%)
helped: 67
HURT: 0

total fills in shared programs: 9373 -> 7842 (-16.33%)
fills in affected programs: 4736 -> 3205 (-32.33%)
helped: 67
HURT: 0

LOST:   1
GAINED: 2

Ice Lake and Skylake had similar results. (Ice Lake shown)
total instructions in shared programs: 16123288 -> 16116876 (-0.04%)
instructions in affected programs: 241155 -> 234743 (-2.66%)
helped: 126
HURT: 2
helped stats (abs) min: 1 max: 209 x̄: 50.90 x̃: 7
helped stats (rel) min: 0.07% max: 5.94% x̄: 1.76% x̃: 0.65%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.05% max: 0.24% x̄: 0.15% x̃: 0.15%
95% mean confidence interval for instructions value: -61.29 -38.89
95% mean confidence interval for instructions %-change: -2.05% -1.42%
Instructions are helped.

total cycles in shared programs: 335419163 -> 330438819 (-1.48%)
cycles in affected programs: 77515502 -> 72535158 (-6.42%)
helped: 139
HURT: 37
helped stats (abs) min: 2 max: 269140 x̄: 36374.19 x̃: 597
helped stats (rel) min: <.01% max: 28.60% x̄: 3.67% x̃: 1.31%
HURT stats (abs)   min: 4 max: 17618 x̄: 2045.08 x̃: 174
HURT stats (rel)   min: 0.02% max: 8.32% x̄: 2.61% x̃: 0.62%
95% mean confidence interval for cycles value: -37799.30 -18795.51
95% mean confidence interval for cycles %-change: -3.13% -1.57%
Cycles are helped.

total spills in shared programs: 8065 -> 7306 (-9.41%)
spills in affected programs: 3153 -> 2394 (-24.07%)
helped: 67
HURT: 0

total fills in shared programs: 8710 -> 7412 (-14.90%)
fills in affected programs: 4466 -> 3168 (-29.06%)
helped: 67
HURT: 0

LOST:   1
GAINED: 1

Broadwell
total instructions in shared programs: 14970538 -> 14965967 (-0.03%)
instructions in affected programs: 227040 -> 222469 (-2.01%)
helped: 126
HURT: 2
helped stats (abs) min: 1 max: 136 x̄: 36.29 x̃: 8
helped stats (rel) min: 0.07% max: 6.02% x̄: 1.47% x̃: 0.89%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.05% max: 0.24% x̄: 0.14% x̃: 0.14%
95% mean confidence interval for instructions value: -43.05 -28.37
95% mean confidence interval for instructions %-change: -1.69% -1.19%
Instructions are helped.

total cycles in shared programs: 336237662 -> 333035960 (-0.95%)
cycles in affected programs: 72066394 -> 68864692 (-4.44%)
helped: 134
HURT: 42
helped stats (abs) min: 4 max: 122640 x̄: 24344.54 x̃: 1833
helped stats (rel) min: <.01% max: 26.93% x̄: 4.02% x̃: 2.38%
HURT stats (abs)   min: 1 max: 17205 x̄: 1439.69 x̃: 92
HURT stats (rel)   min: <.01% max: 7.12% x̄: 1.34% x̃: 0.62%
95% mean confidence interval for cycles value: -23753.58 -12629.40
95% mean confidence interval for cycles %-change: -3.50% -1.98%
Cycles are helped.

total spills in shared programs: 21122 -> 20204 (-4.35%)
spills in affected programs: 3644 -> 2726 (-25.19%)
helped: 67
HURT: 0

total fills in shared programs: 24879 -> 23460 (-5.70%)
fills in affected programs: 4883 -> 3464 (-29.06%)
helped: 67
HURT: 0

Haswell
total instructions in shared programs: 13148269 -> 13145444 (-0.02%)
instructions in affected programs: 137046 -> 134221 (-2.06%)
helped: 97
HURT: 3
helped stats (abs) min: 1 max: 137 x̄: 30.58 x̃: 3
helped stats (rel) min: 0.14% max: 4.38% x̄: 1.38% x̃: 0.44%
HURT stats (abs)   min: 1 max: 70 x̄: 47.00 x̃: 70
HURT stats (rel)   min: 0.05% max: 5.82% x̄: 3.90% x̃: 5.82%
95% mean confidence interval for instructions value: -37.15 -19.35
95% mean confidence interval for instructions %-change: -1.56% -0.89%
Instructions are helped.

total cycles in shared programs: 321221834 -> 318333159 (-0.90%)
cycles in affected programs: 54932349 -> 52043674 (-5.26%)
helped: 95
HURT: 53
helped stats (abs) min: 4 max: 123390 x̄: 30648.39 x̃: 702
helped stats (rel) min: <.01% max: 28.87% x̄: 4.27% x̃: 2.87%
HURT stats (abs)   min: 4 max: 2357 x̄: 432.49 x̃: 113
HURT stats (rel)   min: <.01% max: 3.44% x̄: 1.03% x̃: 0.54%
95% mean confidence interval for cycles value: -26154.16 -12881.99
95% mean confidence interval for cycles %-change: -3.20% -1.55%
Cycles are helped.

total spills in shared programs: 19878 -> 19293 (-2.94%)
spills in affected programs: 3020 -> 2435 (-19.37%)
helped: 41
HURT: 2

total fills in shared programs: 20918 -> 19875 (-4.99%)
fills in affected programs: 3968 -> 2925 (-26.29%)
helped: 41
HURT: 2

LOST:   0
GAINED: 1

Ivy Bridge
total instructions in shared programs: 11875585 -> 11873641 (-0.02%)
instructions in affected programs: 78065 -> 76121 (-2.49%)
helped: 27
HURT: 0
helped stats (abs) min: 8 max: 134 x̄: 72.00 x̃: 72
helped stats (rel) min: 0.36% max: 4.23% x̄: 2.42% x̃: 2.42%
95% mean confidence interval for instructions value: -83.68 -60.32
95% mean confidence interval for instructions %-change: -2.78% -2.07%
Instructions are helped.

total cycles in shared programs: 178232734 -> 175769085 (-1.38%)
cycles in affected programs: 50018707 -> 47555058 (-4.93%)
helped: 27
HURT: 0
helped stats (abs) min: 82035 max: 99953 x̄: 91246.26 x̃: 92278
helped stats (rel) min: 4.40% max: 5.69% x̄: 4.93% x̃: 4.95%
95% mean confidence interval for cycles value: -93674.20 -88818.32
95% mean confidence interval for cycles %-change: -5.09% -4.78%
Cycles are helped.

total spills in shared programs: 4182 -> 3739 (-10.59%)
spills in affected programs: 1089 -> 646 (-40.68%)
helped: 27
HURT: 0

total fills in shared programs: 5216 -> 4345 (-16.70%)
fills in affected programs: 1874 -> 1003 (-46.48%)
helped: 27
HURT: 0

No changes on any earlier Intel platforms.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4156>
 2020-05-07 10:55:50 -07:00
Lionel Landwerlin 4f17e9eef6 anv: don't expose VK_INTEL_performance_query without kernel support 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 2b5f30b1d9 ("anv: implement VK_INTEL_performance_query")
Acked-by: Timothy Strelchun <timothy.strelchun@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4937>
 2020-05-07 16:42:44 +00:00
Arcady Goldmints-Orlov a0de2e0090 anv: increase minUniformBufferOffsetAlignment to 64 
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4904>
 2020-05-06 19:45:01 -05:00
Joshua Ashton c4d11ea3c4 anv: Remove RANGE_SIZE usage 
These were removed from the latest Vulkan headers
https://github.com/KhronosGroup/Vulkan-Docs/issues/1230

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4878>
 2020-05-05 00:27:59 +00:00
Jason Ekstrand 7628585dd7 anv: Refactor setting descriptors with immutable sampler 
Don't call anv_sampler_from_handle if the handle may be invalid.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4690>
 2020-05-04 14:06:27 +00:00
Jason Ekstrand 73fb7cdbe1 vulkan,anv: Move the DEFINE_HANDLE_CASTS macros to vk_object.h 
We've already got these duplicated a bunch of places.  They should
really probably live in common code.  The new versions take two more
arguments:

 1. The struct member which gets you from __driver_type to the
    vk_object_base.  This requires drivers which use this to also use
    vk_object_base.

 2. The VkObjectType enum which represents that object type.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4690>
 2020-05-04 14:06:27 +00:00