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Author SHA1 Message Date
Jason Ekstrand 74ec2b12be nir/lower_tex: Rework invalid implicit LOD lowering 
Only fragment and some compute shaders support implicit derivatives.
They're totally meaningless without helper invocations and some
understanding of the dispatch pattern.  We've got code to lower
nir_texop_tex in these shader stages to use an explicit derivative of 0
but it was pretty badly broken:

 1. It only handled nir_texop_tex, not nir_texop_txb or nir_texop_lod.

 2. It didn't take min_lod into account

 3. It was conflated with adding a missing LOD parameter to opcodes
    which expect one such as nir_texop_txf.  While not really a bug,
    this does make it way harder to reason about the code.

 4. Unless you set a flag (which most drivers don't), it left the
    opcode nir_texop_tex instead of nir_texop_txl which it should have
    been.

This reworks it to go through roughly the same path as other LOD
lowering only with a constant lod of 0 instead of calling out to
nir_texop_lod.  We also get rid of the lower_tex_without_implicit_lod
flag because most drivers set it and those that don't are probably
subtly broken.  If someone really wants to get nir_texop_tex in their
vertex shaders, they can write a new patch to add the flag back in.

Fixes: e382890e25 "nir: set default lod to texture opcodes that..."
Fixes: d5ac5d6e83 "nir: Add option to lower tex to txl when..."
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
 2021-07-23 15:53:57 +00:00
Jason Ekstrand 7ecfbaf7f0 intel/blorp: Use nir_texop_txl 
We set an explicit LOD immediately afterwards so we don't want implicit
mipmap selection.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
 2021-07-23 15:53:57 +00:00
Jason Ekstrand 4465ca296d nir: Suffix all the MCS texture stuff _intel 
It's intel-specific, used to get at MSAA compression information.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
 2021-07-23 15:53:57 +00:00
Sagar Ghuge ef29bb6bc5 intel/compiler: Handle ternary add in lower_simd_width 
We need to lower the add3 instruction simd width otherwise in simd32
mode, we endup writing 4 register wide data which is not allowed.

Reported-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11985>
 2021-07-22 23:38:04 +00:00
Sagar Ghuge 0608e76e00 intel/compiler: Fix missing break in switch 
CoverityID: 1487496

Fixes: cde9ca616d "intel/compiler: Make decision based on source type instead of opcode"
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11985>
 2021-07-22 23:38:04 +00:00
Jason Ekstrand 929558776e intel/eu: Don't validate LSC transpose on ops that don't have it 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11991>
 2021-07-22 21:06:33 +00:00
Caio Marcelo de Oliveira Filho 4dc81cc631 anv: Advertise support for VK_EXT_shader_atomic_float2 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11981>
 2021-07-21 20:15:21 +00:00
Jordan Justen 8c29891fa4 intel/compiler: Remove cube array size lowering in compiler backend 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9466>
 2021-07-21 11:34:49 -07:00
Jordan Justen e2a30ebf44 intel/compiler: Lower cube image sizes using nir_lower_image() 
Reworks:
 * Re-merge early/late passes using Jason's nir image deref patches
 * Create and use a common nir_lower_image() pass. (s-b Jason)
 * Remove cube array size handling in image load/store lowering

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9466>
 2021-07-21 11:34:49 -07:00
Jordan Justen b5514a2236 intel/compiler: Rename brw_nir_lower_image_load_store to brw_nir_lower_storage_image 
Reworks:
 * Add crocus

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9466>
 2021-07-21 11:02:15 -07:00
Timothy Arceri 9f3fde6f36 intel/compiler: Use GCM in nir_optimize 
There is still some work to do before we can enable GVN.

In these shader-db results, Skylake and older platforms used i965 while
newer platforms used Iris.  I believe this accounts for the difference
in "sends."  The shaders helped for sends are all Synmark shaders.

On Sandybridge, the shaders helped for sends were the same ones hurt for
spills and fills.  These are also all Synmark shaders.

Tiger Lake and Ice Lake had similar results. (Ice Lake shown)
total instructions in shared programs: 19868594 -> 19868452 (<.01%)
instructions in affected programs: 6607 -> 6465 (-2.15%)
helped: 12
HURT: 1
helped stats (abs) min: 12 max: 12 x̄: 12.00 x̃: 12
helped stats (rel) min: 1.94% max: 2.62% x̄: 2.38% x̃: 2.58%
HURT stats (abs)   min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 0.45% max: 0.45% x̄: 0.45% x̃: 0.45%
95% mean confidence interval for instructions value: -13.27 -8.58
95% mean confidence interval for instructions %-change: -2.67% -1.65%
Instructions are helped.

total cycles in shared programs: 962404540 -> 962008224 (-0.04%)
cycles in affected programs: 961274 -> 564958 (-41.23%)
helped: 23
HURT: 1
helped stats (abs) min: 10 max: 32536 x̄: 17438.96 x̃: 23658
helped stats (rel) min: 0.02% max: 80.04% x̄: 42.05% x̃: 51.58%
HURT stats (abs)   min: 4780 max: 4780 x̄: 4780.00 x̃: 4780
HURT stats (rel)   min: 3.26% max: 3.26% x̄: 3.26% x̃: 3.26%
95% mean confidence interval for cycles value: -22989.90 -10036.43
95% mean confidence interval for cycles %-change: -55.01% -25.32%
Cycles are helped.

Skylake and Broadwell had simliar results. (Skylake shown)
total instructions in shared programs: 17996652 -> 17996154 (<.01%)
instructions in affected programs: 96622 -> 96124 (-0.52%)
helped: 85
HURT: 0
helped stats (abs) min: 1 max: 12 x̄: 5.86 x̃: 5
helped stats (rel) min: 0.39% max: 2.65% x̄: 0.68% x̃: 0.39%
95% mean confidence interval for instructions value: -6.42 -5.30
95% mean confidence interval for instructions %-change: -0.84% -0.52%
Instructions are helped.

total cycles in shared programs: 939899189 -> 939289732 (-0.06%)
cycles in affected programs: 3719430 -> 3109973 (-16.39%)
helped: 60
HURT: 39
helped stats (abs) min: 18 max: 32444 x̄: 10437.30 x̃: 6940
helped stats (rel) min: 0.08% max: 80.40% x̄: 23.99% x̃: 12.07%
HURT stats (abs)   min: 10 max: 4970 x̄: 430.28 x̃: 323
HURT stats (rel)   min: 0.05% max: 3.41% x̄: 1.55% x̃: 1.60%
95% mean confidence interval for cycles value: -8095.51 -4216.75
95% mean confidence interval for cycles %-change: -18.65% -9.21%
Cycles are helped.

total sends in shared programs: 1026997 -> 1026927 (<.01%)
sends in affected programs: 6090 -> 6020 (-1.15%)
helped: 70
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 1.15% max: 1.15% x̄: 1.15% x̃: 1.15%
95% mean confidence interval for sends value: -1.00 -1.00
95% mean confidence interval for sends %-change: -1.15% -1.15%
Sends are helped.

Haswell and Ivy Bridge had similar results. (Haswell shown)
total instructions in shared programs: 16040891 -> 16040252 (<.01%)
instructions in affected programs: 109132 -> 108493 (-0.59%)
helped: 87
HURT: 0
helped stats (abs) min: 1 max: 12 x̄: 7.34 x̃: 7
helped stats (rel) min: 0.05% max: 2.61% x̄: 0.75% x̃: 0.51%
95% mean confidence interval for instructions value: -7.84 -6.85
95% mean confidence interval for instructions %-change: -0.90% -0.61%
Instructions are helped.

total cycles in shared programs: 968579567 -> 967867117 (-0.07%)
cycles in affected programs: 30688439 -> 29975989 (-2.32%)
helped: 241
HURT: 62
helped stats (abs) min: 4 max: 31929 x̄: 3901.22 x̃: 2282
helped stats (rel) min: 0.04% max: 79.63% x̄: 12.70% x̃: 4.44%
HURT stats (abs)   min: 4 max: 8230 x̄: 3673.27 x̃: 637
HURT stats (rel)   min: 0.01% max: 63.87% x̄: 24.54% x̃: 3.56%
95% mean confidence interval for cycles value: -3100.23 -1602.41
95% mean confidence interval for cycles %-change: -7.94% -2.22%
Cycles are helped.

total sends in shared programs: 935025 -> 934955 (<.01%)
sends in affected programs: 6090 -> 6020 (-1.15%)
helped: 70
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 1.15% max: 1.15% x̄: 1.15% x̃: 1.15%
95% mean confidence interval for sends value: -1.00 -1.00
95% mean confidence interval for sends %-change: -1.15% -1.15%
Sends are helped.

LOST:   1
GAINED: 0

Sandy Bridge
total instructions in shared programs: 11785330 -> 11786504 (<.01%)
instructions in affected programs: 53462 -> 54636 (2.20%)
helped: 16
HURT: 36
helped stats (abs) min: 1 max: 17 x̄: 10.06 x̃: 9
helped stats (rel) min: 0.47% max: 3.29% x̄: 2.03% x̃: 1.90%
HURT stats (abs)   min: 5 max: 38 x̄: 37.08 x̃: 38
HURT stats (rel)   min: 1.77% max: 2.98% x̄: 2.94% x̃: 2.98%
95% mean confidence interval for instructions value: 16.26 28.90
95% mean confidence interval for instructions %-change: 0.75% 2.08%
Instructions are HURT.

total cycles in shared programs: 498009911 -> 497378300 (-0.13%)
cycles in affected programs: 6848277 -> 6216666 (-9.22%)
helped: 108
HURT: 28
helped stats (abs) min: 4 max: 25394 x̄: 6037.42 x̃: 766
helped stats (rel) min: 0.02% max: 60.58% x̄: 11.60% x̃: 4.83%
HURT stats (abs)   min: 96 max: 6834 x̄: 729.64 x̃: 742
HURT stats (rel)   min: 0.17% max: 16.23% x̄: 1.57% x̃: 1.55%
95% mean confidence interval for cycles value: -5907.99 -3380.40
95% mean confidence interval for cycles %-change: -11.67% -6.11%
Cycles are helped.

total spills in shared programs: 2316 -> 2526 (9.07%)
spills in affected programs: 280 -> 490 (75.00%)
helped: 0
HURT: 35

total fills in shared programs: 1540 -> 1750 (13.64%)
fills in affected programs: 280 -> 490 (75.00%)
helped: 0
HURT: 35

total sends in shared programs: 642985 -> 642950 (<.01%)
sends in affected programs: 3045 -> 3010 (-1.15%)
helped: 35
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 1.15% max: 1.15% x̄: 1.15% x̃: 1.15%
95% mean confidence interval for sends value: -1.00 -1.00
95% mean confidence interval for sends %-change: -1.15% -1.15%
Sends are helped.

LOST:   1
GAINED: 0

Iron Lake and GM45 had similar results. (Iron Lake shown)
total cycles in shared programs: 239442382 -> 239429400 (<.01%)
cycles in affected programs: 20816 -> 7834 (-62.37%)
helped: 2
HURT: 0

In Fossil-db, all of the shaders hurt for spill and fills are compute
shaders from Shadow of the Tomb Raider.  Two shaders were helped for
sends, and these are also from SotTR.

All of the shaders helped for loops were from Geekbench5.  These all
went from 3 loops to 2.

Tiger Lake
Instructions in all programs: 160852396 -> 160855303 (+0.0%)
SENDs in all programs: 6878559 -> 6878559 (+0.0%)
Loops in all programs: 38350 -> 38305 (-0.1%)
Cycles in all programs: 7369162339 -> 7344236445 (-0.3%)
Spills in all programs: 193762 -> 193876 (+0.1%)
Fills in all programs: 306417 -> 306600 (+0.1%)

Ice Lake
Instructions in all programs: 144592523 -> 144593946 (+0.0%)
SENDs in all programs: 6930697 -> 6930697 (+0.0%)
Loops in all programs: 38344 -> 38299 (-0.1%)
Cycles in all programs: 8732456458 -> 8707823383 (-0.3%)
Spills in all programs: 216692 -> 216806 (+0.1%)
Fills in all programs: 334089 -> 334272 (+0.1%)

Skylake
Instructions in all programs: 135618746 -> 135619971 (+0.0%)
SENDs in all programs: 6896728 -> 6896724 (-0.0%)
Loops in all programs: 38343 -> 38298 (-0.1%)
Cycles in all programs: 8391957144 -> 8368935657 (-0.3%)
Spills in all programs: 194741 -> 194879 (+0.1%)
Fills in all programs: 301048 -> 301255 (+0.1%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/597>
 2021-07-21 14:24:00 +00:00
Timothy Arceri c742a99fb6 intel/compiler: call nir_opt_dead_cf() after we have finished all opts 
This will avoid a regression with the following patch.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/597>
 2021-07-21 14:24:00 +00:00
Marcin Ślusarz 8250f2ae29 anv: share some code between vkCmdDrawIndirectCount and vkCmdDrawIndexedIndirectCount 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11975>
 2021-07-21 09:23:15 +00:00
Marcin Ślusarz b6843d990b intel/tools/aubinator_error_decode: tag hanging instruction 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11957>
 2021-07-21 08:20:06 +00:00
Iván Briano 0b9562a94a anv: Allow unused VkSpecializationMapEntries 
Fixes future CTS: dEQP-VK.pipeline.spec_constant.*.basic.*unused_*

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11987>
 2021-07-20 21:42:50 +00:00
Iván Briano d27f7fa1b3 anv: fix feature/property/sizes reported for fragment shading rate 
Fixes: 790ff1ceac ("anv: fixup physical device properties of fragment shading rate")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11897>
 2021-07-17 00:46:54 +00:00
Jason Ekstrand 46cc332025 anv: Stop reference counting semaphores 
The only reason we had to refcount semaphores was for the ancient
sync_file semaphores which we used for pre-syncobj kernels.  Now that we
assume syncobj and that code is gone, we don't need reference counting
anymore either.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9777>
 2021-07-16 21:12:21 +00:00
Jason Ekstrand d44ea09e61 anv: Drop unused sync_file and BO semaphore code 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9777>
 2021-07-16 21:12:21 +00:00
Jason Ekstrand 3b363d5b55 anv: Assume syncobj support 
Sync object for i915 support has been in upstream Linux since 4.14 which
is 3.5 years old at this point and, as far as we can tell, it also
exists in all the ChromeOS kernels.  Assuming it allows us to drop some
of our more gnarly synchronization fall-back paths.

At the time of merge, ChromeOS was on the following kernels:

 - kernel 3.18: SKL
 - kernel 4.4: BYT, KBL, APL
 - Kernel 4.14: BDW, GLK

All of the pre-4.14 kernels have had syncobj support back-ported.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9777>
 2021-07-16 21:12:21 +00:00
Jason Ekstrand a62973580b intel/eu: Start validating LSC message descriptors 
This is certainly not a full validation but it at least gets the
framework in place and validates one hard-to-find restriction.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11657>
 2021-07-16 17:25:48 +00:00
Sagar Ghuge 89b7a40212 intel/compiler: Enable has_iadd3 option on XeHP 
shader-db result is inconclusive but doesn't harm to include it for
reference.

Shader-db result on XeHPG:

total instructions in shared programs: 1397405 -> 1397315 (<.01%)
instructions in affected programs: 88252 -> 88162 (-0.10%)
helped: 20
HURT: 7
helped stats (abs) min: 1 max: 18 x̄: 7.20 x̃: 7
helped stats (rel) min: 0.03% max: 2.20% x̄: 0.37% x̃: 0.23%
HURT stats (abs)   min: 4 max: 23 x̄: 7.71 x̃: 4
HURT stats (rel)   min: 0.10% max: 0.68% x̄: 0.22% x̃: 0.11%
95% mean confidence interval for instructions value: -6.81 0.14
95% mean confidence interval for instructions %-change: -0.42% -0.02%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 119924219 -> 119931868 (<.01%)
cycles in affected programs: 45029193 -> 45036842 (0.02%)
helped: 11
HURT: 16
helped stats (abs) min: 15 max: 5490 x̄: 1655.73 x̃: 140
helped stats (rel) min: <.01% max: 0.35% x̄: 0.11% x̃: <.01%
HURT stats (abs)   min: 1 max: 2944 x̄: 1616.38 x̃: 1743
HURT stats (rel)   min: <.01% max: 0.17% x̄: 0.09% x̃: 0.10%
95% mean confidence interval for cycles value: -606.11 1172.70
95% mean confidence interval for cycles %-change: -0.04% 0.07%
Inconclusive result (value mean confidence interval includes 0).

v2:
- Include shader-db result (Jason)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11596>
 2021-07-16 15:59:56 +00:00
Sagar Ghuge e6db2299a8 intel/compiler: Allow ternary add to promote source to immediate 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11596>
 2021-07-16 15:59:56 +00:00
Sagar Ghuge cde9ca616d intel/compiler: Make decision based on source type instead of opcode 
This patch restructure code a little bit to check if source can be
represented as immediate operand. This is a foundation for next patch
which add checks for integer operand as well.

Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11596>
 2021-07-16 15:59:56 +00:00
Sagar Ghuge 705285b9f4 intel/compiler: Add support for ternary add instruction on XeHP 
v2:
- Re-arragne opcode in correct order (Matt Turner)
- Move ADD3 case closer to LRP (Jason)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11596>
 2021-07-16 15:59:56 +00:00
Jason Ekstrand f5008a48d3 intel/perf: Use intel_i915_query_flags instead of hand-rolling it 
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11770>
 2021-07-16 14:19:20 +00:00
Jason Ekstrand ba99d2a328 intel/dev: Use intel_i915_query_alloc in query_topology 
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11770>
 2021-07-16 14:19:20 +00:00
Jason Ekstrand 35ec1d9730 anv: Use intel_i915_query_alloc for memory regions 
Error handling with DRM_IOCTL_I915_QUERY is tricky and we got it wrong
in one of the two calls here.  Use the common helper instead.  This also
fixes a theoretical bug where calloc() fails.  While we're here, inline
anv_track_meminfo because we're not really benefiting from having it
separate anymore.

Fixes: 65e8d72bc1 "anv: Query memory region info"
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11770>
 2021-07-16 14:19:20 +00:00
Jason Ekstrand ffdf4d7683 intel: Pull anv_i915_query into common code 
We also add a helper which contains the standard query+alloc+query
pattern used by anv_gem_get_engine_info().  The caller is required to
free the pointer.

These are declared static inline not because we care about the
performance of these helpers but because we're going to use them in the
intel_device_info code and we don't want a link dependency.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11770>
 2021-07-16 14:19:20 +00:00
Jason Ekstrand b664481ba9 anv: Handle errors properly in anv_i915_query 
DRM_IOCTL_I915_QUERY is a multi-query.  The most egregious errors are
returned via the usual ioctl error mechanism but there are also
per-query errors that are indicated by item.length < 0.  We need to
handle those as well.  While we're at it, scrape errno so we can return
a proper integer error.

Fixes: c0d07c838a "anv: Support i915 query (DRM_IOCTL_I915_QUERY)..."
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11770>
 2021-07-16 14:19:20 +00:00
Jason Ekstrand cb589ee394 intel/dev: Drop a bogus assert 
In c24ba6cecb, I copied over the CHV thread count code from i965 and
ANV into common code.  While at it, I added an assert that I thought
should be true based on the comments.  It turns out to be invalid.  Drop
it.

Fixes: c24ba6cecb "intel/dev: Handle CHV CS thread weirdness in..."
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5072
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11918>
 2021-07-15 21:43:31 -05:00
Iván Briano fce0027d91 anv: Unbreak wide lines on HSW/BDW 
I knew there was a reason the limit was at ~8 and not rounded to it.

Fixes: 004fcfe698 ("anv: fix some multisample lines_wide CTS tests")

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11914>
 2021-07-15 21:59:37 +00:00
Caio Marcelo de Oliveira Filho dfcb47bcec anv: Zero initialize pipeline structs 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11890>
 2021-07-15 21:34:53 +00:00
Iván Briano 004fcfe698 anv: fix some multisample lines_wide CTS tests 
We can use a better algorithm from ICL and onward by setting a chicken
bit, but prior to that we need to resort to disabling rectangular lines.
Since we don't support strictLines anyway, this shouldn't be a major
issue.

Closes #2833
Fixes dEQP-VK.rasterization.interpolation_multisample_*_bit.*lines_wide

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11672>
 2021-07-15 17:07:35 +00:00
Iván Briano f40a08d25c anv: Don't advertise unsupported shader stages 
We don't currently support mesh or ray tracing, so don't advertise their
shader stages as supported for subgroups.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11893>
 2021-07-15 16:32:54 +00:00
Jason Ekstrand 6642749458 intel/dev: Add a max_cs_workgroup_threads field 
This is distinct form max_cs_threads because it also encodes
restrictions about the way we use GPGPU/COMPUTE_WALKER.  This gets rid
of the MIN2(64, devinfo->max_cs_threads) we have scattered all over the
driver and puts it in a central place.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11861>
 2021-07-14 23:02:34 +00:00
Jason Ekstrand 915e5a8cc3 intel/dev: Handle BSW naming issues 
Braswell, a particular Cherryview variant, is especially strange.  We
can't even get the chip name from the PCI ID and instead have to look at
fusing information to decide if it's a 400 or a 405.  Pull that into the
common code as well.  This fixes BSW naming on ANV and crocus.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11861>
 2021-07-14 23:02:34 +00:00
Jason Ekstrand 56d70ba686 intel/dev: Put the device name in intel_device_info 
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11861>
 2021-07-14 23:02:34 +00:00
Jason Ekstrand c24ba6cecb intel/dev: Handle CHV CS thread weirdness in get_device_info_from_fd 
Cherryview is weird in that the actual limits we can expose through GL
are dependent on fusing information which is only obtainable at runtime.
The same PCI ID may have different configurations with different maximum
CS thread counts.  We currently handle this in i965 and ANV by doing the
calculation in the driver.

This dates back to when intel_device_info was computed from the PCI ID.
Now that we have get_device_info_from_fd, we can move the CHV stuff
there and get it out of the driver.  This fixes CHV thread counts on
crocus as well.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11861>
 2021-07-14 23:02:34 +00:00
Ian Romanick 3cb203303c intel/compiler: Update block IPs once in opt_cmod_propagation 
No difference proven at 95.0% confidence (n=10) in
dEQP-VK.ssbo.phys.layout.random.16bit.scalar.13.

v2: Only update each block's IP data once instead of once per block.
Suggested by Emma.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11632>
 2021-07-14 09:57:06 -07:00
Ian Romanick 8f1052938d intel/compiler: Update block IPs once in register_coalesce 
Performance improvement in
dEQP-VK.ssbo.phys.layout.random.16bit.scalar.13 for n=30:

release build (w/Fedora build flags): -0.82% ± 0.23%
Meson -Dbuildtype=debugoptimized:     -0.74% ± 0.27%

The difference in the debugoptimized build is the calls to
inst_is_in_block(block, this) still exist on each call to remove().

v2: Only update each block's IP data once instead of once per block.
Suggested by Emma.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11632>
 2021-07-14 09:57:04 -07:00
Ian Romanick f3f3817307 intel/compiler: Update block IPs once in dead_code_eliminate 
Performance improvement in
dEQP-VK.ssbo.phys.layout.random.16bit.scalar.13 for n=30:

release build (w/Fedora build flags): -7.79% ± 0.25%
Meson -Dbuildtype=debugoptimized:     -5.10% ± 0.40%

The difference in the debugoptimized build is the calls to
inst_is_in_block(block, this) still exist on each call to remove().

v2: Only update each block's IP data once instead of once per block.
Suggested by Emma.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11632>
 2021-07-14 09:57:01 -07:00
Ian Romanick 8ca1bc5f94 intel/compiler: Add cfg_t::adjust_block_ips() method 
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11632>
 2021-07-14 09:56:59 -07:00
Ian Romanick 8206b04d43 intel/compiler: Add the ability to defer IP updates in backend_instruction::remove 
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11632>
 2021-07-14 09:56:46 -07:00
Jason Ekstrand 2fd989a298 anv/allocator: Use list->u64 in free_list_push 
Since we always modify this structure with atomics on the u64, it seems
better to use the u64 here too.  I have no idea if this fixes a bug.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11857>
 2021-07-14 05:50:46 +00:00
Simon Zeni c8ed5ac206 anv: Implement VK_EXT_acquire_drm_display 
Signed-off-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Simon Ser <contact@emersion.fr>
Tested-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11735>
 2021-07-13 20:50:32 +00:00
Jason Ekstrand 3d934ee03f glsl: Delete lower_texture_projection 
This is only used by i965 and we've been getting it through
nir_lower_tex since forever.  Get rid of the GLSL IR pass.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11827>
 2021-07-13 14:06:33 +00:00
Marcin Ślusarz f3742b9c13 intel/compiler: document register types 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11677>
 2021-07-12 13:27:41 +00:00
Lionel Landwerlin 91dcbf1f56 intel/compiler: Track latency/perf of LSC fences 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11759>
 2021-07-12 11:39:03 +00:00
Andrii Simiklit 57f54bb9cc Remove redundant assignment 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4957
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11780>
 2021-07-09 09:34:27 +00:00
Jason Ekstrand d4b482d378 android: Drop the Android.mk build system 
Android.mk files haven't really been supported by Mesa devs for a long
time.  Most of us have been willing to update Makefile.sources if we
remember and sometimes we try to blind code some Android.mk for a new
generator.  However, the reality is that it breaks regularly and ends up
being maintained by the Android community.  To address this problem
another approach was implemented in !10183 utilizing the maintained
meson build system.  The old Android.mk files are no longer required.

This commit was created with the following commands:

    git rm **/Android.mk
    git rm **/Android.*.mk
    git rm **/Makefile.sources
    git rm CleanSpec.mk

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4487
Acked-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9728>
 2021-07-08 14:44:02 -05:00