Commit Graph

1843 Commits

Author SHA1 Message Date
Bas Nieuwenhuizen c685076ab0 radv: Fix freeing meta state if the device pipeline cache fails to allocate.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-22 00:07:24 +01:00
Bas Nieuwenhuizen 71f0315a88 radv: Fix memory allocation failure path in compute resolve init.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-22 00:07:19 +01:00
Bas Nieuwenhuizen d956e0bdf5 radv: Fix ordering issue in meta memory allocation failure path.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-22 00:07:03 +01:00
Dylan Baker 436ed65d38 autotools: include meson build files in tarball
This adds the meson.build, meson_options.txt, and a few scripts that are
used exclusively by the meson build.

v2: - Remove accidentally included changes needed to test make dist with
      LLVM > 3.9

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-01-19 16:30:51 -08:00
Bas Nieuwenhuizen 61a790409e radv: Always re-emit the sample position offset user SGPR.
The user SGPR location can change between pipelines, so we need to
emit it again to the pottentially changed SGPR index.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-19 23:35:12 +01:00
Bas Nieuwenhuizen dbf1e918cd radv: emit pa_sc_mode_cntl_0 with multisample state.
We don't have the meta kludge with 0 viewports anymore,
so we can always enable them.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-19 23:35:12 +01:00
Bas Nieuwenhuizen 32170d87e3 ac/nir: Fix vector extraction if source vector has >4 elements.
v2: Add forgotten argument and start offset.

Fixes: 91074bb11b "radv/ac: Implement Float64 SSBO stores."
Tested-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-01-19 02:00:28 +01:00
Bas Nieuwenhuizen f4211e6f93 ac/nir: Use correct 32-bit component writemask for 64-bit SSBO stores.
Fixes: 91074bb11b "radv/ac: Implement Float64 SSBO stores."
Tested-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-01-19 02:00:14 +01:00
Bas Nieuwenhuizen 4a9fd90e1e ac/nir: Fix TCS output LDS offsets.
When a channel was not set we also did not increase the LDS address,
while that obviously should happen.

The output loading code was inadvertently fixed which resulted in a
mismatch causing the SaschaWillems tessellation demo to result
in corrupt rendering.

Fixes: 7898eb9a60 "ac: rework load_tcs_{inputs,outputs}"
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-19 01:54:59 +01:00
Bas Nieuwenhuizen bd5c942cef radv: Use correct bindings for inputRate in key generation.
The bindings also have an index field.

Fixes: 49d035122e "radv: Add single pipeline cache key."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104677
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-19 01:54:59 +01:00
Bas Nieuwenhuizen b1444c9ccb radv: Implement VK_ANDROID_native_buffer.
Passes
  dEQP-VK.api.smoke.*
  dEQP-VK.wsi.android.*

with android-cts-7.1_r12 .

Unlike the initial anv implementation this does
use syncobjs instead of waiting on the CPU.

This is missing meson build coverage for now.

One possible todo is that linux 4.15 now has a
sycall that allows us to export amdgpu fence to
a sync_file, which allows us not to force all
fences and semaphores to use syncobjs. However,
I had trouble with my kernel crashing regularly
with NULL pointers, and I'm not sure how beneficial
it is in the first place given that intel uses
syncobjs for all fences if available.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-19 01:43:55 +01:00
Bas Nieuwenhuizen a3e241ed07 radv: Add create image flag to not use DCC/CMASK.
If we import an image, we might not have space in the
buffer for CMASK, even though it is compatible.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-19 01:43:55 +01:00
Bas Nieuwenhuizen e344cd8178 radv: Generate VK_ANDROID_native_buffer.
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-19 01:43:55 +01:00
Bas Nieuwenhuizen 0f89f9b8eb radv: Replace an assert with unreachable.
Otherwise we get uninitialized variable warnings for es_vgpr_comp_cnt.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-19 00:38:45 +01:00
Bas Nieuwenhuizen e417ab212b radv: Remove DCC check on CS resolve dst image.
Gives a warning when the assert is disabled, and not even
necessarily true.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-19 00:38:45 +01:00
Timothy Arceri 3bccb5dba9 ac: fix visit_ssa_undef() for doubles
V2: use LLVMIntTypeInContext()

Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver"

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-19 08:09:04 +11:00
Dave Airlie 3153d74207 ac/nir: account for view index in the user sgpr allocation.
The view index user sgpr wasn't being accounted for properly,
this refactors out the code to decide if it's required and then
uses that info to account for it.

Fixes: 180c1b924e (ac/nir: Add shader support for multiviews.)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 19:47:40 +00:00
Timothy Arceri 9248f72c4e ac: tidy up array indexing logic
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-18 15:59:27 +11:00
Dave Airlie 6785034a70 radv/ws: get rid of useless return value
This also used boolean, so nice to kill that.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 01:57:53 +00:00
Bas Nieuwenhuizen 2ce11ac11f radv: Initialize DCC on transition from preinitialized.
Looks like the decompress does not handle invalid encodings well,
which happens with random memory. Of course apps should not use it
with random memory, but they are allowed to ....

Fixes: 44fcf58744 "radv: Disable DCC for GENERAL layout and compute transfer dest."
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-18 01:57:52 +01:00
Timothy Arceri e2b9296146 ac: fix buffer overflow bug in 64bit SSBO loads
Fixes: 441ee1e65b "radv/ac: Implement Float64 SSBO loads"

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-18 10:26:58 +11:00
Timothy Arceri 409e15f26f ac: fix nir_intrinsic_get_buffer_size for radeonsi
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-18 10:25:20 +11:00
Timothy Arceri 7898eb9a60 ac: rework load_tcs_{inputs,outputs}
This shares more code and calls the new shared load_tess_varyings()
abi so that the radeonsi nir path now supports tcs output loads.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-18 00:03:33 +11:00
Timothy Arceri 9622b445c8 ac/radeonsi: add tcs load outputs support
The code to load outputs is essentially the same as load inputs
so we make the interface more generic to maximise code sharing.

We will make use of the new support in the following patch.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-18 00:03:33 +11:00
Bas Nieuwenhuizen 0b8991c0b6 radv: Implement VK_EXT_debug_report.
This is not hooked up to any messages yet, but useful for e.g.
renderdoc if you add some messages during development.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-17 11:29:04 +01:00
Samuel Pitoiset 05f73b9672 ac: set no-signed-zeros-fp-math when RADV_DEBUG="unsafemath" is used
This is an optimisation that is recommended by Matt Arsenault,
and used by RadeonSI, but it's not compatible with Vulkan.

Note that AC_FLOAT_MODE_UNSAFE_FP_MATH includes the no signed
zeros flag in LLVM.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-16 21:39:57 +01:00
Samuel Pitoiset 4f5318df2c ac: set fast math flags when RADV_DEBUG="unsafemath" is used
When that debug option is not used, we use the default float mode
because the no signed zeros optimisation is not Vulkan compatible.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-16 21:39:55 +01:00
Samuel Pitoiset 2091206ad3 ac: import lp_create_builder() from gallivm
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-16 21:39:53 +01:00
Samuel Pitoiset ad2b3b2a9c ac: replace llvm.AMDGPU.kilp by llvm.amdgcn.kill with LLVM 6
This also replaces llvm.AMDGPU.kilp by llvm.AMDGPU.kill with
LLVM < 6. Similar to RadeonSI codepath.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-16 21:39:51 +01:00
Samuel Pitoiset 8045f01e2a Revert "ac/shader: gather If TES reads TESSINNER or TESSOUTER"
This can't work for two reasons:
- TESSINNER/TESSOUTER are shader input values, so never translated
to the intrinsic ops
- the shader info pass scans the current stage but we want to know
in TCS, if TES reads the tess factors.

This fixes 6 regressions related to
deqp-vk/tessellation/shader_input_output/tess_level_{inner,outer}_XXX_tes

This reverts commit 5ba1a61648.
2018-01-15 13:47:18 +01:00
Samuel Pitoiset 5842cb0df1 amd/common: fix loading InstanceID for tess on < GFX9
InstanceID is in VGPR2, not 1.

One more failure that CTS didn't catch up...

Reported-by: Alex Smith <asmith@feralinteractive.com>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-15 11:59:16 +01:00
Samuel Pitoiset 5ba1a61648 ac/shader: gather If TES reads TESSINNER or TESSOUTER
This shouldn't be scanned in the pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-01-15 11:51:47 +01:00
Samuel Pitoiset aebde47840 ac: remove ac_shader_variant_info::fs::output_mask
Unused.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-01-15 11:48:42 +01:00
Timothy Arceri e6378962ce ac: add doubles support to isign
Fixes a number of int64 piglit tests, for example:

generated_tests/spec/arb_gpu_shader_int64/execution/built-in-functions/fs-sign-i64vec2.shader_test

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-14 11:40:03 +11:00
Timothy Arceri 38876c88d1 ac: add i64_0 and i64_1 to llvm build context
These will be used in the following patch.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-14 11:40:03 +11:00
Timothy Arceri 741b21b713 ac/nir: fix translation of nir_op_b2i for doubles
V2: just zero-extend the 32-bit value.

Fixes a number of int64 piglet tests, for example:

generated_tests/spec/arb_gpu_shader_int64/execution/conversion/frag-conversion-explicit-bool-int64_t.shader_test

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-14 11:40:03 +11:00
Timothy Arceri f0d74ecce8 radv/radeonsi/nir: lower 64bit flrp
Fixes a bunch of arb_gpu_shader_fp64 piglit tests for example:

generated_tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-mix-double-double-double.shader_test

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-13 18:04:40 +11:00
Samuel Pitoiset 0eb30d81c4 ac: add 'const' qualifiers to the shader info pass
For clarification purposes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-12 12:25:21 +01:00
Samuel Pitoiset 20f7f9a328 ac: remove unused ac_nir_compiler_options from gather_info_input_decl()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-12 12:25:19 +01:00
Dave Airlie ad11fc3571 radv: don't emit unneeded vertex state.
If the number of instances hasn't changed and we've already
emitted it, don't emit it again.

If the vertex shader is the same and the first_instance, vertex_offset
haven't changed don't emit them again.

This increases the fps in GL_vs_VK -t 1 -m -api vk from around 40
to around 60 here, it may not impact anything else.

Dieter also reported smoketest going from 1060->1200 fps.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-12 00:43:07 +00:00
Dave Airlie e37db93246 radv: trim buffer load result (fixes dota2)
Running dota2 since the below commit crashes with an llvm assert.

Trim the vector like the other user. This possible could also be
avoided by not padding inside the load vec3->vec4.

Fixes: 41c36c4549 (amd/common: use ac_build_buffer_load() for emitting UBO loads)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-12 00:41:55 +00:00
Dylan Baker 2083a14179 meson: Use dependencies for nir
This creates two new internal dependencies, idep_nir_headers and
idep_nir. The former encapsulates the generation of nir_opcodes.h and
nir_builder_opcodes.h and adding src/compiler/nir as an include path.
This ensures that any target that needs nir headers will have the
includes and that the generated headers will be generated before the
target is build. The second, idep_nir, includes the first and
additionally links to libnir.

This is intended to make it easier to avoid race conditions in the build
when using nir, since the number of consumers for libnir and it's
headers are quite high.

Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
2018-01-11 15:40:02 -08:00
Dylan Baker 8e981eb2b7 meson: Use include variables
These were added after adderlib was mesonified, but it still good to use
them instead of open coding them.

Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
2018-01-11 15:40:02 -08:00
Dylan Baker fbf192a67e meson: Use consistent style
Currently the meosn build has a mix of two styles:
arg : [foo, ...
       bar],

and
arg : [
  foo, ...,
  bar,
]

For consistency let's pick one. I've picked the later style, which I
think is more readable, and is more common in the mesa code base.

v2: - fix commit message

Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
2018-01-11 15:40:02 -08:00
Timothy Arceri 30c1a93f6d ac/nir: fix translation of nir_op_fsign for doubles
Without this we end up with the llvm error message:

"Both operands to a binary operator are not of the same type!"

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-12 09:29:18 +11:00
Timothy Arceri d7b6b8ba52 ac: add f64_0 to the llvm build context
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-12 09:29:18 +11:00
Timothy Arceri 7b971c828a ac/nir: fix translation of nir_op_frcp for doubles
Without this we end up with the llvm error message:

"Both operands to a binary operator are not of the same type!"

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-12 09:29:18 +11:00
Timothy Arceri 24575c815c ac/nir: fix translation of nir_op_frsq for doubles
Without this we end up with the llvm error message:

"Both operands to a binary operator are not of the same type!"

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-12 09:29:17 +11:00
Timothy Arceri c0eb304acd ac: add f64_1 to the llvm build context
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-12 09:29:17 +11:00
Bas Nieuwenhuizen b9f4c615f8 radv: reset semaphores & fences on sync_file export.
Per spec:

"Additionally, exporting a fence payload to a handle with copy transference has the same side effects
on the source fence’s payload as executing a fence reset operation. If the fence was using a
temporarily imported payload, the fence’s prior permanent payload will be restored."

And similar for semaphores:

"Additionally, exporting a semaphore payload to a handle with copy transference has the same side
effects on the source semaphore’s payload as executing a semaphore wait operation. If the
semaphore was using a temporarily imported payload, the semaphore’s prior permanent payload
will be restored."

Fixes: 42bc25a79c "radv: Advertise sync fd import and export."
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-11 21:56:13 +01:00