Commit Graph

13268 Commits

Author SHA1 Message Date
Samuel Pitoiset bbf135db3d radv: allocate only 1 GDS OA counter for gfx10 NGG streamout
It works with just one counter.

This mitigates https://gitlab.freedesktop.org/drm/amd/-/issues/2902
quite a lot when you run dEQP-VK.transform_feedback.* in parallel on
more than 16 threads with RDNA3.

For example, on my GPU the kernel reports 16 GDS OA counters which means
that if you run VKCTS with 16 threads (ie. 16 Vulkan devices are
created) it's fine. Otherwise, the kernel might report ENOMEM.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25619>
2023-10-10 15:12:26 +00:00
Samuel Pitoiset 7c7684c656 radv: fix destroying GDS/OA BOs
Otherwise, we have dangling BO pointers in the global BO list. Not
quite sure why this hasn't been triggered before.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25623>
2023-10-10 14:31:01 +00:00
David Heidelberg 5ab60581da ci/traces: keep images for every job except the performance testing
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8354

Acked-by: Emma Anholt <emma@anholt.net>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25606>
2023-10-10 12:46:51 +00:00
Alyssa Rosenzweig c39896b17b nir: Use getters for nir_src::parent_*
First, we need to give the parent_instr field a unique name to be able to
replace with a helper.  We have parent_instr fields for both nir_src and
nir_def, so let's rename nir_src::parent_instr in preparation for rework.

This was done with a combination of sed and manual fix-ups.

Then we use semantic patches plus manual fixups:

    @@
    expression s;
    @@

    -s->renamed_parent_instr
    +nir_src_parent_instr(s)

    @@
    expression s;
    @@

    -s.renamed_parent_instr
    +nir_src_parent_instr(&s)

    @@
    expression s;
    @@

    -s->parent_if
    +nir_src_parent_if(s)

    @@
    expression s;
    @@

    -s.renamed_parent_if
    +nir_src_parent_if(&s)

    @@
    expression s;
    @@

    -s->is_if
    +nir_src_is_if(s)

    @@
    expression s;
    @@

    -s.is_if
    +nir_src_is_if(&s)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>
2023-10-10 04:58:05 -04:00
Samuel Pitoiset e1622dcca1 radv: fix IB alignment
This re-introduces "radv: fix alignment of DGC command buffers" and
"radv/amdgpu: fix alignment of command buffers" which were valid
changes.

IBs need to be aligned to the IB size requirement, not the number of
padded NOPs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25588>
2023-10-10 06:26:59 +00:00
Qiang Yu 5263a9e364 ac,radeonsi: remove unused ps prolog key fields
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
2023-10-10 11:10:20 +08:00
Qiang Yu 5ef7c54829 aco: wait memory ops done before go to next shader part
Next part don't know whether p_end_with_regs args are loaded from
memory ops or not, need to wait it's done here.

Other memory load needs to be waited too like:
  a = load_mem()
  b = ...
  if (...) {
    wait_mem(a)
    store_mem(a)
  }
  p_end_with_regs(b)

"a" still needs to be waited, otherwise next shader part regs may
be overwritten by unfinished memory loads.

Memory stores are waited too. When >=gfx10 and last VGT has no
parameter export, we need to wait all memeory stores done before
pos export (see ac_nir_export_position). So when merged shader
(ES+GS or VS+GS) is partially built, first stage needs to wait
all memory stores done, otherwise second stage don't know if
any memory stores pending before.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Signe-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10 02:36:34 +00:00
Qiang Yu 5ba68f92b4 aco: create exit block for p_end_with_regs to branch to
To handle ps discard in radeonsi part mode shader.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10 02:36:34 +00:00
Qiang Yu bf25a7f59b aco: fix assertion fail when program contains empty block
radeonsi may generate empty main shader or an empty exit block
for p_end_with_regs to jump to.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10 02:36:34 +00:00
Qiang Yu 6eb0910d45 aco: do not fix_exports when program has epilog
PS with epilog does not need to fix_exports. And radeonsi use
p_end_with_regs so does not have jump instruction at last.

radeonsi may also have exec restore instruction, so may break
before reach to p_end_with_regs.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10 02:36:34 +00:00
Qiang Yu f97a701d89 aco,radv,radeonsi: pass spi ps input ena and addr
radeonsi may pass different ena and addr when part mode shader.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10 02:36:34 +00:00
Qiang Yu c9c18d3da5 aco: compact ps expilog color export for radeonsi
radeonsi need to compact color export for ps epilog while radv does not.
radv will fill empty color slot, so won't affected by this change.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10 02:36:34 +00:00
Qiang Yu 1517aa7a8a aco,radv: add radeonsi spec ps epilog code
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10 02:36:34 +00:00
Qiang Yu 9972a385fb aco: simplify export_fs_mrt_color
It's now used by ps epilog only.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10 02:36:34 +00:00
Qiang Yu 77d5966661 aco,radv: rename ps epilog info inputs to colors
Will add other mrtz args for radeonsi.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10 02:36:34 +00:00
Qiang Yu d8fa106c17 aco,radv: remove unused ps epilog info fields
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10 02:36:34 +00:00
Qiang Yu 57b0f19582 aco: add create_fs_end_for_epilog for radeonsi
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10 02:36:33 +00:00
Qiang Yu 90c901a987 aco: handle ps outputs from radeonsi
radeonsi will keep outputs <FRAG_RESULT_DATA0.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10 02:36:33 +00:00
Qiang Yu 49250f9fc5 aco: add ps prolog generation for radeonsi
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10 02:36:33 +00:00
Qiang Yu 67244fc88a aco: remove p_end_with_regs from needs_exact()
ps needs to handle wqm:
1. main part may compute with args from prolog in wqm mode, so
   prolog need to compute these args in wqm mode too.
2. prolog and main part need to end with exact exec, so next
   shader part which inherit previous shader part's exec won't
   do valid job for helper threads

1 need p_end_with_regs to operate in wqm mode and itself can't
be exact, otherwise some move instruction added by it won't be
in wqm mode so helper threads' compute result is not passed to
next shader part as args.

2 is done by p_end_wqm added by finish_program automatically
after p_end_with_regs.

Piglit tests can trigger the problem:

1. gl-2.1-polygon-stipple-fs
  a. ps prolog call discard_if
  b. ps main pass wqm exec to epilog
  c. ps epilog export color for discarded pixel

2. fs-fwidth-color.shader_test
  a. ps prolog need to pass args computed in wqm mode
  b. set p_end_with_regs to exact will end wqm mode before
     the move instructions, so helper threads's result is not
     passed to next shader part

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10 02:36:33 +00:00
Qiang Yu 80728a2e71 aco: do not eliminate final exec write when p_end_with_regs block
p_end_with_regs just partially end the program, next part need
exec mask to be set correctly. For example p_end_wqm will generate
a exec restore from WQM mode after p_end_with_regs.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10 02:36:33 +00:00
Qiang Yu 38530b808e ac,radeonsi: move ps arg pos_fixed_pt to ac_shader_args
It's a HW init reg, not driver spec user sgpr. radv just
doesn't use it. Move it to amd common for aco ps prolog
usage.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10 02:36:33 +00:00
Samuel Pitoiset 3c61fd029b radv: fix re-emitting streamout descriptors for NGG streamout
In a scenario like:
CmdBindTransformFeedbackBuffers()
BeginTransformFeedback()
CmdDraw() --> streamout descriptors emitted
EndTransformFeedback() --> streamout descriptors emitted as 0 (disabled)
CmdDraw()
BeginTransformFeedback()
CmdDraw() --> streamout descriptor not re-emitted
EndTransformFeedback()

Fix this by re-emitting streamout descriptors when streamout is
enabled/disabled because a buffer size of 0 acts like a disable bit.

This fixes dEQP-VK.transform_feedback.simple.backward_dependency_indirect*
on NAVI31.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25583>
2023-10-06 22:51:31 +00:00
Eric Engestrom 82e342888f ci: skip dEQP-VK.api.driver_properties.conformance_version for everyone
This test checks the driver's reported conformance version against the
version of the CTS we're running. This check fails every few months
and everyone has to go and bump the number in every driver.

Running this check only makes sense while preparing a conformance
submission, so skip it in the regular CI.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25519>
2023-10-06 17:37:20 +00:00
Samuel Pitoiset 752fba4643 radv: fix gang submissions with chaining
Gang submissions are mostly only be used for task shaders to both
submit GFX and ACE command buffers in the same submission. Though,
the gang leader (the last submitted CS) IP type should match the
queue IP type to determine which fence to signal.

But if chaining is enabled, it's possible that all GFX cmdbufs are
chained to the first GFX cmdbuf, which means the last CS is ACE and
not GFX.

Fix this by resetting chaining for GFX when a cmdbuffer has GFX+ACE.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9724
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24966>
2023-10-06 12:42:33 +00:00
Samuel Pitoiset f233a73c1c radv: fill the scratch BO in radv_fill_shader_rings()
Cleanup.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25529>
2023-10-06 12:09:46 +00:00
Samuel Pitoiset 4192e01dcc radv: always write the sample positions when a new descriptor BO is created
This was completely broken, for example in the following scenario:
- submits something which needs sample positions (this creates a new
descriptor BO with sample positions)
- submits something which needs the tess rings (this creates a new
descriptor BO with tess rings but without sample positions, ie.
add_sample_positions would be FALSE)
- submits something which needs sample positions again (this won't
create a new descriptor BO because it incorrectly remembered that
sample positions were set)

Fix this by always writing the sample positions.

This should fix the following flakes:
- dEQP-VK.fragment_shading_barycentric.*.weights.pipeline_topology_dynamic.msaa_interpolate_at_sample.*
- dEQP-VK.pipeline.fast_linked_library.multisample_interpolation.sample_interpolate_at_distinct_values.*
- dEQP-VK.pipeline.fast_linked_library.multisample_interpolation.sample_interpolation_consistency.*
- dEQP-VK.draw.renderpass.linear_interpolation.*
- dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.linear_interpolation.*

These flakes were extremely hard to reproduce!

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25529>
2023-10-06 12:09:46 +00:00
Chia-I Wu dcb764b0f0 radv: hard code format features for emulated formats
The format features are known.  No need to rely on
radv_is_sampler_format_supported which will not work for ASTC.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25071>
2023-10-06 00:55:18 +00:00
Chia-I Wu 99e54c39f6 radv: simplify view format override for emulated formats
Override the view format to the format of plane 1 when the view format
is also emulated.  There is no functional change.

v2: check iview->vk.format directly (@yogeshmohan)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25071>
2023-10-06 00:55:18 +00:00
Chia-I Wu 55b7d6e5a3 radv: add radv_is_format_emulated
This is a cleanup with no functional change.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25071>
2023-10-06 00:55:18 +00:00
Chia-I Wu 9eda61c931 vulkan/runtime, radv: remove 1D support from ETC2 emulation
The nir code deos not support 1D.  There is also no point in supporting
1D ETC2 images.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25071>
2023-10-06 00:55:18 +00:00
Chia-I Wu afdbeaf1b4 radv: use vk_tecompress_etc2 from the runtime
There are some minor differences

 - fix incorrectly use of device->meta_state.resolve_compute.p_layout
 - when on_demand is true, the creation of ds and pipeline layouts are
   also deferred
 - unlike radv_meta_get_view_type, vk_texcompress_etc2_image_view_type
   returns 1d/2d array image views

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25071>
2023-10-06 00:55:18 +00:00
Georg Lehmann 7b4f0e714c aco/gfx11: support vinterp as fma_mix
Totals from 718 (0.94% of 76572) affected shaders:
Instrs: 657897 -> 654219 (-0.56%)
CodeSize: 3471668 -> 3457352 (-0.41%); split: -0.41%, +0.00%
VGPRs: 34200 -> 34164 (-0.11%)
Latency: 11687698 -> 11677030 (-0.09%); split: -0.10%, +0.00%
InvThroughput: 1455371 -> 1451537 (-0.26%); split: -0.26%, +0.00%
VClause: 7598 -> 7600 (+0.03%)
SClause: 18293 -> 18241 (-0.28%); split: -0.44%, +0.15%
Copies: 34641 -> 34644 (+0.01%); split: -0.05%, +0.06%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25220>
2023-10-05 20:02:53 +00:00
Georg Lehmann 7d7657ef74 aco: support v_fma_f32_dpp as fma_mix
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25220>
2023-10-05 20:02:53 +00:00
Georg Lehmann 5e9fad48bf aco/gfx11: apply clamp/omod to vinterp
Totals from 2504 (3.27% of 76572) affected shaders:
MaxWaves: 74098 -> 74106 (+0.01%)
Instrs: 1829278 -> 1823427 (-0.32%); split: -0.32%, +0.00%
CodeSize: 9775908 -> 9759308 (-0.17%); split: -0.18%, +0.01%
Latency: 13494107 -> 13485390 (-0.06%); split: -0.10%, +0.04%
InvThroughput: 2052428 -> 2048724 (-0.18%); split: -0.18%, +0.00%
VClause: 26637 -> 26640 (+0.01%); split: -0.04%, +0.05%
SClause: 62027 -> 61988 (-0.06%); split: -0.14%, +0.08%
Copies: 73776 -> 73815 (+0.05%); split: -0.07%, +0.12%
PreVGPRs: 84403 -> 84397 (-0.01%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25220>
2023-10-05 20:02:53 +00:00
Marek Olšák 7196b5318d Revert "ac/gpu_info: replace ib_alignment with per-IP IB base and size alignments"
This reverts commit b6f435888b.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25558>
2023-10-05 19:12:29 +00:00
Marek Olšák 5f42a21dad Revert "ac/gpu_info: pad IBs according to ib_size_alignment"
This reverts commit 4f660f9937.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25558>
2023-10-05 19:12:29 +00:00
Marek Olšák 461cb2fd77 Revert "radv: fix alignment of DGC command buffers"
This reverts commit b01e874234.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25558>
2023-10-05 19:12:29 +00:00
Marek Olšák 94f117ec9b Revert "radv/amdgpu: fix alignment of command buffers"
This reverts commit 4bc58c9f11.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25558>
2023-10-05 19:12:29 +00:00
Marek Olšák b4be110333 Revert "ac/gpu_info: override ib_size_alignment for VCN_DEC and JPEG"
This reverts commit 867a995ce7.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25558>
2023-10-05 19:12:29 +00:00
Samuel Pitoiset 2e5d2df362 radv/ci: cleanup list of expected failures for NAVI10/NAVI21/VEGA10
These are flakes, not failures. Remove them from the list of expected
failures to avoid confusion.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25557>
2023-10-05 15:08:37 +00:00
Samuel Pitoiset 0c4b4000aa radv/ci: remove no longer existing test for VANGOGH
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25557>
2023-10-05 15:08:37 +00:00
Samuel Pitoiset be32502979 radv: fix synchronization with emulated GS primitives/invocations queries
Move emitting the EOP even which writes the availability bit after the
GDS copy to ensure it's available.

This should fix all GS primitives/invocations flakes in CI.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25457>
2023-10-05 14:17:56 +00:00
Samuel Pitoiset f2819c3870 radv/ci: exclude dEQP-VK.texture.explicit_lod.2d.sizes.128x128_* for all jobs
These tests usually take more than 20s to finish which is slow.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25556>
2023-10-05 12:34:59 +00:00
Samuel Pitoiset aabf53ce6b radv/ci: remove duplicate skipped tests for RAVEN/STONEY
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25556>
2023-10-05 12:34:59 +00:00
Georg Lehmann 34d8fa6185 aco/gfx11: optimize dual source export
We can combine dpp with the v_cndmask_b32.

Foz-DB Navi31:
Totals from 222 (0.28% of 79330) affected shaders:
Instrs: 564392 -> 563373 (-0.18%); split: -0.19%, +0.01%
CodeSize: 2867040 -> 2864728 (-0.08%); split: -0.09%, +0.01%
Latency: 4278957 -> 4275199 (-0.09%); split: -0.09%, +0.00%
InvThroughput: 586636 -> 585824 (-0.14%); split: -0.14%, +0.00%
SClause: 20210 -> 20211 (+0.00%); split: -0.02%, +0.02%
Copies: 39763 -> 39778 (+0.04%); split: -0.13%, +0.17%
PreVGPRs: 13924 -> 13922 (-0.01%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25541>
2023-10-05 10:37:34 +00:00
Marek Olšák 9f569acf20 ac/surface: don't require exact pitch for gfx6-8 tiled imports
It was reported that it broke Stoney. Something probably uses a suboptimal
pitch, like minigbm.

Fixes: 7d066330e0 - ac/surface: relax custom pitch requirements to any multiple of 256B on gfx10.3+

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25540>
2023-10-05 07:27:02 +00:00
Leo Liu 867a995ce7 ac/gpu_info: override ib_size_alignment for VCN_DEC and JPEG
With the commit 4f660f99 ("ac/gpu_info: pad IBs according to ib_size_alignment"),
we found kernel isn't reporting ib_base/size_alignment correctly, thus causing
VCN_DEC and JPEG functions broken. We will fix the kernel and bump the kernel
version, and now for the older kernel, we need this override.

closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9916

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25511>
2023-10-04 22:58:47 +00:00
Rhys Perry 1a268dc59d aco: disable FI for quad/masked swizzle
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8330
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25525>
2023-10-04 18:53:43 +00:00
Rhys Perry ad5be40303 nir: add fetch inactive index to quad_swizzle_amd/masked_swizzle_amd
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25525>
2023-10-04 18:53:43 +00:00