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150735 Commits

Author SHA1 Message Date
Samuel Pitoiset
bb90d29660 aco: add p_dual_src_export_gfx11 for dual source blending on GFX11 
Dual source blending must be in strict WQM mode.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19643>
 2022-11-16 18:35:10 +00:00
David Heidelberg
e93de8a75e dzn: add triangle_strip flake 
Reference: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7672

Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19782>
 2022-11-16 17:49:50 +00:00
Gert Wollny
35d6e290e4 r600/sfn: Fix location for reading cube array image dimensions 
Fixes: 79ca456b48
        r600/sfn: rewrite NIR backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19755>
 2022-11-16 17:22:04 +00:00
Gert Wollny
d1a81db9ee r600/sfn: set finalize_nir after reading debug flags 
Fixes: a81c50a214 (upstream/main)
    r600/sfn: implement finalize_nir

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19755>
 2022-11-16 17:22:04 +00:00
Gert Wollny
0ccf7ed791 r600/sfn: Honor shader key w.r.t. atomic counter layout 
Fixes: 79ca456b48
        r600/sfn: rewrite NIR backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19755>
 2022-11-16 17:22:04 +00:00
Georg Lehmann
6d02054047 aco: Combine v_cvt_u32_f32 with insert to v_cvt_pk_u8_f32. 
No Foz-DB difference on Navi21.

Foz-DB GFX11:
Totals from 746 (0.55% of 134913) affected shaders:
CodeSize: 8430248 -> 8416128 (-0.17%); split: -0.17%, +0.00%
Instrs: 1617202 -> 1614707 (-0.15%)
Latency: 13943398 -> 13934161 (-0.07%); split: -0.07%, +0.00%
InvThroughput: 2601620 -> 2596624 (-0.19%); split: -0.20%, +0.01%
Copies: 114346 -> 114334 (-0.01%); split: -0.01%, +0.00%
PreVGPRs: 48314 -> 48312 (-0.00%)

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18492>
 2022-11-16 16:49:04 +00:00
Samuel Pitoiset
5a3cc2d453 aco: fix missing SCC for p_interp_gfx11 in emit_interp_mov_instr() 
Fixes: 369c9b6425 ("aco: fix p_interp_gfx11 to not overwrite SCC")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19777>
 2022-11-16 15:59:56 +00:00
Alyssa Rosenzweig
c567e5528f panfrost: Use PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY 
..instead of 4BYTE_ALIGNED_ONLY. This is more correct and avoids
needless repacking. Noticed in Firefox, which was hitting the vbuf
translate path.

Fixes: e03622e50f ("panfrost: Set STRIDE_4BYTE_ALIGNED_ONLY")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19761>
 2022-11-16 15:40:37 +00:00
Alyssa Rosenzweig
42212a9bfd panfrost: Fix reference counting with batch->resources 
Refactor accesses to batch->resources to happen through safe helpers
that update the appropriate bookkeeping. This makes it obvious that (in
particular) reference counts are updated when they should be.

The functional change is that we are now correctly unreferencing
resources during shadowing, fixing a leak of shadowed resources.

Closes: #7362
Fixes: 2d8f28df73 ("panfrost: Replace resource shadowing flush")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reported-by: Mastodon, apparently
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19753>
 2022-11-16 15:20:33 +00:00
David Heidelberg
6b87bad993 r300: use drm_shim_override 
Acked-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19692>
 2022-11-16 14:37:47 +00:00
Pavel Ondračka
65ffcee23d meson: build radeon drm-shim also for r300 and r600 
Right now the drm-shim is build only when one also builds radeonsi
or radv.

Acked-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19692>
 2022-11-16 14:37:47 +00:00
Joshua Ashton
c699122d6a turnip: Enable EXT_swapchain_colorspace 
This extension is basically a no-op exposing some new enums.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19726>
 2022-11-16 14:07:45 +00:00
Joshua Ashton
55b6813b7b anv: Enable EXT_swapchain_colorspace 
This extension is basically a no-op exposing some new enums.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19726>
 2022-11-16 14:07:45 +00:00
Joshua Ashton
5637a1b91e radv: Enable EXT_swapchain_colorspace 
This extension is basically a no-op exposing some new enums.

Signed-off-by: Joshua Ashton <joshua@froggi.es>

Reviewed-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19726>
 2022-11-16 14:07:45 +00:00
Joshua Ashton
0b9beb5107 wsi/display: Refactor available_surface_formats structure 
Pack the VkSurfaceFormatKHR in here so we can expose formats +
color spaces in one.

This will be needed for exposing HDR color spaces such as
VK_COLOR_SPACE_HDR10_ST2084_EXT.

Signed-off-by: Joshua Ashton <joshua@froggi.es>

Reviewed-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19726>
 2022-11-16 14:07:45 +00:00
José Roberto de Souza
d6c58f5446 iris: Destroy batch contexts in a single place 
While at it also moving has_engines_context to iris_context, no need
to have this information replicated into every iris_batch.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19687>
 2022-11-16 13:38:30 +00:00
José Roberto de Souza
cd159c7d6c iris: Set priority for replaced engine context 
The replace_kernel_ctx() code path was not setting back the context
priority.

Fixes: 5c4c8bdc4c ("iris/batch: Add support for engines contexts")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19687>
 2022-11-16 13:38:30 +00:00
Matt Coster
f7e7fa6e5f pvr: Fix valgrind issue on compute job submissions 
When no flags are set, submit_info->flags is uninitialized. This is not
a problem in the render codepath as the equivalent submit_info is
zeroed before being filled in.

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19740>
 2022-11-16 13:28:34 +00:00
Samuel Pitoiset
cd2e2021a0 radv: emit PA_SU_PRIM_FILTER_CNTL in the graphics preamble 
This register doesn't change.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19654>
 2022-11-16 13:02:14 +00:00
Samuel Pitoiset
d4ce63a87a radv: determine if sample positions are needed at pipeline bind time 
Like other ring stuff that depends on pipelines.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19654>
 2022-11-16 13:02:14 +00:00
Samuel Pitoiset
5c9ade2464 radv: simplify load_sample_mask_in lowering 
From the Vulkan spec:
    "Sample shading is enabled if at least one of the following
     conditions is true:

     - VkPipelineMultisampleStateCreateInfo::sampleShadingEnable is
       set to VK_TRUE, or
     - the fragment shader’s entry point interface includes input
       variables decorated with a BuiltIn of SampleId or SamplePosition
       built-ins."

We don't need to pass the number of rasterization samples, checking
for sample shading is enough. This will help for dynamic rasterization
samples.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19654>
 2022-11-16 13:02:14 +00:00
Lucas Stach
0097592f8c etnaviv: rs: set TS_MODE for inplace resolve 
When using the inplace resolve the TS_MODE isn't taken from the
RS_SOURCE_STRIDE state, but need to be set in RS_EXTRA_CONFIG.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19751>
 2022-11-16 12:53:28 +00:00
Lucas Stach
7d370d80ed etnaviv: update headers from rnndb 
Update to etna_viv commit 59403372cb48.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19751>
 2022-11-16 12:53:28 +00:00
Lucas Stach
78c71d14e0 etnaviv: don't select TS modifier when not FAST_CLEAR capable 
When presented with a list of modifiers to choose from we must never
pick a shared TS modifier if the local instance isn't FAST_CLEAR capable.

Fixes: c2b06e1a38 ("etnaviv: add support for sharing the TS buffer")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19751>
 2022-11-16 12:53:28 +00:00
Martin Roukala (né Peres)
6e3fc88f0c radv/ci: mark the whole texturequerylod subtests as flakes on renoir 
Seems like we keep on getting more of these flakes, so let's be a bit
broader.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19742>
 2022-11-16 12:20:29 +00:00
Yonggang Luo
e70362e747 gallium/pipe: Trim trailing spaces in src/gallium/include/pipe/*.h 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19545>
 2022-11-16 11:21:01 +00:00
Samuel Pitoiset
1b8e66e564 radv: rework how vertex buffer descriptors are flushed 
Dirty the flag at pipeline bind time, instead of passing this useless
pipeline_is_dirty flag.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19724>
 2022-11-16 10:07:18 +00:00
Samuel Pitoiset
0945412ec8 radv: use more radv_dynamic_state pointers in radv_emit_XXX() helpers 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19678>
 2022-11-16 08:06:37 +00:00
Samuel Pitoiset
86d9a4f20f radv: cleanup radv_emit_viewport() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19678>
 2022-11-16 08:06:37 +00:00
Samuel Pitoiset
2bb76d579c radv: constify more pointers in radv_emit_XXX() helpers 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19678>
 2022-11-16 08:06:37 +00:00
Samuel Pitoiset
34d81d264b radv: cleanup radv_CmdSetXXX() functions 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19678>
 2022-11-16 08:06:37 +00:00
Samuel Pitoiset
fc193133d4 aco: adjust an assertion about nir_texop_txf_ms and GFX11 
This can fail with RADV_DEBUG=nofmask.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19613>
 2022-11-16 07:59:15 +01:00
Samuel Pitoiset
cf7b96a83f radv: introduce RADV_DEBUG=nofmask 
To disable MSAA compression on MSAA images. This will also allow us to
emulate GFX11 (FMASK has been removed) and to experiment 32 byte
descriptor sizes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19613>
 2022-11-16 07:59:11 +01:00
Rob Clark
35c78d4f15 freedreno/a6xx: Fix dummy binning pass FS shader 
No changes, but it looks funning to see in the binning pass that FS uses
r0 and hr0.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19710>
 2022-11-16 03:44:06 +00:00
Rob Clark
2de0a031ea freedreno/a6xx: Un-open-code some event names 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19710>
 2022-11-16 03:44:06 +00:00
Rob Clark
0132c22de7 freedreno/a6xx: Don't disable LRZ for invalid channels 
Similar idea to commit ("c9db71c8ba1 turnip: Don't disable LRZ for color
write mask channels beyond the format's"), but different implementation.
If the blend state masks writes to a color channel that doesn't exist,
that doesn't mean we need to disable LRZ write.  In particular, this
scenario will come up with z-prepasses (doh!)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19710>
 2022-11-16 03:44:06 +00:00
Rob Clark
4e9d913f81 freedreno/a6xx: Improve LRZ test for stencil write 
If all the ops are KEEP, we don't actually write the stencil, and can
avoid falling off the LRZ fastpath.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19710>
 2022-11-16 03:44:06 +00:00
Rob Clark
d03d08668f freedreno/a6xx: Use same LRZ state for draw and binning 
Originally these where split as that is what the blob GL driver did (at
least at the time).  But that turns out to be unnecessary, so simplify
things and combine them into a single LRZ state object like tu does.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19710>
 2022-11-16 03:44:06 +00:00
Rob Clark
2b186016a3 freedreno/a6xx: Handle additional depth test funcs 
These were left as a TODO, and we forgot to revisit.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19710>
 2022-11-16 03:44:06 +00:00
Rob Clark
edca30efbf freedreno/drm: Fix suballoc alignment 
IBO/etc descriptors need to be aligned to 64.. this was handled
correctly in the stateobj case (for tex descriptors) but not in
the streaming case (for IBO).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19710>
 2022-11-16 03:44:06 +00:00
Alyssa Rosenzweig
cf6b2699ca panfrost: Don't set job_barrier on vertex jobs 
This was a hack needed for the old transform feedback code. This barrier
is handled by the explicit XFB emulation that we're using on Midgard
now, so we don't need the barrier in the general case.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19760>
 2022-11-16 02:45:14 +00:00
Pavel Ondračka
51457b19ce r300: tweak nir loop unrolling hint for r500 vertex shaders 
This should prevent some cxbx-r shaders from unrolling above the
instruction limit and results in 3 gained cxbx-r shaders on RV530
with no other changes in shader-db.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5967

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19702>
 2022-11-15 22:55:38 +00:00
Yonggang Luo
6ac678df43 freedreno: Add one flake 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7713

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19759>
 2022-11-15 22:24:44 +00:00
M Henning
f3ee9be836 glsl: Drop borrow/carry lowerings in favor of nir 
Unconditionally lowering prevents GL drivers from natively
implementing these ops. Drivers that need lowering should set
lower_uadd_carry and lower_usub_borrow on nir_shader_compiler_options to
get the nir lowerings.

Tested with dEQP-GLES31.functional.shaders.builtin_functions.integer.*

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19704>
 2022-11-15 21:51:04 +00:00
Chia-I Wu
339d80d5f2 pps: make pps-producer RT only on freedreno 
Calling sched_setscheduler twice every sample period has high CPU
overhead.  For intel and panfrost, their dump_perfcnt is preemptible and
they don't need the scheduler change.

For freedreno, simply makes the main thread RT at all time.  This solves
most of the cpu overhead issue.

v2: removed pthread_t param and just change the scheduler for the
    calling thread

Acked-by: Rob Clark <robdclark@chromium.org> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19668>
 2022-11-15 21:21:42 +00:00
Yonggang Luo
557120b593 util: Include the needed util/detect*.h headers in multiple files 
This is discovered either by manually or -W-no-def option

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19674>
 2022-11-15 20:35:55 +00:00
Yonggang Luo
4ff21b4a47 util: Remove the unused PIPE_(ARCH|OS|CC) macro defines from src/util/detect_arch.h and src/util/detect_cc.h 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19674>
 2022-11-15 20:35:55 +00:00
Yonggang Luo
1accc0df64 tree-wide: Convert all usage of PIPE_(OS|ARCH|CC)_* to DETECT_(OS|ARCH|CC)_* by use grep 
This should be the last commit, and should be take care that can only in comment block or
version
Exclude files:
src/util/detect_*.h

From:
PIPE_(OS|ARCH|CC)_([0-9A-Z_]+)
To:
DETECT_$1_$2

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19674>
 2022-11-15 20:35:55 +00:00
Yonggang Luo
27fe4bd29f tree-wide: Convert all usage of #ifndef PIPE_(OS|ARCH|CC)_* to #if DETECT_(OS|ARCH|CC)_* by use grep 
From:
#ifndef[\s]+PIPE_(OS|ARCH|CC)_([0-9A-Z_]+)
To:
#if !DETECT_$1_$2

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19674>
 2022-11-15 20:35:55 +00:00
Yonggang Luo
1817659bb6 tree-wide: Convert all usage of #ifdef PIPE_(OS|ARCH|CC)_* to #if DETECT_(OS|ARCH|CC)_* by use grep 
From:
#ifdef[\s]+PIPE_(OS|ARCH|CC)_([0-9A-Z_]+)
To:
#if DETECT_$1_$2

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19674>
 2022-11-15 20:35:55 +00:00