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Author SHA1 Message Date
Lionel Landwerlin ba3ff8b3bb brw: move barycentric_mode enum to intel_shader_enums.h 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32329>
 2024-11-26 13:05:30 +00:00
Lionel Landwerlin bfcb9bf276 brw: rename brw_sometimes to intel_sometimes 
Moving it to intel_shader_enums.h

The plan is to make it visible to OpenCL shaders.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32329>
 2024-11-26 13:05:30 +00:00
Lionel Landwerlin 9016a5458a brw: change fs_msaa flags checks to test compiled flag first 
There should be no functional change here. This is just trying to make
things more clear, we use the compiled value if != BRW_SOMETIMES and
otherwise use the dynamically computed flags.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32329>
 2024-11-26 13:05:30 +00:00
Lionel Landwerlin 54e6a8b019 anv: split runtime flushing code for reuse 
We'll want to reuse some of this for device generated commands.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32329>
 2024-11-26 13:05:30 +00:00
Lionel Landwerlin d9d1894bb9 anv: move tracking of tcs_input_vertices/fs_msaa_flags to hw state 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32329>
 2024-11-26 13:05:30 +00:00
Lionel Landwerlin d1795a73e2 anv: move gfx tracking values to anv_cmd_graphics_state 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32329>
 2024-11-26 13:05:30 +00:00
Lionel Landwerlin db258503fa anv: split vertex buffer emission in a different function 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32329>
 2024-11-26 13:05:30 +00:00
Lionel Landwerlin 195350c5da anv: rework vertex input helper 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32329>
 2024-11-26 13:05:30 +00:00
Lionel Landwerlin c4e7578fa6 anv: pass anv_device to batch_set_preemption 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32329>
 2024-11-26 13:05:30 +00:00
Lionel Landwerlin c36f7e42a7 anv: remove 3DSTATE_VF_STATISTICS from pipeline 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32329>
 2024-11-26 13:05:29 +00:00
Lionel Landwerlin ce40a1e05b anv: remove 3DSTATE_MULTISAMPLE from the pipeline 
We can make this completely dynamic, there is no information from the
pipeline.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32329>
 2024-11-26 13:05:29 +00:00
Lionel Landwerlin 2b49249a4d anv: remove 3DSTATE_RASTER from pipeline 
At a pipeline level, we only put fixed values in this instruction.
Might has well put that in the final emission and avoid :
  - store the instruction on the anv_graphics_pipeline
  - diff the instructions between pipelines

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32329>
 2024-11-26 13:05:29 +00:00
Lionel Landwerlin 9d8950e435 anv: move helpers out of genX_pipeline.c/anv_private.h 
Those are only used in genX_gfx_state.c

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32329>
 2024-11-26 13:05:29 +00:00
Tapani Pälli 19b6991160 anv/android: always create 2 graphics and compute capable queues 
Android hwui requires 2 queues.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32279>
 2024-11-24 16:39:33 +00:00
Caio Oliveira 0c0b61b029 intel/brw: Dump IR after lower scoreboard pass 
Acked-by: Iván Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32269>
 2024-11-22 21:47:46 +00:00
Caio Oliveira 90343f452d intel/brw: Fix SWSB output when printing IR 
The printing routine was ignoring dependencies that
were only unordered.

Acked-by: Iván Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32269>
 2024-11-22 21:47:46 +00:00
Caio Oliveira 1d704af515 intel/brw: Fix decoding of cond_modifier and saturate in EU validation 
These fields are only valid in certain formats, so set them accordingly.
Note the check if !is_send is used because FORMAT_BASIC is reused for
SEND/SENDS in some platforms.  If we start to see more cases like that,
we can create a new FORMAT for it.

The cond_modifier is trickier because on top of that, it is not valid
for 64-bit immediates in some platforms.  Found when EU validation
complained about moving 64-bit immediates with higher bits.

Fixes: e4440df2d8 ("intel/brw: Add pred/cmod/sat to brw_hw_decoded_inst")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32287>
 2024-11-22 21:15:46 +00:00
Nanley Chery 385080fb92 intel: Allow CCS on 3D surfaces for gfx120 
According to HSD 1406738321, full resolves and fast-clears don't work
properly on 3D textures. Up until now, we've disabled CCS for this case.
Instead, redescribe the surface as 2-dimensional to perform auxiliary
surface operations.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31880>
 2024-11-22 20:11:43 +00:00
Nanley Chery 84208d514e intel/isl: Allow CCS on 3D 64bpp+ Tile64 
The restriction is incorrectly tagged for gfx12.5.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31880>
 2024-11-22 20:11:43 +00:00
Nanley Chery e32203827a intel/blorp: Assert 3D Ys fast-clear restriction 
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31880>
 2024-11-22 20:11:43 +00:00
Caio Oliveira 9383a62d95 intel/executor: Enable PTL 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32196>
 2024-11-22 10:26:12 -08:00
Eric Engestrom ad42be50c9 ci/deqp: fully isolate deqp builds 
Since the builds can be from very different versions of the code, we
need to make sure the common bits are compiled from the correct code.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32250>
 2024-11-22 10:16:49 +00:00
Lionel Landwerlin b44faa22ab anv: document the X4 Foundations workaround a bit more 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32297>
 2024-11-22 10:19:26 +02:00
Lionel Landwerlin 0fa3be44aa anv: add a workaround for X4 Foundations 
This title incorrectly tries to allocate descriptor sets larger than
the number of sampler items in the descriptor pool.

Workaround by taking other largest item count in the descriptor pool
and use that for samplers.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11795
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lina Versace <lina@kiwitree.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32285>
 2024-11-22 06:44:34 +00:00
Lionel Landwerlin 14d8da4c3c anv: indent driconf code 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lina Versace <lina@kiwitree.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32285>
 2024-11-22 06:44:34 +00:00
Lionel Landwerlin d483f7d984 anv: track allocated descriptor pool sizes 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lina Versace <lina@kiwitree.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32285>
 2024-11-22 06:44:34 +00:00
Caio Oliveira 3e2599d475 intel/brw: Use <V,W,H> notation for FIXED_GRF and ARF source when printing IR 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32260>
 2024-11-21 17:36:34 -08:00
Caio Oliveira 71d362db66 intel/brw: Omit type and region in payload sources when printing IR 
These are not really used since SEND messages deal with full GRFs.

Before

```
send(8) (mlen: 1) (ex_mlen: 1) (null):UD, 0u, 0u, g1:UD, g8:UD
send(8) (mlen: 1) g5:UD, 0u, 0u, g4:UD, (null):UD
send(8) (mlen: 1) (ex_mlen: 1) (null):UD, 0u, 16777216u, g1:D, g6:UD
send(8) (mlen: 1) (EOT) (null):UD, 0u, 0u, g126:UD, (null):UD NoMask
```

and after

```
send(8) (mlen: 1) (ex_mlen: 1) (null), 0u, 0u, g1, g8
send(8) (mlen: 1) g5, 0u, 0u, g4, (null)
send(8) (mlen: 1) (ex_mlen: 1) (null), 0u, 16777216u, g1, g6
send(8) (mlen: 1) (EOT) (null), 0u, 0u, g126, (null) NoMask
```

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32259>
 2024-11-22 00:50:40 +00:00
Caio Oliveira 8474dc853d intel/brw: Add SHADER_OPCODE_QUAD_SWAP 
For the horizontal, vertical and diagonal variants.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31053>
 2024-11-22 00:27:01 +00:00
Tapani Pälli c2b7bafd76 intel/dev: lower amount of max gs threads for Wa_18040209780 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32245>
 2024-11-21 20:43:38 +00:00
Tapani Pälli 7117e14026 intel/dev: update mesa_defs.json from workaround database 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32245>
 2024-11-21 20:43:38 +00:00
Caio Oliveira 2bd7592b0b intel/brw: Add SHADER_OPCODE_BALLOT 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31052>
 2024-11-21 19:32:59 +00:00
Eric Engestrom 5ba6200b99 intel/ci: add missing .intel-common-manual-rules to .{iris,crocus,i915g}-manual-rules 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32278>
 2024-11-21 11:37:01 +00:00
Eric Engestrom 5ffd170033 intel/ci: disable CML jobs because of networking issues 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32278>
 2024-11-21 11:37:01 +00:00
Guilherme Gallo 2e8e14fa9f ci/iris: Update iris-cml-deqp CI expectations 
One test has timed out when the parallel number changed.
And other one flaked.
Both are inside the `KHR-Single-GL46.arrays_of_arrays_gl` test group.
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/66875845

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32163>
 2024-11-21 04:10:52 +00:00
Guilherme Gallo 17e36bc894 ci/iris: Fix iris-cml-traces expectations 
The results just changed a tiny bit, nothing relevant, so let's update
the traces checksums.

See also:
https://mesa.pages.freedesktop.org/-/mesa/-/jobs/66830844/artifacts/results/summary/problems.html

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32163>
 2024-11-21 04:10:52 +00:00
Guilherme Gallo 9b567a59f4 ci/iris: Rebalance iris-cml-deqp jobs 
There are more puffs available in the farm, so let's use them to reduce
from 20 minutes on average to 10 minutes.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32163>
 2024-11-21 04:10:52 +00:00
Guilherme Gallo b15eeff992 ci/iris: Force UART for puff boards 
We are expericing some difficulties with the LAVA IP addressing for puff
DUTs atm, blocking the SSH session to happen smoothly.

So, let's force the UART only communication to bypass this issue until
it is solved.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32163>
 2024-11-21 04:10:52 +00:00
Guilherme Gallo f7e7a9ed57 ci/intel: Set HWCI modules for puff DUT 
We were missing the i915 during the boot, making the intel-cml jobs fail

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32163>
 2024-11-21 04:10:52 +00:00
Lina Versace 56116c4da5 anv: Fix feature pipelineProtectedAccess 
We enable VK_EXT_pipeline_protected_access only if
anv_physical_device::has_protected_contexts. Therefore we should do the
same for vk_features::pipelineProtectedAccess.

Fixes: 0b5408f ("anv: expose VK_EXT_pipeline_protected_access")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32206>
 2024-11-20 04:31:54 +00:00
Lina Versace 906b1a0678 anv: Sort extensions in enablement table 
Several extensions were unsorted in
anv_physical_device.c:get_device_extensions().
The worse was an EXT found between INTEL/NV.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32205>
 2024-11-20 03:53:19 +00:00
Marek Olšák 25d4943481 nir: make use_interpolated_input_intrinsics a nir_lower_io parameter 
This will need to be set to true when the GLSL linker lowers IO, which
can later be unlowered by st/mesa, and then drivers can lower it again
without load_interpolated_input. Therefore, it can't be a global
immutable option.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32229>
 2024-11-20 02:45:37 +00:00
Caio Oliveira d918edaf9a intel/common: Enable mi_builder test for PTL 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32194>
 2024-11-20 01:47:04 +00:00
Caio Oliveira 6b931a68c7 intel/common: Implement Xe KMD in mi_builder tests 
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32194>
 2024-11-20 01:47:04 +00:00
Caio Oliveira 3998602d0e intel/common: Prepare mi_builder tests to support Xe KMD 
No functional change, just move i915 specific data to a struct
and check for kmd_type where appropriate.  This will make the
next patch (which adds Xe KMD support here) cleaner.

This patch had to make intel_kmd.h header C++ friendly so it
can use its symbols.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32194>
 2024-11-20 01:47:04 +00:00
Caio Oliveira 3735652be8 intel/common: Properly dispose resources in mi_builder tests 
Since we will already use SetUp()/TearDown(), remove the ctor/dtor
that now would be unused.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32194>
 2024-11-20 01:47:04 +00:00
Lionel Landwerlin 9b779068c3 anv: prevent access to destroyed vk_sync objects post submission 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 36ea90a361 ("anv: Convert to the common sync and submit framework")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12145
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32219>
 2024-11-19 19:40:03 +00:00
Caio Oliveira 0b66cb1f82 intel/brw: Allow extra SWSB encodings for Xe2 
There are new combinations of ordered and unordered dependencies
available for the instructions to use, which among others include:

- combining FLOAT and INT pipe deps in SENDs;
- combining SRC mode deps in regular instructions for the inferred type.

This patch enables a couple of tests checking for the first case.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31375>
 2024-11-19 04:27:00 +00:00
Caio Oliveira 1b13eea642 intel/brw: Add test for combining SWSB dependencies in SENDs 
These are currently DISABLED_ since they fail.  A later patch will
enable them.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31375>
 2024-11-19 04:27:00 +00:00
Lionel Landwerlin 8845255881 anv: fix missing push constant reallocation 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 62d96a6546 ("anv: add dirty tracking for push constant data")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12151
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30007>
 2024-11-18 16:31:33 +00:00