AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
213,726 Commits 1 Branch 0 Tags
ba293ebbc8bb9e9731fbea43a1e4776e6dbb43b7
Commit Graph

197867 Commits

Author SHA1 Message Date
Ludvig Lindau ba293ebbc8 panfrost/panvk: Reduce fills from LCRA 
Currently when LCRA spills it also fills on every single usage of the
spilled value. This leads to a lot of cases where a spill is immediately
followed by a fill.

This patch reduces fills by LCRA by simply not filling until reaching
either the index that caused LCRA to fail allocating registers, or the
end of a block.

Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37299>
 2025-10-20 09:07:31 +00:00
Ludvig Lindau a26e46980e panfrost/panvk: Merge stores in vector spills 
Make vector spills use a single store of appropriate data size instead
of using a store for every vector component.

Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37299>
 2025-10-20 09:07:31 +00:00
Jose Maria Casanova Crespo a131530dd1 v3d: mark FRAG_RESULT_COLOR as output_written on SAND blits FS 
With the introduction of "v3d: Add support for 16bit normalised
formats" https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35820
nir_lower_fragcolor is always called if shaders outputs_written shows
that FRAG_RESULT_COLOR is used.

But on SAND8/30 blit fragment shaders although the FRAG_RESULT_COLOR
is used, it was not marked as output_written so the lowering was not
applied.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14141
Fixes: ee48e81b26 ("v3d: Always lower frag color")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37949>
 2025-10-20 09:42:19 +02:00
Emma Anholt aa96444149 wsi: Fix the flagging of dma_buf_sync_file for the amdgpu workaround. 
In my regression fix, I covered one of the two paths that had stopped
setting the implicit_sync flag and thus triggered the amdgpu behavior we
don't want, but probably the less common one.

Fixes: f7cbc7b1c5 ("radv: Allocate BOs as implicit sync even if the WSI is doing implicit sync.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13942
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37874>
 2025-10-20 03:58:47 +00:00
Marek Olšák e2b271d7b1 radeonsi/ci: update hawaii failures 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37910>
 2025-10-19 17:01:44 +00:00
Marek Olšák f5b648f6d3 winsys/radeon: fix completely broken tessellation for gfx6-7 
The info was moved to radeon_info, but it was only set for the amdgpu
kernel driver. It was uninitialized for radeon.

Fixes: d82eda72a1 - ac/gpu_info: move HS info into radeon_info

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37910>
 2025-10-19 17:01:43 +00:00
Benjamin Cheng b1370e1935 radv/video: Fill maxCodedExtent caps first 
Later code (i.e. max qp map extent filling) depends on this.

Fixes: ae6ea69c85 ("radv: Implement VK_KHR_video_encode_quantization_map")
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37940>
 2025-10-17 17:58:08 +00:00
Job Noorman ad421cdf2e nir: mark fneg distribution through fadd/ffma as nsz 
df1876f615 ("nir: Mark negative re-distribution on fadd as imprecise")
fixed the fadd case by marking it as imprecise. This commit fixes the
ffma case for the same reason.

However, "imprecise" isn't necessary and nowadays we have "nsz" which is
more accurate here. Use that for both fadd and ffma.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 62795475e8 ("nir/algebraic: Distribute source modifiers into instructions")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37930>
 2025-10-17 08:58:59 +00:00
Frank Binns b9baf2c260 pvr: Advertise VK_KHR_storage_buffer_storage_class 
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37913>
 2025-10-17 08:11:11 +00:00
Frank Binns c6c0690723 pvr: Advertise VK_KHR_relaxed_block_layout 
This is already supported by the compiler and all the relevant conformance
tests pass.

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37913>
 2025-10-17 08:11:11 +00:00
Frank Binns 28cc04b400 pvr: sort extensions alphabetically 
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37913>
 2025-10-17 08:11:10 +00:00
Josh Simmons b10c1a1952 radv: Fix crash in sqtt due to uninitalized value 
Fixes: 772b9ce411 ("radv: Remove qf from radv_spm/sqtt/perfcounter where applicable")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37900>
 2025-10-17 06:10:46 +00:00
Qiang Yu 11f2babddc mesa,gallium: not touch TS when internal draws 
TS does not affect vertex pipeline draws. We keep mesh shader
before radeonsi is ready.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:19 +00:00
Qiang Yu 4711fb711c gallium/blitter: no need to save TS state 
TS does not affect blitter currently.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:19 +00:00
Qiang Yu 71e0895715 mesa,radeonsi: add comments about vertex and mesh pipeline shader states 
They are exclusive in mesa state tracker currently, so add some comments
and assertions for developers.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:19 +00:00
Qiang Yu dcf2399e6f radeonsi: save mesh shader when blit 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:19 +00:00
Qiang Yu ffc3d430db radeonsi: simplify si_update_rasterized_prim while handle mesh shader 
Otherwise mesh shader ends in the "else" section.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:19 +00:00
Qiang Yu 56a437183a radeonsi: si_get_vs support mesh shader 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:19 +00:00
Qiang Yu 7e83962e85 radeonsi: update scratch va for mesh shader 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:19 +00:00
Qiang Yu de4fb088d3 radeonsi: share some vertex pipe function with mesh pipe 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:18 +00:00
Qiang Yu e6e21dfbf2 radeonsi: kill outputs for mesh shader 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:18 +00:00
Qiang Yu 4c315bdbfa radeonsi: lower task/mesh shader io to mem 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:18 +00:00
Qiang Yu 5931dbf7ac radeonsi: add task info to screen 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:18 +00:00
Qiang Yu 73aebeec42 radeonsi: no ngg culling for mesh shader 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:17 +00:00
Qiang Yu 74894150f1 radeonsi: init pm4 state for mesh shader 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:17 +00:00
Qiang Yu ce6a1e7563 radeonsi: init mesh shader args 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:16 +00:00
Qiang Yu 2038134efc radeonsi: calc workgroup size for mesh shader 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:15 +00:00
Qiang Yu 977a3f45bf radeonsi: add task/mesh shader info to si_shader_info 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:15 +00:00
Qiang Yu 8659666089 radeonsi: add si_mesh_resources_add_all_to_bo_list 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:14 +00:00
Qiang Yu b533d39b95 radeonsi: inline uniform support mesh shader 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:14 +00:00
Qiang Yu 8a3ef188c2 radeonsi: add context shader state for mesh shader 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:13 +00:00
Qiang Yu 24d7c9a2a8 radeonsi: handle mesh shader when si_create_shader 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:12 +00:00
Qiang Yu f06a1b0d07 radeonsi: enlarge SI_NUM_SHADERS for mesh shader 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>
 2025-10-17 03:52:12 +00:00
Mike Blumenkrantz f74cf45078 zink: consistently set/unset msrtss in begin_rendering 
this has to always be set or unset, never persistent from previous renderpass

Fixes: 5080f2b6f5 ("zink: disable msrtss handling when blitting")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37923>
 2025-10-16 22:22:34 -04:00
Marek Olšák 733ba77bfe r300: fix DXTC blits 
Fixes: 9d359c6d10 - gallium: delete pipe_surface::width and pipe_surface::height
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37912>
 2025-10-16 22:33:50 +00:00
Gert Wollny ba35ac29b6 r600/sfn: drop range pinning for registers after RA 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37847>
 2025-10-16 20:57:18 +00:00
Gert Wollny 5962add398 r600/sfn: correct register interference range 
If a life range of one register starts in the same instruction where the
life range of another register ends, then
the two ranges don't overlap.

v2: Fix test

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37847>
 2025-10-16 20:57:18 +00:00
José Roberto de Souza ad86a666ae anv: Add support for low latency hint on Xe KMD 
This hint tells KMD and firmware to turn into low latency but high
power usage mode.
i915 already had it now it was implemented in Xe KMD.

Reviewed-by: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33214>
 2025-10-16 20:23:21 +00:00
José Roberto de Souza 0ba6a0a23b intel/dev: Add supports_low_latency_hint to intel_device_info 
Lets query if this feature is supported only once, also in the next
patches support for this feature will be added to Xe KMD.

Reviewed-by: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33214>
 2025-10-16 20:23:21 +00:00
Xaver Hugl 892cf427a0 vulkan/wsi: require extended target volume support for scRGB 
It's hardly going to be useful without that

Signed-off-by: Xaver Hugl <xaver.hugl@kde.org>
Fixes: 4b663d56 ("vulkan/wsi: implement support for VK_EXT_hdr_metadata on Wayland")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37920>
 2025-10-16 19:58:02 +00:00
Mary Guillemard b2accf86d1 poly: Migrate AGX's GS/TESS emulation to common code 
This moves most of the code to a new home: src/poly.
Most precomp kernels logic that could be moved are provided by poly now.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>
 2025-10-16 19:25:35 +00:00
Mary Guillemard 8048004238 asahi/gs: Reuse GS shader compiler options 
Avoid importing internal bits

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>
 2025-10-16 19:25:35 +00:00
Mary Guillemard 6f73533094 asahi,nir: Stop relying on zero and scratch page in GS/TESS code 
Introduce new NIR intrinsics to handle getting a "sink" read-only
address and another intrinsic to handle conversion of address to
read-write (allowing implementation to replace the "sink" read-only with
another address like required for Asahi)

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>
 2025-10-16 19:25:35 +00:00
Mary Guillemard 60e5abdbaa asahi: Move compiler preprocess out of agx_nir_lower_gs 
We run agx_preprocess_nir as the last step of each new compute shaders
in agx_nir_lower_gs but we could move this out of the pass and makes it
the driver responsability to call it.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>
 2025-10-16 19:25:35 +00:00
Mary Guillemard a427581c4d asahi/gs: Remove agx_nir_* prefix around static functions 
Only a small detail but git will not go too crazy when I move
everything around at least.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>
 2025-10-16 19:25:35 +00:00
Mary Guillemard 71c4943c37 compiler: rename vs.tes_agx bit to vs.tes_poly 
Preparing to move AGX's GS/TESS lowering code.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>
 2025-10-16 19:25:35 +00:00
Mary Guillemard 1e0c18d6cf nir: Rename stat_query_address_agx to stat_query_address_poly 
This is used by the geometry lowering that we are going to move to
common code.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>
 2025-10-16 19:25:35 +00:00
Mary Guillemard 8a25b88d69 asahi/libagx: Do not expose anything not use externaly 
No need to actually generate NIR bindings for anything we don't need
to.

We are going to copy most of this in Panfrost and that will be required
there...

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>
 2025-10-16 19:25:35 +00:00
Mary Guillemard 29f348941d asahi/libagx: Stop exposing fake entrypoint _libagx_prefix_sum 
This was a hack to allow things to build but still could break in the
future, let comply by passing scratch as an argument instead.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>
 2025-10-16 19:25:35 +00:00
Lionel Landwerlin c20e2733bf Revert "brw: add serialize send stats" 
This reverts commit b8ae4ede60 now that
we have a cycle estimation accounting.

Reviewed-by: Alyssa Anne Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37816>
 2025-10-16 18:55:06 +00:00