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646 Commits

Author SHA1 Message Date
Jianxun Zhang 8906816f49 anv,hasvk,genxml: Rename genxml files using verx10 
It could be confusing that a newer platform named with a smaller
number than a half-generation of an older platform like 'gfx20' and
'gfx75' in xml files.

Down the road, it can be a little worse once we pass something like
'gfx40' when there is already a gfx45.xml for the oldest platform.

Unify naming xml files with verx10 numbers to resolve the issue.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31943>
 2024-11-09 00:04:47 +00:00
Sagar Ghuge 17096f87c1 intel: Switch to COMPUTE_WALKER_BODY 
Stuff COMPUTE_WALKER_BODY in COMPUTER_WALKER in both iris and anv.

This also fixes the tracepoint for ray dispatches. Stuffing
COMPUTE_WALKER_BODY allow us to set the
cmd_buffer->state.last_compute_walker.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31822>
 2024-10-29 15:54:43 +00:00
Jordan Justen acb1c45a8b intel/genxml: Start Xe3 support 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
 2024-10-26 07:39:29 +00:00
José Roberto de Souza 2483f8f7cd intel/genxml: Do small fixes in gfx20 definition of STATE_COMPUTE_MODE 
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30796>
 2024-10-22 15:24:32 +00:00
José Roberto de Souza 86ed5ec78e intel/genxml: Append 'Z Async Throttle settings' to gfx125 definition of STATE_COMPUTE_MODE 
DG2 has the 'Force Non-Coherent' fields but MTL and ARL has
'Z Async Throttle settings', so here adding the missing one.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30796>
 2024-10-22 15:24:32 +00:00
Tapani Pälli 8cb08830e6 intel/genxml: introduce L3 Fabric Flush for gfx12 
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
 2024-10-08 08:45:40 +00:00
Rohan Garg c1af71c9c2 anv,iris: prefix the argument format with XI for a upcoming refactor 
Backport-to: 24.2
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30690>
 2024-08-20 09:41:51 +00:00
David Heidelberg c2bbdda39b intel/genxml: fix length of HCP_FQM_STATE for gen20 and 125 
Fixes: 7f280e1e93 ("intel/genxml: fix some length of HCP_FQM_STATE")
Acked-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30558>
 2024-08-08 19:43:41 +09:00
Lionel Landwerlin 8cc492cb26 genxml: unify some bits between Gfx8/Gfx11/Gfx12.5 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30539>
 2024-08-06 17:55:18 +00:00
Hyunjun Ko 46e02ee861 intel/genxml: adds a value of reference pic to HCP_SURFACE_STATE 
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27810>
 2024-08-02 07:15:59 +00:00
Hyunjun Ko 7f280e1e93 intel/genxml: fix some length of HCP_FQM_STATE 
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27810>
 2024-08-02 07:15:59 +00:00
Hyunjun Ko 663f9eb740 intel/genxml: Adds more VDENC commands 
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27810>
 2024-08-02 07:15:59 +00:00
Hyunjun Ko 3eb69b9577 intel/genxml: fix the length of VDENC_DS_REF_SURFACE_STATE 
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27810>
 2024-08-02 07:15:59 +00:00
Hyunjun Ko e79cad5af0 intel/genxml: Add missing fields for HCP_SLICE_STATE 
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27810>
 2024-08-02 07:15:59 +00:00
Hyunjun Ko 9425ba6f2b intel/genxml: update VDENC instructions 
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27810>
 2024-08-02 07:15:59 +00:00
Hyunjun Ko b97d440bc5 intel/genxml: change the length of MFX_QM_STATE 
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27810>
 2024-08-02 07:15:58 +00:00
Hyunjun Ko 5057a33fe3 intel/genxml: add a missing value for MFX_SURFACE_STATE 
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27810>
 2024-08-02 07:15:58 +00:00
Paulo Zanoni 6bc9a57173 intel/genxml: add the BLT and COMP_CTX0 versions of the TR-TT registers 
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30252>
 2024-07-22 10:04:33 -07:00
David Heidelberg 68215332a8 build: pass licensing information in SPDX form 
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29972>
 2024-06-29 12:42:49 -07:00
Jianxun Zhang 1c92b31888 intel/genxml,blorp,common: Update 3DSTATE_PS command (xe2) 
From Bspec 56423 (r58507), the legacy full resovling and
partial resolving options are gone since Xe2. They also
cause hang on Xe2 if not disabled.

Some suggested code from Nanley Chery <nanley.g.chery@intel.com> is
included.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
José Roberto de Souza 19a8abde5f anv: Implement Wa_14019857787 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29619>
 2024-06-20 21:47:59 +00:00
Francisco Jerez 8e61d32db8 iris,anv/xe2+: Use pipelined variant of 3DSTATE_DRAWING_RECTANGLE. 
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29562>
 2024-06-17 16:19:17 -07:00
Francisco Jerez 576c9e3af2 iris,anv/xe2+: Set tessellation redistribution regions per patch to recommended values. 
See also HSDES#14015504893 regarding the region-based tessellation
redistribution feature which allows fine-tuning the number of regions
per patch.  This sets it to the recommended value, since region-based
redistribution is enabled by default.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29562>
 2024-06-17 16:19:17 -07:00
Francisco Jerez 2aa4652a68 iris,anv/xe2+: Enable the DX10/OGL border mode for YCrCb as per Wa_14014226147. 
Hardware defaults to DX9 YCrCb border color mode instead of the
behavior expected for DX10/OGL.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29562>
 2024-06-17 16:19:17 -07:00
Lionel Landwerlin 3b88a77b45 genxml: add MI_MEM_FENCE for Gfx20 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29571>
 2024-06-13 11:04:31 +00:00
Marcin Ślusarz 1fa343c38b intel/genxml/xe2: update MESH_CONTROL 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29617>
 2024-06-10 15:21:34 +00:00
Lionel Landwerlin e6efe2e3fe anv: support setting CFE_STATE::StackIDControl per application 
This is a performance tuning value, recommended value is 512 on DG2.
On DG2 this was in the privileged register RT_CTRL.

Minor CFE_STATE defintion fixes from Jose.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29616>
 2024-06-10 14:08:03 +00:00
José Roberto de Souza 62a25f0649 anv/xe2: Add STATE_COMPUTE_MODE individual masks 
So we can enable each mask individually when programming registers.
Also setting Mask2/mask of the second double word so all registers in
it are also zeored during state init.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29616>
 2024-06-10 14:08:03 +00:00
José Roberto de Souza a472d415bc anv/xe2: Enable compute walker and BTD thread preemption 
GFX versions older than GFX 20 have 'Thread Preemption disable' while
GFX 20 has 'Thread Preemption' with value flipped in compute walker
instruction.
So here by default enabling thread preemption, only disabling it
when BTD mode is enabled as instructed in Wa_14017794102.

Similar for 3DSTATE_BTD, enabling preemption by default and
only disabling when platform is affected by Wa_14017794102.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29616>
 2024-06-10 14:08:02 +00:00
José Roberto de Souza 6e03ddd95d intel/genxml/gfx20: Sync POSTSYNC_DATA struct with spec 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29616>
 2024-06-10 14:08:02 +00:00
Rohan Garg 01faec2709 intel/genxml: Add RESOURCE_BARRIER for xe2 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29297>
 2024-06-05 15:22:25 +00:00
Kevin Chuang d07321e3d8 intel/genxml: add task/mesh shader statistics registers 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29523>
 2024-06-04 16:24:48 +00:00
Rohan Garg 6fc6f95e90 intel/genxml: Update STATE_COMPUTE_MODE for Xe2 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Rohan Garg f5a5c35717 intel/genxml: update MI_SEMAPHORE_WAIT for Xe2 
Rework:
 * José: Restore "Register Poll Mode" default to "Memory Poll"
 * José: Other minor formatting changes to match other genxml

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Rohan Garg 569a037fb1 intel/genxml: Update XY_BLOCK_COPY_BLT 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Rohan Garg 26e78f83bb intel/genxml: update CFE_STATE for LNL 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Rohan Garg b9c68883c4 intel/genxml: update 3DSTATE_CPSIZE_CONTROL_BUFFER for xe2+ 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Rohan Garg bd09649750 intel/genxml: add the new state byte stride instruction 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Jordan Justen 17b6db893b intel/genxml: Update 3DSTATE_BTD for xe2 
Reworks:
  - Rohan: 3DSTATE_BTD can also be emitted on the CCS

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Jordan Justen 5709bbe033 intel/genxml: Add XY_FAST_COLOR_BLT for xe2 
Reworks:
  - Rohan: Use a uint for the surface format since we're dropping the
    SURFACE_FORMAT enum from genxml

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
José Roberto de Souza a47a65c1c2 intel/genxml/xe2: Update definition of INTERFACE_DESCRIPTOR_DATA 
This maches specification and better matches the gfx 125 definition.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28505>
 2024-04-03 20:21:04 +00:00
José Roberto de Souza 0f29b780e1 intel/genxml/gfx125: Fix definition of INTERFACE_DESCRIPTOR_DATA::Thread group dispatch size 
It was using the wrong platform definition that only had 1 bit,
filtering by DG2/ACM it shows the correct definition.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28505>
 2024-04-03 20:21:04 +00:00
José Roberto de Souza c00c685f84 intel/genxml: Add more instdone registers 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28505>
 2024-04-03 20:21:04 +00:00
José Roberto de Souza 2f3dc31876 anv: Set STATE_COMPUTE_MODE mask bit when zeroing compute mode 
Justing setting all zeroes to STATE_COMPUTE_MODE will do nothing,
the mask of each register must be set for it to change.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28505>
 2024-04-03 20:21:04 +00:00
David Heidelberg d8f53f698c util: move gen_zipped_file into generic util and rename to gen_zipped_xml_file 
Make the filename more descriptive and since the file is used by
multiple drivers, move it into appropriate util/ directory.

Cosmetics:
 - use SPDX license tag
 - add newline before main function

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27804>
 2024-03-21 20:48:41 +00:00
Paulo Zanoni 18df1a81a8 anv/trtt: update GFX_TRTT_VA_RANGE for LNL 
This register has changed a little bit for LNL.

While this fixes sparse with TR-TT, it is worth remembering that LNL
is using sparse with vm_bind by default.

v2: Use the proper value instead of hardcoding 0xF (Lionel).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27316>
 2024-03-13 01:50:35 +00:00
Rohan Garg 9baa57158d intel/genxml: update PIPE_CONTROL so that we can decode it on the CCS 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28013>
 2024-03-06 14:37:11 +00:00
Lionel Landwerlin 19aeb274e6 genxml: generate opencl temporary variables with private qualifier 
To avoid generic pointers, makes the NIR prints a bit more readable.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Fixes: 41b2ed65 ("genxml: generate opencl packing headers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27637>
 2024-02-20 14:41:43 +00:00
Lionel Landwerlin 76c3d97c84 intel/shaders: add iris variant of indirect draws generation shader 
Iris does not use Gfx11+ SGVS extended parameters, so we have to rely
on the old Gfx9 method of providing the parameters through vertex
buffers.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00
Lionel Landwerlin b52e25d3a8 anv: rewrite internal shaders using OpenCL 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
 2024-02-13 00:06:45 +00:00