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Author SHA1 Message Date
Nicolai Hähnle b8d3fd46d6 radeonsi/gfx10: set user data base registers 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 016a465d7d radeonsi/gfx10: implement gfx10_shader_ngg 
For pipelines without API GS. We will later expand this to cover NGG
geometry shaders as well.

Note that the vtx offset passed into the GS part is just the
vertex index multiplied by VGT_ESGS_RING_ITEMSIZE.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle d0c204a1e0 radeonsi/gfx10: add NGG registers to si_init_config 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle ae00cae0b7 radeonsi/gfx10: update shader-related fields in si_init_config 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 1dee01ee13 radeonsi/gfx10: implement si_shader_ps 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 612489bd5d radeonsi/gfx10: generate VS and TES as NGG merged ESGS shaders 
This does not support geometry shading yet. Also missing are streamout
and NGG-specific optimizations.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle e86256c512 radeonsi/gfx10: distinguish between merged shaders and multi-part shaders 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 4063ea95e9 radeonsi/gfx10: update si_get_shader_name 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 8ec60d3031 radeonsi/gfx10: add as_ngg shader key bit 
Also add the shader main part NGG variant, so that in principle
we can switch between legacy in NGG modes.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 40b12c0f5a radeonsi/gfx10: implement si_update_shaders 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 5726ec0d24 radeonsi/gfx10: implement si_build_vgt_shader_config 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle b45c3debe8 radeonsi/gfx10: keep track of whether NGG is used 
We always use NGG by default, except when tessellation is enabled with
extreme geometry shader amplification.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 226f650d92 radeonsi/gfx10: document NGG shader stages 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 7bb9bb0540 radeonsi/gfx10: implement gfx10_emit_cache_flush 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 0c6c6810bd radeonsi/gfx10: add si_context::emit_cache_flush 
The introduction of GCR_CNTL makes cache flush handling on gfx10
sufficiently different that it makes sense to just use a separate
function.

Since emit_cache_flush is called quite early during context init,
we initialize the pointer explicitly in si_create_context.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 08e2a62b07 radeonsi/gfx10: implement DB registers 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 372652bccc radeonsi/gfx10: set CB registers 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 44adae42ae radeonsi/gfx10: always set up sample locations 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 79b1eaf2fd radeonsi/gfx10: use Z32_FLOAT_CLAMP for upgraded depth textures 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle c049a6f895 radeonsi/gfx10: implement vertex format changes 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 62f73d8214 radeonsi/gfx10: implement si_set_{constant,shader}_buffer 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 21ac1da0d1 radeonsi/gfx10: implement si_make_buffer_descriptor 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 7bc818aef1 radeonsi/gfx10: implement si_set_mutable_tex_desc_fields 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 8598a999ea radeonsi/gfx10: gfx10 can render up to 8192 layers 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 3f2b2b52d0 radeonsi/gfx10: add gfx10_make_texture_descriptor 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 595a7f7c47 radeonsi/gfx10: add pipe_screen::make_texture_descriptor 
Texture descriptors in gfx10 are very different.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 4afce5efdd radeonsi/gfx10: determine view->is_integer based on the pipe_format 
It was convenient, but NUM_FORMAT no longer exists in gfx10.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 3163db3ba4 radeonsi/gfx10: implement si_is_format_supported 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 0ffa2292b3 radeonsi/gfx10: generate gfx10_format_table.h 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle af29ad7cc6 radeonsi/gfx10: set MAX_ALLOC_COUNT 
The number for Vega was copied from PAL and has no effect because of MIN2.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 594010e366 radeonsi/gfx10: require LLVM 9 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang de99e0a563 radeon/vcn: update for new vcn enc interface 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang 9ab1e427bb radeonsi: enable jpeg decode for navi10 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang 6480c7b577 radeon/vcn: implement vcn 2.0 jpeg decode 
Use direct register to implement vcn 2.0 jpeg deocde

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang 0cd7953ece radeon/vcn: add direct register bool 
VCN 2.0 uses direct register space where VCN 1.0 uses some indirect registers

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang 7a5c22d32a radeon/vcn: add defines for vcn 2.0 jpeg 
Add neccesary register defines for vcn 2.0 jpeg deocde

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang 0c27971157 radeon/vcn: use variable to assign ib cmd 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang 587b9c5dae radeon/vcn: implement vcn 2.0 encode 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang 40e1bed389 radeon/vcn: add vcn2.0 encode skeleton 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
(v2: build fix -- Nicolai)
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang 8f6272d494 radeon/vcn: move vcn1.0 specific defines to c 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang b5287a9fa6 radeon/vcn: assign function pointer with ib functions 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang 9940a6e066 radeon/vcn: add function pointer for ib functions 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang c6b5188505 radeon/vcn: move header related algorithm to vcn_enc 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang dd46740bc2 radeon/vcn: move add buf func to common file 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang e6ca4d1bd8 radeon/vcn: move cs defines to enc header file 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Leo Liu 874881b26b radeon/vcn: add VP9 support for Navi10 
It requires bigger DPB and context buffers

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Leo Liu 9bbb546c4f radeonsi: enable encode support for newer HW 
Previously it was Raven only allowed to do so

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Leo Liu d6acd29c9a radeon/vcn: add VCN2 set of internal registers for IB 
From VCN2.0, the RBC have different views on the registers

Signed-off-by: Leo Liu <leo.liu@amd.com>
(v2: rebase -- Nicolai)
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Leo Liu a38268ea5b radeonsi/uvd: allow newer HW to create HW decoder 
Previously it was Raven only allowed to do so

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 84e7ee421f ac/surface/gfx10: allow "rotated" micro mode 
Standard mode does not support DCC.

The R is retconned to "render target" on gfx10.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00