b005fd62f9
nir/spirv: Add GLSL.std.450.h
...
It accidentally got removed during the mass rename.
2015-12-28 15:46:22 -08:00
9c84b6cce0
anv/device: Set device->info sooner in CreateDevice
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anv_block_pool_init calls anv_block_pool_grow which checks
device->info.has_llc to see if it needs to set caching parameters.
If we don't set device->info early enough, this reads an undefined value
which is probably 0 and not what we want on llc platforms.
Found with valgrind.
2015-12-28 13:29:01 -08:00
763176a3e2
nir/lower_returns: Fix a bug in loop lowering
2015-12-28 13:22:09 -08:00
381a89cf2a
i965: Enable ARB_tessellation_shader on Gen7-7.5.
...
We've resolved all the GPU hangs, and everything seems to be working.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org >
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
2015-12-28 13:17:05 -08:00
bd8ab8dedb
i965: Don't set interleave or complete on TCS EOT message.
...
Setting interleave on the TCS EOT message causes Ivybridge hardware to
GPU hang like crazy. Individual tests would pass, but running even a
simple test like nop.shader_test in a loop would hang within 1-3 runs.
Adding sleep delays worked around the problem, somehow.
Interleave doesn't make much sense given that we only have one patch
URB handle, not two. Complete doesn't seem useful either.
There's no reason to actually set those bits. We were just being lazy.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org >
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
2015-12-28 13:17:03 -08:00
b7793783b3
i965: Relase input URB Handles on Gen7/7.5 when TCS threads finish.
...
Pre-Broadwell hardware requires us to manually release the ICP Handles
by issuing URB read messages with the "Complete" bit set. We can do
this in pairs to use fewer URB read messages.
Based heavily on work from Chris Forbes.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org >
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
2015-12-28 13:17:00 -08:00
6ceabb72ea
i965: Use proper TCS barrier ID bits for Ivybridge/Baytrail.
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Gen7 uses bits 15:12 while Gen7+ uses bits 16:13.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org >
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
2015-12-28 13:16:57 -08:00
5898cbae24
i965: Use proper TCS Instance ID bits for Ivybridge/Baytrail.
...
Gen7 uses 22:16 while Gen7.5+ uses 23:17.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org >
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
2015-12-28 13:16:54 -08:00
1245724f72
i965: Port tessellation evaluation shaders to vec4 mode.
...
This can be used on Broadwell by setting INTEL_SCALAR_TES=0.
More importantly, it will be used for Ivybridge and Haswell.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org >
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
2015-12-28 13:16:48 -08:00
889d987904
i965: Emit a real 3DSTATE_DS on Gen7.
...
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org >
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
2015-12-28 13:16:45 -08:00
2c240b05e9
i965: Emit a real 3DSTATE_HS on Gen7.
...
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org >
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
2015-12-28 13:16:34 -08:00
74b83fe368
i965: Add the TCS/TES state upload atoms to the gen7_atoms list.
...
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org >
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
2015-12-28 13:16:19 -08:00
7aaed91581
nir/spirv: Move to its own directory
2015-12-28 11:49:39 -08:00
d5fa51bdee
Merge remote-tracking branch 'mesa-public/master' into vulkan
...
This pulls in the removal of nir_function_overload
2015-12-28 10:56:31 -08:00
d9dcfafacc
nir/spirv: Use nir_build_alu for alu instructions
2015-12-28 10:35:31 -08:00
237f2f2d8b
nir: Get rid of function overloads
...
When Connor originally drafted NIR, he copied the same function+overload
system that GLSL IR had with a few names changed. However, this
double-indirection is not really needed and has only served to confuse
people. Instead, let's just have functions which may not have unique names
and may or may not have an implementation. If someone wants to do overload
resolving, they can hav a hash table based function+overload system in the
overload resolving pass. There's no good reason to keep it in core NIR.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com >
Acked-by: Kenneth Graunke <kenneth@whitecape.org >
ir3 bits are
Reviewed-by: Rob Clark <robclark@gmail.com >
2015-12-28 09:59:53 -08:00
ea77b384e8
Merge remote-tracking branch 'mesa-public/master' into vulkan
...
This pulls in tessellation and the store_var changes that go with it.
2015-12-27 23:23:05 -08:00
f948767471
nir/lower_returns: Better algorithm as per connor
2015-12-27 22:50:45 -08:00
3489f66056
nir: Add a cursor helper for getting a cursor after any phi nodes
2015-12-27 22:50:14 -08:00
109c348284
nvc0: don't forget to reset VTX_TMP bufctx slot after blit completion
...
Also release the scratch allocation if any.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu >
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org >
2015-12-27 21:33:36 -05:00
28e07fdd4a
nv50,nvc0: add a note when converting vertex elements using CPU
...
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu >
2015-12-27 19:49:44 -05:00
c60456dfaa
nir/gather_info: Handle multi-slot variables in io bitfields
2015-12-24 00:47:20 -08:00
bbebd2de13
nir: Add a helper for getting the bitmask for a variable's location
2015-12-24 00:47:20 -08:00
4ff4310a78
nir/types: Expose glsl_type::count_attribute_slots()
2015-12-24 00:47:19 -08:00
0bc1b0fd23
nir/lower_return: Do it for real this time
2015-12-24 00:47:19 -08:00
e1b1d58bec
nir/cf: Make extracting or re-inserting nothing a no-op
2015-12-23 23:46:04 -08:00
eae352e75c
nir: Add a function for comparing cursors
2015-12-23 18:09:42 -08:00
41c7912d04
gallium/auxiliary: don't build NIR sources with MSVC2008 flags
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NIR has never been built with MSVC2008, so we shouldn't add
MSVC2008_COMPAT_CFLAGS to anything that uses it. This allows us to get
rid of the pragma in tgsi_to_nir.c.
Build tested with freedreno.
v2: Use MSVC2013_COMPAT_CLFAGS instead.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com >
Signed-off-by: Connor Abbott <cwabbott0@gmail.com >
2015-12-23 20:46:48 -05:00
54c870ff61
nir/spirv: Add support for undefs in vtn_ssa_value()
2015-12-23 14:14:39 -08:00
2e823d5754
nir/spirv: Properly handle vector times matrix
2015-12-23 13:49:56 -08:00
452ba4db2b
nir/spirv: Create the correct type if a matrix-vector multiply produces a vector
2015-12-23 13:49:56 -08:00
5b30132388
nir/spirv: Fix some mem_ctx issues with create_vec
2015-12-23 13:49:56 -08:00
66168a798b
nir/spirv: Better document vtn_ssa_value.transposed
2015-12-23 13:49:56 -08:00
3b391892aa
anv/descriptor_set: Use anv_foreach_stage
2015-12-23 13:49:56 -08:00
72ceb99bab
anv: Mask out invalid stages in foreach_stage
2015-12-23 13:49:56 -08:00
5644b1cece
nir/spirv: Handle LogicalNot
2015-12-23 13:49:56 -08:00
6219a69589
nir/spirv: Handle derefs in vtn_ssa_value
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This is kind of a hack, but it makes vtn_ssa_value insert a load if the
value requested is actually a deref. This shouldn't happen normally but,
thanks to the impedence mismatch of the NIR function parameter model vs.
the SPIR-V model, this can happen for function arguments.
2015-12-23 13:49:56 -08:00
3ab1b7afa8
nir/spirv: Do boolean fixup on block loads
...
We used to do it for variable loads on things of type "uniform" but that
never got ported to block loads.
2015-12-23 13:49:56 -08:00
af74ce5a19
spirv/nir: Handle non-vector extractions in vtn_composite_extract
2015-12-23 13:49:56 -08:00
79b8b42081
nir/spirv: Handle function calls
2015-12-23 13:49:56 -08:00
95990c96cc
nir: Create the params array in function_impl_create
2015-12-23 13:49:56 -08:00
a7f3e113ad
i965/nir: Remove return handling
...
This was added because we were getting spurrious returns coming out of
SPIR-V. Now that we're calling lower_returns, we don't need this.
2015-12-23 13:49:56 -08:00
ac975b73cf
anv/pipeline: Run lower_returns and inline_functions after spirv_to_nir
2015-12-23 13:49:56 -08:00
8fba4bf79f
nir: Add a function inlining pass
2015-12-23 13:49:56 -08:00
b21db9cea5
nir/builder: Add a copy_deref_var helper
2015-12-23 13:49:56 -08:00
23cfa683d5
nir: move nir_copy_var from anv_nir_builder to nir_builder
2015-12-23 13:49:56 -08:00
4aac03fe61
nir/clone: Add support for cloning a single function_impl
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This will be useful for things such as function inlining.
2015-12-23 13:49:56 -08:00
98291b8f2c
nir: Add a helper for creating a "bare" nir_function_impl
...
This is useful if you want to clone a single function_impl if, for
instance, you wanted to do function inlining.
2015-12-23 13:49:56 -08:00
86772c2488
nir/control_flow: Handle relinking top-level blocks
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This can happen if a function ends in a return instruction and you remove
the return.
2015-12-23 13:49:56 -08:00
1749e667ea
nir: Add a stub function inlining pass
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All it does is remove the return at the end, but it's good enough for
simple functions.
2015-12-23 13:49:56 -08:00
Jason Ekstrand