Commit Graph

74545 Commits

Author SHA1 Message Date
Nicolai Hähnle
f7a85a8a0a radeonsi: Lower TGSI_OPCODE_ATOM* down to LLVM op
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-21 15:34:24 -05:00
Nicolai Hähnle
bfcefcb3c7 radeonsi: Lower TGSI_OPCODE_STORE down to LLVM op
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-21 15:34:24 -05:00
Nicolai Hähnle
1e82dedeca radeonsi: Lower TGSI_OPCODE_LOAD down to LLVM op (v3)
v2: new signature style for buffer intrinsics (offsets)
v3: new signature style for llvm.amdgcn.buffer.load.format (overloaded return)

Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
2016-03-21 15:34:24 -05:00
Nicolai Hähnle
136686a51d radeonsi: extract the LLVM type name construction into its own function
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-21 15:34:23 -05:00
Nicolai Hähnle
02bd0cd7b1 radeonsi: Lower TGSI_OPCODE_RESQ down to LLVM op
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-21 15:34:23 -05:00
Nicolai Hähnle
75539197c7 radeonsi: extract TXQ buffer size computation into its own function
This will allow it to be reused for RESQ.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-21 15:34:23 -05:00
Nicolai Hähnle
515fb2c09c radeonsi: decompress shader images
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-21 15:34:23 -05:00
Nicolai Hähnle
f61566b77a radeonsi: update shader image descriptor for invalidated buffer
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-21 15:34:23 -05:00
Nicolai Hähnle
e85cf35a65 radeonsi: implement set_shader_images (v2)
Whether DCC is disabled depends on the access flags with which the image
is bound: image_load supports DCC, but store and atomic don't.

v2: remove an unnecessary masking of images->desc.enabled_mask

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-21 15:34:23 -05:00
Nicolai Hähnle
b1b7268f01 gallium/radeon: make r600_texture_disable_dcc externally accessible
We will need it in radeonsi for shader images.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-21 15:34:22 -05:00
Nicolai Hähnle
457f9c6b25 tgsi/scan: track which shader images are really buffers
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-21 15:34:22 -05:00
Nicolai Hähnle
fa096a14af tgsi/scan: add images_writemask
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-21 15:34:22 -05:00
Nicolai Hähnle
1379544081 st/mesa: translate additional flags in MemoryBarrier
Re-order flags in the order in which they appear in the OpenGL spec in the
description of MemoryBarrier().

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-21 15:34:22 -05:00
Nicolai Hähnle
96cd908fd3 gallium: add additional PIPE_BARRIER_* bits
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-21 15:34:22 -05:00
Brian Paul
86caa67aef svga: add svga_winsys_context::pipe_debug_callback pointer
The svga winsys modules can use this to send debug messages to the
state tracker and Mesa.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2016-03-21 13:37:40 -06:00
Charmaine Lee
f8aaf0094d svga: Fix the index buffer rebind regression
The index buffer handle saved in the hw_state structure could
be invalid after the index buffer is destroyed. Instead of
rebinding the index buffer using the saved index buffer handle,
we will reset the index buffer handle in the hw_state structure
to force resending of the index buffer.

Fixes bug 1593320

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-03-21 13:37:40 -06:00
Charmaine Lee
47856e5945 svga: rebind stream output targets
To ensure stream output target surfaces are available for the draw commands,
we need to rebind the current stream output targets at the first draw in the
command buffer.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-03-21 13:37:40 -06:00
Charmaine Lee
47cfc83440 svga: rebind index buffer
Similar to other resources, current index buffer needs to be
rebound at the first draw of the current command buffer to make
sure the buffer is available for the draw command.

Fixes bug 1587263.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-03-21 13:37:40 -06:00
Brian Paul
299f8ca0a7 svga: minor formatting fix, comment addition
To sync with our internal tree.

Signed-off-by: Brian Paul <brianp@vmware.com>
2016-03-21 13:37:25 -06:00
Charmaine Lee
b45b47c5c9 svga: optimize constant buffer uploads
When a constant buffer slot is allocated in the upload buffer,
the allocated slot size is always in multiple of 256. But the actual buffer
size might not be in multiple of 256. This causes a gap between
the ending offset of a slot and the starting offset of the next slot.
The gap will prevent the two slots to be updated in a single update command.
In order to maximize the chance of merging the contiguous dirty ranges,
when a slot is to be allocated in the constant upload buffer,
specify a buffer size in multiple of 256.

There is about 10% performance improvement with Lightsmark2008 and
30% with Cinebench R11.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
2016-03-21 12:58:25 -06:00
Charmaine Lee
0a1d91ef97 svga: add a few more resource updates HUD query
This patch adds the following HUD queries:
.num-resource-updates  -- number of resource update. Commands include
                          UPDATE_SUBRESOURCE, UPDATE_GB_IMAGE.
.num-buffer-uploads    -- number of buffer uploads.
.num-const-buf-updates -- number of set constant buffer.
.num-const-updates     -- number of set shader constant.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
2016-03-21 12:58:25 -06:00
Charmaine Lee
79e343b36a svga: add new num-readbacks HUD query
To find out how many image readback command is issued.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
2016-03-21 12:58:25 -06:00
Brian Paul
dc9ecf58c0 svga: use shader sampler view declarations
Previously, we looked at the bound textures (via the pipe_sampler_views)
to determine texture dimensions (1D/2D/3D/etc) and datatype (float vs.
int).  But this could fail in out of memory conditions.  If we failed to
allocate a texture and didn't create a pipe_sampler_view, we'd default
to using 0 (PIPE_BUFFER) as the texture type.  This led to device errors
because of inconsistent shader code.

This change relies on all TGSI shaders having an SVIEW declaration for
each SAMP declaration.  The previous patch series does that.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-03-21 11:59:25 -06:00
Brian Paul
b56b853ab3 gallium/tests: declare sampler views in shaders
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-03-21 11:59:25 -06:00
Brian Paul
38e831ca3d gallium/util: declare sampler view in util_make_fs_blit_msaa_depthstencil()
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-03-21 11:59:25 -06:00
Brian Paul
e7b5a844e3 postprocess: declare sampler views in shaders
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-03-21 11:59:25 -06:00
Brian Paul
5a9f2a2d89 hud: add sampler view declaration in text fragment shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-03-21 11:59:25 -06:00
Brian Paul
b3daaefadb st/mesa: emit sampler view decls in drawpixels code
v2: support both TGSI_TEXTURE_2D and _RECT

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-03-21 11:59:25 -06:00
Brian Paul
0f0a23d4d8 st/mesa: emit sampler view declaration in bitmap shader
In June 2015, Rob Clark started updating the tgsi utility code to emit
SVIEW declarations in various shaders (for polygon stipple, blitting,
etc).  These patches do the same for the Mesa state tracker.

The VMware driver will use this.

v2: support both TGSI_TEXTURE_2D and _RECT

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-03-21 11:59:25 -06:00
Brian Paul
72eb5a3cfe st/mesa: emit sampler view declarations for ARB vert/frag programs
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-03-21 11:59:25 -06:00
Brian Paul
eda81fa357 st/mesa: use correct TGSI texture target in drawpix fragment shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-03-21 11:59:25 -06:00
Brian Paul
83b5b3d66e st/mesa: use correct TGSI texture target in bitmap fragment shader
Depending on the driver's support for NPOT textures, we might use
a RECT texture instead of 2D texture.  We should propogate that info
to the fragment shader's TEX instruction.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-03-21 11:59:25 -06:00
Brian Paul
63e020d734 gallium/tgsi: pass TGSI tex target to tgsi_transform_tex_inst()
Instead of hard-coded 2D tex target in tgsi_transform_tex_2d_inst()

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-03-21 11:59:25 -06:00
Nicolai Hähnle
a8b315b827 st/mesa: use the texture view's format for render-to-texture
Aside from the bug below, it fixes a simplistic test I've written locally,
and I see no regression in Piglit for radeonsi.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94595
Cc: "11.0 11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-21 11:28:38 -05:00
Hans de Goede
dcf8a4d281 gallium: Remove unused TGSI_RESOURCE_ defines
These magic file-index defines where only ever used in the nouveau code
and that no longer uses them.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (v2)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
2016-03-21 12:20:58 +01:00
Hans de Goede
9b4c8f6629 nouveau: codegen: Do not silently fail in handeLOAD / handleSTORE / handleATOM
handeLOAD / handleSTORE / handleATOM can only handle TGSI_FILE_BUFFER
and TGSI_FILE_MEMORY. Make things fail explictly when another
register-file is used in these functions.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (v2)
2016-03-21 12:20:48 +01:00
Hans de Goede
86e4440361 nouveau: codegen: Disable more old resource handling code
Commit c3083c7082 ("nv50/ir: add support for BUFFER accesses") disabled /
commented out some of the old resource handling code, but not all of it.

Effectively all of it is dead already, if we ever enter the old code
paths in handeLOAD / handleSTORE / handleATOM we will get an exception
due to trying to access the now always zero-sized resources vector.

Disable all the dead code.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (v2)
2016-03-21 12:20:40 +01:00
Hans de Goede
71e315475c nouveau: codegen: gk110: Make emitSTORE offset handling identical to emitLOAD
Make the store offset handling in CodeEmitterGK110::emitSTORE identical
to the one in CodeEmitterGK110::emitLOAD handling.

This is just a cleanup, it does not cause any functional changes.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-03-21 12:20:38 +01:00
Hans de Goede
c783ad0e24 nouveau: codegen: Slightly refactor Source::scanInstruction() dst handling
Use the dst temp variable which was used in the TGSI_FILE_OUTPUT
case everywhere. This makes the code somewhat easier to reads
and helps avoiding going over 80 chars with upcoming changes.

This also brings the dst handling more in line with the src
handling.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-03-21 12:20:32 +01:00
Hans de Goede
54cdde5eff nouveau: codegen: Add support for clover / OpenCL kernel input parameters
Add support for clover / OpenCL kernel input parameters.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> (v1)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (v2)
2016-03-21 12:20:28 +01:00
Hans de Goede
3788e1bf74 tgsi: Add support for global / private / input MEMORY
Extend the MEMORY file support to differentiate between global, private
and shared memory, as well as "input" memory.

"MEMORY[x], INPUT" is intended to access OpenCL kernel parameters, a
special memory type is added for this, since the actual storage of these
(e.g. UBO-s) may differ per implementation. The uploading of kernel
parameters is handled by launch_grid, "MEMORY[x], INPUT" allows drivers
to use an access mechanism for parameter reads which matches with the
upload method.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> (v1)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (v2)
2016-03-21 12:20:24 +01:00
Hans de Goede
43ddec2f43 tgsi: Fix decl.Atomic and .Shared not propagating when parsing tgsi text
When support for decl.Atomic and .Shared was added, tgsi_build_declaration
was not updated to propagate these properly.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> (v1)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (v2)
2016-03-21 12:20:19 +01:00
Hans de Goede
b72156c8e0 tgsi: Fix return of uninitialized memory in tgsi_*_instruction_memory
tgsi_default_instruction_memory / tgsi_build_instruction_memory were
returning uninitialized memory for tgsi_instruction_memory.Texture and
tgsi_instruction_memory.Format. Note 0 means not set, and thus is a
correct default initializer for these.

Fixes: 3243b6fc97 ("tgsi: add Texture and Format to tgsi_instruction_memory")
Cc: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-03-20 18:01:53 -04:00
Ilia Mirkin
bbbdcdcf75 st/mesa: report correct precision information for low/medium/high ints
When we have native integers, these have full precision. Whether they're
low/medium/high isn't piped through the TGSI yet, but eventually those
might have differing precisions. For now they're just 32-bit ints.

Fixes the following dEQP tests:

  dEQP-GLES3.functional.state_query.shader.precision_vertex_highp_int
  dEQP-GLES3.functional.state_query.shader.precision_fragment_highp_int

which expected highp ints to have full 32-bit precision, not the default
23-bit float precision.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-03-20 17:51:08 -04:00
Nishanth Peethambaran
eeb117a09d st/omx/dec: Correct the timestamping
Attach the timestamp to the dpb buffer and use that timestamp
while pushing buffer from dpb list to the omx client.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Nishanth Peethambaran <nishanth.peethambaran@amd.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-03-20 15:01:28 -04:00
Nishanth Peethambaran
46de6bbb77 st/omx: Remove trailing spaces
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Nishanth Peethambaran <nishanth.peethambaran@amd.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-03-20 15:01:28 -04:00
Ilia Mirkin
7d98bfedd7 nv50/ir: fix indirect texturing for non-array textures on nvc0
If a layer parameter is provided, we want to flip it to position 0 (and
combine it with any indirect params). However if the target is not an
array, there is no layer, so we have to shift all of the arguments down
by one to make room for it.

This fixes situations where there were non-coordinate parameters, such
as bias, lod, depth compare, explicit derivatives. Instead of adding a
new parameter at the front for the indirect reference, we would swap one
of those in its place.

Fixes dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.uniform.compute.*shadow

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reported-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-03-20 14:14:32 -04:00
Ilia Mirkin
adb40a7399 st/mesa: only minify depth for 3d targets
We make sure that that image depth matches the level's depth before
copying it into place. However we should only be minifying the first
level's depth for 3d textures - array textures have the same depth for
all levels.

This fixes tests such as
dEQP-GLES3.functional.texture.specification.texsubimage3d_depth.* and I
suspect account for a number of other odd situations I've run into where
level > 0 of array textures was messed up.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-03-20 14:14:32 -04:00
Ilia Mirkin
6eeb284e4f nv50/ir: normalize cube coordinates after derivatives have been computed
In "manual" derivative mode (always used on nv50 and sometimes on nvc0
but always for cube), the idea is that using the quadop instruction, we
set up the "other" quads to have values such that the derivatives work
out, and then run the texture instruction as if nothing were strange. It
pulls values from the other lanes, and does its magic.

However cube coordinates have to be normalized - one of the 3 coords has
to be 1, to determine which is the major axis, to say which face is
being sampled. We were normalizing the coordinates first, and then
adding the derivatives. This is wrong for two reasons:

- the coordinates got normalized by a scaling factor but the
  derivatives didn't
- the result of the addition didn't end up normalized

To resolve this, we flip the logic around to normalize *after* the
per-lane coordinates are set up.

This fixes a bunch of textureGrad cube dEQP tests.

NOTE: nv50 cube arrays with explicit derivatives are still broken, to be
resolved at a later date.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-03-20 14:14:32 -04:00
Marek Olšák
ea2bff1d11 gallium/radeon: remove remnants of R600 TGSI->LLVM
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-03-20 00:57:05 +01:00