eb6764c4a7
anv: Add proper support for depth clamping
...
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Cc: "12.0" <mesa-stable@lists.freedesktop.org >
2016-06-20 12:04:08 -07:00
8a46b505cb
anv/cmd_buffer: Split emit_viewport in two
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Signed-off-by: Jason Ekstrand <jason@jlekstrand.net >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Cc: "12.0" <mesa-stable@lists.freedesktop.org >
2016-06-20 12:03:09 -07:00
87d062a940
i965: Fix shared local memory size for Gen9+.
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Skylake changes the representation of shared local memory size:
Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
-------------------------------------------------------------------
Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
-------------------------------------------------------------------
Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
The old formula would substantially underallocate the amount of space.
This fixes GPU hangs on Skylake when running with full thread counts.
v2: Fix the Vulkan driver too, use a helper function, and fix the table
in the comments and commit message.
Cc: "12.0" <mesa-stable@lists.freedesktop.org >
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org >
Reviewed-by: Francisco Jerez <currojerez@riseup.net >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
2016-06-12 00:38:26 -07:00
3ba9594f32
anv: Support new local ID generation & cross-thread constants
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The cross thread constant support appears on Haswell. It allows us to
upload a set of uniform data for all threads without duplicating it
per thread.
We also support per-thread data which allows us to store a per-thread
ID in one of the uniforms that can be used to calculate the
gl_LocalInvocationIndex and gl_LocalInvocationID variables.
v4:
* Support the old local ID push constant layout as well (Jason)
Cc: "12.0" <mesa-stable@lists.freedesktop.org >
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
2016-06-01 19:29:02 -07:00
1b79e7ebbd
i965: Store number of threads in brw_cs_prog_data
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Cc: "12.0" <mesa-stable@lists.freedesktop.org >
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
2016-06-01 19:29:02 -07:00
3a83c176ea
anv/cmd_buffer: Only emit PIPE_CONTROL on-demand
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This is in contrast to emitting it directly in vkCmdPipelineBarrier. This
has a couple of advantages. First, it means that no matter how many
vkCmdPipelineBarrier calls the application strings together it gets one or
two PIPE_CONTROLs. Second, it allow us to better track when we need to do
stalls because we can flag when a flush has happened and we need a stall.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
2016-05-27 15:18:09 -07:00
1ff212bfd3
anv: Fix warning: unused variable ‘cs_prog_data’
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This was introduced in 8a80af2820jason@jlekstrand.net >
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
2016-05-17 14:09:56 -07:00
8a80af2820
anv: Port L3 cache programming from i965
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Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Acked-by: Jason Ekstrand <jason@jlekstrand.net >
2016-05-17 13:04:03 -07:00
d14778656b
anv: fix warnings in release build
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Mark variables MAYBE_UNUSED to avoid unused-but-set-variable warnings
in release build.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com >
Reviewed-by: Chad Versace <chad.versace@intel.com >
Reviewed-by: Emil Velikov <emil.velikov@collabora.com >
2016-04-25 12:23:31 +02:00
50018522d2
anv: s/anv_batch_emit_blk/anv_batch_emit/
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Acked-by: Kristian Høgsberg <krh@bitplanet.net >
2016-04-20 14:54:09 -07:00
a48f8340d9
anv/gen8_cmd_buffer: Use the new emit macro
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Acked-by: Kristian Høgsberg <krh@bitplanet.net >
2016-04-20 14:54:09 -07:00
79fbec30fc
anv: Remove default scissor and viewport concepts
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Users should never provide a scissor or viewport count of 0 because
they are required to set such state in a graphics pipeline. This
behavior was previously only used in Meta, which actually just
disables those hardware operations at pipeline creation time.
Kristian noticed that the current assignment of viewport count
reduces the number of viewport uploads, so it is not removed.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com >
Reviewed-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com >
2016-04-13 18:02:38 -07:00
f60683b32a
anv: Invalidate state cache before L3 partitioning set-up.
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Port 10d84ba9f0jordan.l.justen@intel.com >
2016-03-28 17:01:35 -07:00
5879cb0251
anv: Fix cache pollution race during L3 partitioning set-up.
...
Port 0aa4f99f56jordan.l.justen@intel.com >
2016-03-28 17:01:35 -07:00
8f3c236674
anv: Use genxml register support for L3 Cache config
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The programming of the L3 Cache registers should match the previous
manually packed LRI values.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
2016-03-25 00:19:18 -07:00
1b126305de
anv/genX: Add flush_pipeline_select_gpgpu
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Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
2016-03-12 12:43:46 -08:00
248ab61740
anv/cmd_buffer: Pull the core of flush_state into genX_cmd_buffer
2016-03-08 17:10:05 -08:00
28cbc45b3c
anv/cmd_buffer: Split flush_state into two functions
2016-03-08 16:54:07 -08:00
2b29342fae
anv: Store prog data in pipeline cache stream
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We have to keep it there for the cache to work, so let's not have an
extra copy in struct anv_pipeline too.
2016-03-05 13:50:07 -08:00
81f30e2f50
anv/hsw: Move query code to genX file for Haswell
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This fixes many CTS cases, but will require an update to the kernel
command parser register whitelist. (The CS GPRs and TIMESTAMP
registers need to be whitelisted.)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
2016-03-05 01:08:07 -08:00
d154a5ebd6
anv/cmd_buffer: Let the pipeline set StencilBufferWriteEnable on gen9
2016-03-04 12:23:01 -08:00
f374765ce6
anv/cmd_buffer: Mask stencil reference values
2016-03-04 12:22:32 -08:00
ec18fef88d
anv/pipeline: Set StencilBufferWriteEnable from the pipeline
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The hardware docs say that StencilBufferWriteEnable should only be set if
StencilTestEnable is set. It seems reasonable to set them together.
2016-03-04 12:03:00 -08:00
fa8539dd6b
anv/pipeline: Respect pRasterizationState->depthBiasEnable
2016-03-04 12:03:00 -08:00
8f5a64e44f
gen8/cmd_buffer: Properly return flushed push constant stages
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This is required on SKL so that we can properly re-emit binding table
pointers commands.
2016-03-02 10:48:40 -08:00
6e20c1e058
anv/cmd_buffer: Look at both sides for stencil enable
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Now it's all consistent with gen9
2016-03-01 11:03:29 -08:00
bb08d86efe
anv/cmd_buffer: Clean up stencil state setup on gen8
2016-03-01 10:58:43 -08:00
097564bb8e
anv/cmd_buffer: Dirty push constants when changing pipelines.
2016-02-29 14:36:24 -08:00
d29fd1c7cb
anv/cmd_buffer: Re-emit push constants packets for all stages
2016-02-29 14:36:24 -08:00
371b4a5b33
anv: Switch over to the macros in genxml
2016-02-20 09:09:28 -08:00
9851c8285f
Move the intel vulkan driver to src/intel/vulkan
2016-02-18 10:37:59 -08:00
Jason Ekstrand