a3f67c2d3a
intel/elk: Remove FB_READ opcodes
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629 >
2024-03-07 15:53:18 +00:00
77ba6f5dcd
intel/elk: Remove Gfx9+ dataport messages
...
Note GFX9_DATAPORT_DC_PORT1_A64_SCATTERED_READ is marked as Gfx9 but
it is in the bspec and the PRM does mention it (although not in the
list), so keep it around since we've been using it for a while now.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629 >
2024-03-07 15:53:18 +00:00
59c5c67d22
intel/elk: Rename symbols for A64 OWord Block R/W messages
...
These are also present in Gfx8, so use the GFX8 instead of
GFX9 as prefix to avoid confusion.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629 >
2024-03-07 15:53:18 +00:00
05d78994a7
intel/elk: Remove Gfx9+ sampler messages and modes
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629 >
2024-03-07 15:53:18 +00:00
9b709e31cb
intel/elk: Remove Gfx12 SFIDs and related LSC code
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629 >
2024-03-07 15:53:18 +00:00
43b2261ab5
intel/elk: Remove SYNC opcode and SWSB annotations
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629 >
2024-03-07 15:53:18 +00:00
37cd18e30e
intel/elk: Remove encoding for Gfx9+
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629 >
2024-03-07 15:53:18 +00:00
accac95c0d
intel/elk: Remove EU compaction logic for Gfx9+
...
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629 >
2024-03-07 15:53:18 +00:00
e8c4104362
intel/elk: Remove IADD3 opcode
...
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629 >
2024-03-07 15:53:17 +00:00
d1049408b5
intel/elk: Remove ROR and ROL opcodes
...
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629 >
2024-03-07 15:53:17 +00:00
28a7265b10
intel/elk: Remove DP4A opcode
...
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629 >
2024-03-07 15:53:17 +00:00
9e58170f84
intel/elk: Remove BTD and RT opcodes
...
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629 >
2024-03-07 15:53:17 +00:00
24569b8079
intel/elk: Remove DPAS opcode
...
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629 >
2024-03-07 15:53:17 +00:00
7b90470ca1
intel/elk: Remove split sends
...
They are not supported in Gfx8-.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629 >
2024-03-07 15:53:17 +00:00
0b6a2c24d6
anv: don't copy the null descriptor from the GPU memory
...
Performance regression with vkd3d-proton.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: 9506d3f338tapani.palli@intel.com >
Tested-by: Felix DeGrood felix.j.degrood@intel.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28010 >
2024-03-06 22:45:13 +00:00
6823ffe70e
anv: try to keep the pipeline in GPGPU mode when buffer transfer ops
...
To avoid ping-ponging between 3D & GPGPU in the following sequence :
vkCmdDispatch(...)
vkCmdCopyBuffer(...)
vkCmdDispatch(...)
We can try to keep the pipeline in GPGPU mode when doing blorp buffer
operations (we have blorp support for the CCS and can use the same
shaders on RCS).
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27956 >
2024-03-06 20:33:12 +00:00
194afe8416
anv/iris/blorp: use the right MOCS values for each engine
...
There are multiple problems currently :
- blorp blitter commands overwrite the protection value coming from
the driver
- anv & iris are using render target MOCS for compute commands
Driver already have the ability to pass the MOCS values so we choose
to stick to that in this change. But now the driver need to select the
right MOCS depending on the engine the commands are going to run onto.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Cc: mesa-stable
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27956 >
2024-03-06 20:33:12 +00:00
c40f14bb31
anv: fix incorrect ISL usage in buffer view creation
...
We need to use the usage parameter.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: 64f20cec28rohan.garg@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27956 >
2024-03-06 20:33:12 +00:00
9baa57158d
intel/genxml: update PIPE_CONTROL so that we can decode it on the CCS
...
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28013 >
2024-03-06 14:37:11 +00:00
731ffa0737
anv, blorp: Set COMPUTE_WALKER Message SIMD field
...
Fixes: d95bbf35rohan.garg@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27983 >
2024-03-06 10:58:27 +00:00
0de856ecef
anv: fix companion command buffer initialization
...
Currently the command buffer is completely empty, which is not good.
There are a few of things that should be programmed, but we've
probably been okay due to the default engine initialization.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: edcde0679crohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27979 >
2024-03-06 10:23:34 +00:00
67c9f94b05
anv: delay internal shader upload to when needed
...
People reported an increase in device initialization affecting some
Android tests [1].
So delay the internal shader upload (similar to what we do for blorp
shaders, and what RADV seems to be doing too) until actually needed.
[1] : https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25361#note_2305129
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Matt Turner <mattst88@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27946 >
2024-03-06 09:58:53 +00:00
597c1c1c18
intel/dev: declare workarounds required by ATSM platforms
...
INTEL_PLATFORM_ATSM_G10 requires the same workarounds as INTEL_PLATFORM_DG2_G10
INTEL_PLATFORM_ATSM_G11 requires the same workarounds as INTEL_PLATFORM_DG2_G11
Closes : #10749
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27987 >
2024-03-05 22:49:14 -08:00
1316854e74
ci/intel: split asus-cx9400-volteer into acer-cp514-2h-11{30,60}g7-volteer
...
Cc: mesa-stable
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27877 >
2024-03-06 01:52:49 +00:00
861c123ba0
ci/intel: move machine definition to the intel-tgl-skqp job
...
Cc: mesa-stable
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27877 >
2024-03-06 01:52:49 +00:00
f9ba492647
ci/intel: add acer-cp514-2h-11{30,60}g7-volteer
...
Originally asus-cx9400-volteer, but now we can choose machine regarding
to available CPU within.
Cc: mesa-stable
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27877 >
2024-03-06 01:52:49 +00:00
ed73137d35
ci/intel: decompose anv-tgl-test so we can specify custom devices for TGL
...
No functional changes.
Cc: mesa-stable
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27877 >
2024-03-06 01:52:49 +00:00
db103c56ab
treewide: Remove vulkan/runtime vulkan/util prefix in include path
...
This is for unify the include style of shared vulkan headers
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com >
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27526 >
2024-03-05 19:05:00 +00:00
c82edb4e8f
anv: drop duplicated 3DSTATE_SLICE_TABLE_STATE_POINTERS emission
...
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27985 >
2024-03-05 15:49:41 +00:00
edf14f4b7c
intel/brw: Unindent code after previous change
...
I kept things indented in the previous patch to make the diffs easier to
read, but there's no reason to continue doing so.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27959 >
2024-03-05 12:03:31 +00:00
4c10613625
intel/brw: Remove SIMD lowering to a larger SIMD size
...
On Gfx4, we had to emulate SIMD8 texturing with SIMD16 for some message
types. This ceased to be a thing with Gfx5 and hasn't come up again.
So, we can simply assert that we are truly "SIMD splitting", and assume
that the lowered size is smaller than the original instruction size.
This avoids some mental complexity as we can always think of the split
instructions as taking apart, operating on, and recombining subsets of
the original values.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27959 >
2024-03-05 12:03:31 +00:00
bb191e3af5
intel/brw: Call constant combining after copy propagation/algebraic
...
This copy propagation can create MADs with immediates in src1, which
need to be cleaned up by constant combining (which puts them back in
VGRFs).
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27876 >
2024-03-05 11:39:26 +00:00
e8ef184677
intel/brw: Make register coalescing obey the g112-g127 restriction
...
opt_register_coalesce can sometimes unpleasantly coalesce both
SENDS payload sources into the larger of the two registers.
This can break the assumption that the VGRFs for sources 2-3
must occupy no more than 16 registers, so they fit in g112-127.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27876 >
2024-03-05 11:39:26 +00:00
1c1e79d75a
intel/brw: Copy the smaller payload in fixup_sends_duplicate_payload
...
Sometimes one source can be a larger register than the other, especially
since opt_register_coalesce can sometimes coalesce those sources into
larger registers.
Copy the smaller of mlen and ex_mlen. It's less copying.
shader-db and fossil-db on Alchemist show 47 shaders affected with
small 1-2 instruction improvements each, and no regressions.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27876 >
2024-03-05 11:39:26 +00:00
91252c98a8
intel/brw: Add assertions that EOT messages live in g112+
...
The validator already catches this, but asserting here makes it easier
to catch the problem earlier in a debugger.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27876 >
2024-03-05 11:39:26 +00:00
f6ac6c94a9
intel/brw: Handle SHADER_OPCODE_SEND without src[3] in copy prop
...
We construct some SENDs with only 3 sources (such as FB writes).
This code could read out of bounds.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27876 >
2024-03-05 11:39:26 +00:00
49606ab067
intel/brw: Avoid copy propagating any fixed registers into EOTs
...
We were handling FIXED_GRF, but we probably also ought to handle ATTR
(pushed inputs) and UNIFORM (pushed constants). Just check if file
isn't VGRF to handle everything.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27876 >
2024-03-05 11:39:26 +00:00
97bf3d3b2d
intel/brw: Replace CS_OPCODE_CS_TERMINATE with SHADER_OPCODE_SEND
...
There's no need for special handling here, it's just a send message
with a trivial g0 header and descriptor.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27924 >
2024-03-05 11:16:20 +00:00
dde2527afb
anv: add support for VK_EXT_map_memory_placed
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27963 >
2024-03-05 07:03:13 +00:00
6ad2a03ffd
anv: remove some wrapping around mmap
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27963 >
2024-03-05 07:03:13 +00:00
9d18cde8ed
hasvk: make sure aux is disabled for memory objects
...
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27948 >
2024-03-04 20:36:34 +02:00
78ea3bb43d
ci/deqp: use the proper gl/gles releases for deqp-gl*, deqp-gles*, deqp-egl
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27473 >
2024-03-04 16:53:58 +00:00
f3b0330fbc
anv: fix helper usage for CmdUpdateBuffer()
...
We created a new helper for things that don't need to be indexed from
the dynamic state pool. This allocation got missed.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: 82d772fa9bjose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27966 >
2024-03-04 16:24:24 +00:00
e5bbf4975f
iris/ci: add pbuffer flakes for amly, same as apl and glk
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27932 >
2024-03-02 13:08:24 +00:00
63d2aa4eb6
intel/brw: Mark FIND[_LAST]_LIVE_CHANNEL as not writing the flag
...
brw_lower_find_live_channel doesn't actually write a flag register,
but elk_find_live_channel notes that the flag was used on Gfx7.
This allows more CSE on FIND[_LAST]_LIVE_CHANNEL.
shader-db and fossil-db on Alchemist show minor reductions in cycles
and instruction count, a few minor increases, but it doesn't seem to
be a large effect in either direction.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27862 >
2024-03-01 17:18:30 -08:00
337641cfcc
intel/compiler: Fix SIMD lowering when instruction needs a larger SIMD
...
When lower_simd_width() encounters an instruction that needs a larger
SIMD, for example SHADER_OPCODE_TXS_LOGICAL in Gfx4 needs at least
SIMD16. In this case the builder needs to be at least as large as
max_width, otherwise the group() setup will assert.
Turns out this did not assert before "by accident", since it was
relying on the default fs_visitor builder that had a dispatch width of 64,
a bogus placeholder value, expected not to be used.
However, when we changed the code to remove that builder (and the bogus
value), we created a new builder in the pass shader dispatch_width --
which work fine except in the case where we want to "lower" the SIMD above
the shader dispatch width. The fix is to also consider the already
calculated max_width when creating the builder.
Fixes: 5b8ec015f2https://gitlab.freedesktop.org/mesa/mesa/-/issues/10338
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27782 >
2024-03-01 22:54:57 +00:00
ad37622a8f
intel/brw: Delete legacy texture opcodes
...
We first generate the logical opcodes, and these days fully lower to
SHADER_OPCODE_SEND. In the past, we lowered to a non-logical variant
and handled that in the generator. These days, we were just using the
non-logical opcodes as an awkward intermediate opcode change during
the lowering...which isn't really necessary at all.
This patch eliminates them by using the original logical opcodes.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27908 >
2024-03-01 22:19:51 +00:00
19248f48eb
intel/brw: Allow CSE on TXF_CMS_W_GFX12_LOGICAL
...
This was missed when adding the new XeHP variant of the opcode.
Fixes: 261dd6c8caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27908 >
2024-03-01 22:19:51 +00:00
45a5e4c0c4
intel/brw: Delete SHADER_OPCODE_TXF_UMS
...
Nothing seems to generate this anymore. I guess we always use CMS.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27908 >
2024-03-01 22:19:51 +00:00
601ef12467
intel/brw: Delete SHADER_OPCODE_TXF_CMS[_LOGICAL]
...
We always use the wide variant (_W) on hardware this compiler supports.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27908 >
2024-03-01 22:19:50 +00:00
Caio Oliveira