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Author SHA1 Message Date
Faith Ekstrand 4d54b423e7 nir: Don't clang-format a couple typedefs 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24382>
 2023-08-12 19:27:28 +00:00
Faith Ekstrand 8579224fe1 nir: Don't clang-format const_value helpers 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24382>
 2023-08-12 19:27:28 +00:00
Faith Ekstrand a89fb36f6b nir: Re-align a couple enums and add clang-format comments 
I actually kinda care about the human-readable formatting of these
enums.  Keep clang-format from messing them up.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24382>
 2023-08-12 19:27:28 +00:00
Faith Ekstrand a6be819121 clang-format: Set the default ColumnLimit to 0 
This is a better default than any actual limit because it causes
clang-format to mostly leave line wrapping alone.

Suggested-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24382>
 2023-08-12 19:27:28 +00:00
Faith Ekstrand 54680948a8 clang-format: nir_foreach_src is not a foreach macro 
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24382>
 2023-08-12 19:27:28 +00:00
Faith Ekstrand fe5671e881 clang-format: Add nir_foreach_reg_* 
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24382>
 2023-08-12 19:27:28 +00:00
Roman Stratiienko ee42e2166d android: Introduce the Android buffer info abstraction 
Both EGL and Vulkan implementations require obtaining buffer metadata,
e.g., format, modifier, offsets, strides, etc.

Currently, mesa3d doesn't have a generic solution, and every Vulkan
implementation uses its getters. Most of the getters rely on
kernel metadata storage that is available for x86-based GPU drivers.

ARM-based Vulkan drivers rely on userspace metadata sharing, making it
important to use advanced metadata API. Otherwise, the driver will work
with limited functionality (no YUV, lack of support for modifiers, etc.)

Current EGL buffer getter implementation is advanced enough and used as
a base for a common Android buffer-getter logic.

Use example:

    void
    android_buffer_test(android_handle_type *a_handle)
    {
       // First, get the gralloc object. It will be created if it doesn't
       // exist. Use U_GRALLOC_TYPE_AUTO to let the implementation choose
       // the best gralloc
       struct u_gralloc *gralloc = u_gralloc_create(U_GRALLOC_TYPE_AUTO);

       // Prepare the internal handle structure (hal_format and
       // pixel_stride are required for the fallback implementation).
       // Both Vulkan and EGL clients expose HAL format / pixel stride
       // in their structures.
       u_gralloc_buffer_handle hnd = {
          .handle = a_handle->native_handle,
          .hal_format = a_handle->hal_format,
          .pixel_stride = a_handle->pixel_stride,
       };

       // Get the basic buffer info
       u_gralloc_buffer_basic_info basic_info;
       int ret = u_gralloc_get_buffer_basic_info(gralloc, &hnd, &basic_info);
       if (ret) {
          // Handle the error
       }

       // Get the color info
       u_gralloc_buffer_color_info color_info;
       ret = u_gralloc_get_buffer_color_info(gralloc, &hnd, &color_info);
       if (ret) {
          // Handle the error
       }

       // unref the gralloc object
       u_gralloc_destroy(&gralloc);
    }

Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18215>
 2023-08-12 18:46:57 +00:00
Roman Stratiienko 21dcde096f util: Add NONNULL macro 
Macro leverages __attribute__((__nonnull__)) to help users mark
the function parameter that isn't allowed to be NULL.

Suggested-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18215>
 2023-08-12 18:46:57 +00:00
David Heidelberg 9bf104f934 ci/deqp: really remove the uncompressed results.csv file 
Arguments are parsed in order, so the `-c` here causes that first `--rm`
won't get applied and then it gets overriden by `-o` which writes the file.

Sadly zstd won't report this as a issue, but that's being reported in [1],
so maybe in future versions zstd will warn about it.

[1] https://github.com/facebook/zstd/issues/3719

Fixes: d110299d77 ("ci/deqp-runner: compress results.csv before uploading it to GitLab")

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24651>
 2023-08-12 19:32:34 +02:00
Lionel Landwerlin 7cc2f23d53 anv: move genX(rasterization_mode) to gfx8_cmd_buffer.c 
Only used there.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24632>
 2023-08-12 13:49:32 +00:00
Lionel Landwerlin 705840d417 anv: get rid of genX(emit_multisample) 
The initialization can be simplified and the real programming moved
over to genX_pipeline.c

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24632>
 2023-08-12 13:49:32 +00:00
Lionel Landwerlin eef54f3175 intel/decoder: add options to decode surfaces/samplers 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24632>
 2023-08-12 13:49:32 +00:00
Lionel Landwerlin cf5ee0a0f7 anv: emit 3DSTATE_GS only once per pipeline 
Following 71ebd9b9d7, 3DSTATE_GS can be emitted as part of the
pipeline batch and as a dynamic state. Just do the latter.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 71ebd9b9d7 ("anv,hasvk: respect provoking vertex setting on geometry shaders")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24632>
 2023-08-12 13:49:31 +00:00
Lionel Landwerlin 8689791e1f blorp: drop programming of 3DSTATE_(MESH|TASK)_SHADER 
We can disable the MESH/TASK stages by just using the CONTROL
instruction and keep the rest of the HW programmed as before.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24632>
 2023-08-12 13:49:31 +00:00
Lionel Landwerlin 22c7ccb523 intel/decoder: constify some input parameters 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24632>
 2023-08-12 13:49:31 +00:00
David Heidelberg 9d45a25b80 ci/farms: enabled Microsoft job only when conditions are met 
Otherwise it gets run by default on newly pushed fork branch.

In general, this is copy-paste of `.container-rules`.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24604>
 2023-08-12 13:09:13 +00:00
antonino 19d318d88a zink/nir: add a zink specific intrinsic for push constants 
Push costants in Zink are not flat indexed like in vulkan drivers which
makes the `nir_intrinsic_load_push_constant` intrinsic inappropiate.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24401>
 2023-08-12 12:20:31 +00:00
antonino 333b6ef409 zink: remove unused indices from nir_load_push_constant calls 
Zink passes `base` and `range` indices to this intrinsic despite those
being ignored by nir_to_spirv. This change removes them completely.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24401>
 2023-08-12 12:20:31 +00:00
David Heidelberg 57b8b82d7d ci/freedreno: document vs-nested-return-sibling-loop2 flake on Adreno 530 
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24607>
 2023-08-12 13:35:24 +02:00
David Heidelberg aee00062f4 ci/amd: add glx@glx-visuals-depth flake to raven 
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24607>
 2023-08-12 13:35:23 +02:00
David Heidelberg 17021f70f4 ci/build: limit debian-build-testing to 30 minutes 
Previous 45 minutes is too much.

 - 5 - 15 minutes mesa LTO build
 - 5 - 15 minutes shader-db run

Should be safe, in case something fails, we still can make another run.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24607>
 2023-08-12 13:35:23 +02:00
Georg Lehmann 9585689839 nir/opt_if: also rewrite uniform uses for read_invocation 
No Foz-DB changes, but maybe it matters in the future because dxil-spirv
will use read_invocation for WaveReadLaneFirst in fragment shaders.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24618>
 2023-08-12 07:16:28 +00:00
Samuel Pitoiset ce0c70fb0c vulkan: ignore VkPipelineColorWriteCreateInfoEXT if the state is dynamic 
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24601>
 2023-08-11 23:38:55 +00:00
Erico Nunes c43135d740 egl/drm: fix EGL_EXT_buffer_age with gbm contexts 
Fix remaining dri2 check from 3d59f4cfcb, which caused gbm contexts to
not expose EGL_EXT_buffer_age anymore.

Fixes: 3d59f4cfcb ("egl/drm: Use IMAGE_DRIVER instead of DRI2_LOADER")

Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24630>
 2023-08-11 21:50:21 +00:00
Alyssa Rosenzweig ae81eb9d50 asahi: Legalize compression before blitting 
Fixes invalid recursive blitting.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig 7ac6176ea5 agx: Do not allow creating vec8 
mem_access_bit_size needs to split up 64x4 into 2 loads. Fixes:

dEQP-VK.spirv_assembly.instruction.compute.64bit_compare.int64.comp_opiequal_vector

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig fd481d00d3 agx: Handle <32-bit local memory access 
I don't know if this is possible to hit with GL, but it is with Vulkan. Fixes:

dEQP-VK.spirv_assembly.instruction.compute.workgroup_memory.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig aeffd22c30 agx: Handle f2f16_rtne like f2f16 
TBD whether we can control round modes later on.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig 4002ba95bb agx: Lower f2f16_rtz 
Based on what VIR does.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig 3634791baa agx: Fix 64-bit immediate moves 
Don't truncate them in the builder. Fixes:

dEQP-VK.spirv_assembly.instruction.compute.convertutof.uint64_to_float32_4294967296

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig 4d0233cb1d agx: Fix uadd_sat packing 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig 73657cd011 agx: Handle conversions to 8-bit 
These can't be lowered by nir_lower_bit_sizes but it doesn't actually matter.
Fixes SPIR-V conversions tests.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig fa2a7cb2a8 agx: Lower f2u8/f2i8 
The less 8-bit we need to emulate in the backend the better.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig b3ed5228b4 agx: Handle blocks with no predecessors 
This can come up with loops with SPIR-V. Fixes:

dEQP-VK.spirv_assembly.instruction.compute.loop_control.none

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Asahi Lina c247de37bb asahi: Fix incorrect BO bitmap reallocations 
If the BO handle is greater than 2x what fits inside the current bitmap
size, then we end up overflowing. Make sure to always reallocate to a
large enough bitmap, not just 2x the previous size.

Found while replaying firefox apitraces with looping (which apparently
leaks a ton of objects, but that might just be apitrace).

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Asahi Lina f1fedb72d3 asahi: Handle non-written RTs correctly 
When a bound RT is not written to, we need to force the pass type to
translucent to ensure that this draw does not cull draws that do write
to that RT.

Fixes Inochi2D regression after c24b753378.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Mary 0f4e3a03fd agx: Move nir_lower_fragcolor out of agx_preprocess_nir 
Do not apply "nir_lower_fragcolor" in the common code.

This fix a crash on agxv side when a frag shader have SSBO writes.

This is caused by "nir_lower_frag_color" assuming that every
"store_deref" will have a variable backing the
output.

Signed-off-by: Mary <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig 3704caca0b agx: Stop setting forwarding bit 
We need actual analysis to set it properly, and improperly setting it can cause
random data dependency hazards it turns out. Stop setting it. Fixes some flaky
tests with shuffle code inserted.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig 09dfaf2c91 agx: Remove unused allocation 
Relic from early RA attempts.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig ae440c9929 agx: Don't reuse ssa_to_reg across blocks 
This avoids an entire class of bugs with live range splitting. Fixes with
AGX_MESA_DEBUG=demand:

   dEQP-GLES31.functional.separate_shader.random.8

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig d035908550 agx: Don't use ssa_to_reg across blocks 
This is a footgun with live range spltiting.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig 964a67fda4 agx: Assert invariant stated in the comment 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig 6909cb6379 agx: Use agx_replace_src 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig 6447bf4cce agx: Stop setting registers after the shader 
Leftover from before live range splitting. Should be a no-op.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig 87121cf9a4 agx: Set phi sources in predecessors 
This ensures correctness with live range splits. Now agx_set_sources is only for
non-phis where it makes sense.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig 8cc96d64b0 agx: Fix accounting for phis 
All affected shaders are in pubg. Presumably, with the new demand calculation,
RA is hitting a higher target thread count at the expense of a little more live
range splitting.

   total instructions in shared programs: 1773295 -> 1773310 (<.01%)
   instructions in affected programs: 6058 -> 6073 (0.25%)
   helped: 0
   HURT: 15
   Instructions are HURT.

   total bytes in shared programs: 11695360 -> 11695450 (<.01%)
   bytes in affected programs: 40496 -> 40586 (0.22%)
   helped: 0
   HURT: 15
   Bytes are HURT.

   total halfregs in shared programs: 530844 -> 530724 (-0.02%)
   halfregs in affected programs: 1785 -> 1665 (-6.72%)
   helped: 15
   HURT: 0
   Halfregs are helped.

   total threads in shared programs: 18909440 -> 18910400 (<.01%)
   threads in affected programs: 12480 -> 13440 (7.69%)
   helped: 15
   HURT: 0
   Threads are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:28 +00:00
Alyssa Rosenzweig d2224544d6 agx: Allow 64-bit memory regs 
The mask is based on the format, which can be at most 32-bits per channel. So if
we have 64-bit loads/stores we're still using a 32-bit format with double the
bits set in the mask. This will fix validation fails with spilling.

No shader-db changes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:27 +00:00
Alyssa Rosenzweig d0b966cb10 agx: Maintain ctx->max_reg while assigning regs 
We can't calculate after since ssa_to_reg[] gets overwritten during live range
splits. Theoretical issue only, but let's fix it while squashing live range
splitting bugs.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:27 +00:00
Alyssa Rosenzweig b973e38214 agx: Fix AGX_MESA_DEBUG=demand 
No wonder it seemed like it wasn't doing anything!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:27 +00:00
Alyssa Rosenzweig 135f3c35c5 agx: Optimize logical_end removal 
We know logical_end instructions are only at the end of the block (validated),
so by changing how we iterate the pass goes from O(instructions) to O(blocks)
which is strictly better.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
 2023-08-11 20:31:27 +00:00