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5656 Commits

Author SHA1 Message Date
Timothy Arceri
1a8f918050 intel/compiler: add and fix up fallthrough comments for gcc warnings 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5714>
 2020-07-02 12:11:30 +10:00
Timothy Arceri
512db7ec78 anv: update fallthrough comment so gcc sees it 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5714>
 2020-07-02 12:11:30 +10:00
Matt Turner
8da810a7fb intel/compiler: Don't emit no-op cr0 changes 
If mask is 0, we're asking for no changes to cr0.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5566>
 2020-07-02 01:24:06 +00:00
Matt Turner
fe14dc98bf intel/compiler: Add assert that set bits are within mask 
We generate bitfields of bits that we want to retain (mask) and bits
that we want to set (brw_mode) in the cr0 register, so the bits we want
to set should be in the set of bits we want to retain.

Also, remove the initialization of mask from
fs_visitor::emit_shader_float_controls_execution_mode since
brw_rnd_mode_from_nir initializes the mask parameter unconditionally.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5566>
 2020-07-02 01:24:06 +00:00
Jan Beich
2e5b214506 anv: disable i915_perf warning on non-Linux 
$ vkcube
INTEL-MESA: warning: Performance support disabled, consider sysctl dev.i915.perf_stream_paranoid=0

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5461>
 2020-06-30 21:05:52 +00:00
Rafael Antognolli
66df2ffa36 anv: Align "used" attribute to 64 bits. 
This is a 64 bits value that might not be aligned on 32 bit plaforms.
Since it's used with atomics, let's make sure it gets properly aligned
to avoid any potential performance loss.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5637>
 2020-06-25 22:11:36 -07:00
Kenneth Graunke
8278a46b26 intel: Disable loading drivers on DG1 devices for now 
Kernel support for DG1 has not yet been merged upstream; per our
long-standing DRM subsystem policy, we should not enable the platform
in userspace until the kernel patches are merged and functional.

We will re-enable this in the future.  In the meantime, we retain all
of the infrastructure and code for the platform so that we can continue
developing DG1 support in upstream.

See a discussion here:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956#note_547775

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5617>
 2020-06-24 02:48:04 +00:00
Jordan Justen
ecf3335eef anv/cmd_buffer: Split GPGPU_WALKER out to emit_gpgpu_walker 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5571>
 2020-06-24 00:14:36 +00:00
Jordan Justen
759b7f83dd anv/pipeline: Split VFE/INTERFACE_DESCRIPTOR out to emit_media_cs_state 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5571>
 2020-06-24 00:14:35 +00:00
Jason Ekstrand
561aaeeb48 intel/eu: Add the RNDU opcode 
We don't want to use it on gen5 and earlier because only RNDD can be
done with a single instruction and we can implement RNDU(x) as -RNDD(-x)
so it's better to just do that when we have the instruction.  On gen6
and above, we may as well just use the right instruction.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5596>
 2020-06-23 17:43:54 +00:00
Jason Ekstrand
e0ab48e3ea intel/eu: Set the right subnr for ALIGN16 destinations 
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5596>
 2020-06-23 17:43:54 +00:00
Jason Ekstrand
8a0d772dca intel/eu: Add a brw_urb_dest_msg_type helper 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5596>
 2020-06-23 17:43:54 +00:00
Kenneth Graunke
2c762955d4 intel/eu: Add a brw_urb_desc helper 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5596>
 2020-06-23 17:43:53 +00:00
Jason Ekstrand
ecda98fbb2 intel/compiler: Expose brw_texture_offset to C 
Some day we probably want to move it out of brw_shader if we're going to
share it with IBC but that can be another day.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5596>
 2020-06-23 17:43:53 +00:00
Jason Ekstrand
479797e130 intel/fs: Move more prog_data setup into populate_wm_prog_data 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5596>
 2020-06-23 17:43:53 +00:00
Jason Ekstrand
fc519cad57 intel/fs: Break wm_prog_data setup into a helper 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5596>
 2020-06-23 17:43:53 +00:00
Jason Ekstrand
2687ec5ee6 intel/fs: Expose a couple of NIR lowering helpers 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5596>
 2020-06-23 17:43:53 +00:00
Jason Ekstrand
6ac99b9f39 anv: Bump the advertised patch version to 145 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5597>
 2020-06-22 23:24:25 +00:00
Jordan Justen
c72832e83c anv: Make use of devinfo has_aux_map field 
Reworks:
 * Use device rather than physical_device for info. (Lionel)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5572>
 2020-06-22 22:32:03 +00:00
Eric Engestrom
04e8eaf4e8 util: rename xmlpool.h to driconf.h 
To make it clearer what it is and does.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>
 2020-06-22 21:50:12 +00:00
Eric Engestrom
2ef983dca6 driconf: drop now unused translation facility 
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>
 2020-06-22 21:50:12 +00:00
Jordan Justen
c323e0ddf3 intel/dev: Add device info for DG1 
Reworks:
 * Anuj: Set is_dg1
 * Anuj: Add dg1 to gen_device_name_to_pci_device_id
 * Anuj: Update simulator id
 * Rafael: has_llc = false

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:42:00 -07:00
Rafael Antognolli
37a724e4ae anv/dg1: Don't use SET_TILING kernel uapi. 
It is not available on discrete platforms anymore.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:42:00 -07:00
Rafael Antognolli
762e601f77 intel/devinfo: Add function to check for DRM_I915_GEM_GET_TILING. 
Future (discrete) platforms won't have support for get/set tiling. This
function allows our drivers to query for that, by simply trying to get
the tiling from a dummy buffer.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:42:00 -07:00
Rafael Antognolli
86617c08cc intel/l3: Return the URB size from devinfo for DG1 
We don't have any URB size set in the L3 config, since it's a fixed
value now. So just return the value that we know from gen_device_info.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:42:00 -07:00
Rafael Antognolli
793b409241 intel/isl: Update mocs for DG1 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:42:00 -07:00
Anuj Phogat
3daa866751 intel/l3: Add DG1 L3 configuration 
Reworks:
 * Jordan: Make DG1 L3 config table empty

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:41:59 -07:00
Jordan Justen
633dec7163 anv: Set L3 full way allocation at context init if L3 cfg is NULL 
If the platform's default L3 config is NULL, then it now gets
initialized only at context init time, and cmd_buffer_config_l3 will
always return immediately.

Rework:
 * Remove unneeded check on !cfg in cmd_buffer_config_l3 (Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:41:59 -07:00
Jordan Justen
6054b24f58 intel/l3: Allow platforms to have no l3 configurations 
On some gen12 platforms we will use the L3FullWayAllocationEnable and
never reconfigure the L3 setup.

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:41:59 -07:00
Jordan Justen
49fe43e15f intel/l3: Don't rely on cfg entry URB size being 0 as a sentinal 
An example entry with URB size being 0 is in the cnl list.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:41:59 -07:00
Anuj Phogat
f1fba99695 intel/devinfo: Add is_dg1 to device info 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:41:55 -07:00
Arcady Goldmints-Orlov
04f77595f0 intel/compiler: Always apply sample mask on Vulkan. 
With OpenGL, shader writes to the sample mask are ignored when not
rendering to a multisample render target. However, on Vulkan, writes to
the sample mask have still have their effect in that case.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3016

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5156>
 2020-06-19 20:24:11 -05:00
Nanley Chery
b25fedeff9 isl/drm: Support I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS 
Add an entry for this modifier in the modifier_info array.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5420>
 2020-06-19 23:32:29 +00:00
Nanley Chery
db5d98cde8 intel: Add ISL_AUX_USAGE_GEN12_CCS_E 
Add a new aux usage which more accurately describes the behavior of
CCS_E on gen12. On this platform, writes using the 3D engine are either
compressed or substituted with fast-cleared blocks.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5363>
 2020-06-19 22:41:40 +00:00
Jason Ekstrand
77c50891b6 anv: Use resolve_device_entrypoint for dispatch init 
There's no good reason to have the "which table do I use?" code
duplicated twice.  The only advantage to the way we were doing it before
was that we could move the switch statement outside the loop.  If this
is ever an actual device initialization perf problem that someone cares
about, we can optimize that when the time comes.  For now, the
duplicated cases are simply a platform-enabling pit-fall.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5530>
 2020-06-19 19:13:56 +00:00
Matt Turner
1f87106276 intel/tools: Add assembler tests for the cr0 register 
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
 2020-06-19 02:10:40 +00:00
Matt Turner
e573f21edd intel/tools: Disallow control subregisters > 3 
> 4 was probably a typo, since the documentation says that there are 4
subregisters (0-3).

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
 2020-06-19 02:10:40 +00:00
Matt Turner
cc6fc963f0 intel/tools: Require explicit regions/types for special regs 
The docs say that these registers should  only be read with a certain
type, and I'm inclined to believe that the hardware behaves that way,
but it makes the assembler a little more confusing and also confuses the
user of the assembler that some operands don't take types or regions.

Just always requiring regions and types seems like the sensible thing.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
 2020-06-19 02:10:40 +00:00
Matt Turner
9feb6302f9 intel/tools: Drop srctype from ipreg 
It's unused, and it would cause shift/reduce conflicts after the next
patch.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
 2020-06-19 02:10:40 +00:00
Matt Turner
27557e7110 intel/tools: Remove unnecessary reg number checking 
a0 is the only address register, and cr0 is the only control register,
so there's no need to return the register number, espcially since the
lexer explicitly consumes "a0" and "cr0".

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
 2020-06-19 02:10:40 +00:00
Eric Engestrom
00defe2e0a anv: replace all dup() with os_dupfd_cloexec() 
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5369>
 2020-06-18 02:09:56 +00:00
Iván Briano
ed7bebc17b anv: enable VK_EXT_pipeline_creation_cache_control 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5136>
 2020-06-17 00:48:39 +00:00
Iván Briano
23633f6c69 anv: implement VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT 
v2:
* Set pPipeline to NULL in the corresponding
  graphics/compute_create_pipeline function.
* Keep current ANV behavior of bailing on the first real error.

v3:
* Don't return early if the pipeline succeeded.

v:4(5?):
* Simplify return conditions.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5136>
 2020-06-17 00:48:39 +00:00
Iván Briano
13f44596d7 anv: support externally synchronized pipeline caches 
Implement the VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT_EXT
bits of the VK_EXT_pipeline_creation_cache_control extension.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5136>
 2020-06-17 00:48:39 +00:00
Sagar Ghuge
a0ef4971d0 intel/compiler: Remove unnecessary optimization for MUL 
2 source instruction only support immediate for src1 operand, so no
point in adding optimization condition for src0 oprand.

v2:
- Update commit message and don't remove ADD optimization (Matt Turner)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5341>
 2020-06-16 17:11:32 -07:00
Sagar Ghuge
d4f3f9390f intel/compiler: Optimize integer add with 0 into mov 
Kaby Lake
total instructions in shared programs: 326560 -> 323616 (-0.90%)
instructions in affected programs: 178062 -> 175118 (-1.65%)
helped: 129
HURT: 0
helped stats (abs) min: 1 max: 118 x̄: 22.82 x̃: 8
helped stats (rel) min: 0.35% max: 6.56% x̄: 2.57% x̃: 2.47%
95% mean confidence interval for instructions value: -27.71 -17.93
95% mean confidence interval for instructions %-change: -2.81% -2.32%
Instructions are helped.

total cycles in shared programs: 43741127 -> 45397851 (3.79%)
cycles in affected programs: 40880261 -> 42536985 (4.05%)
helped: 94
HURT: 34
helped stats (abs) min: 5 max: 6160 x̄: 598.91 x̃: 45
helped stats (rel) min: 0.20% max: 34.86% x̄: 2.52% x̃: 1.09%
HURT stats (abs)   min: 1 max: 76198 x̄: 50383.00 x̃: 69677
HURT stats (rel)   min: 0.07% max: 48.41% x̄: 15.65% x̃: 6.49%
95% mean confidence interval for cycles value: 8023.10 17863.21
95% mean confidence interval for cycles %-change: <.01% 4.60%
Cycles are HURT.

total spills in shared programs: 1086 -> 978 (-9.94%)
spills in affected programs: 897 -> 789 (-12.04%)
helped: 24
HURT: 0

total fills in shared programs: 1686 -> 1584 (-6.05%)
fills in affected programs: 1371 -> 1269 (-7.44%)
helped: 24
HURT: 0

v2:
- Use brw_reg_type_is_integer (Matt Turner)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5341>
 2020-06-16 16:54:27 -07:00
Lionel Landwerlin
762706c5a6 anv: add an option to disable secondary command buffer calls 
Those are currently hurting Felix' ability to look at the batches.

We can probably detect this in the aubinator but that's a bit more
work than falling back to the previous behavior.

v2: Condition VK_KHR_performance_query to not using this variable (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5391>
 2020-06-16 20:23:52 +00:00
Jason Ekstrand
8f9b8af782 anv: Add anv_pipeline_init/finish helpers 
This cleans up pipline create/destroy a bit after the compute/gfx split.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5457>
 2020-06-16 17:02:44 +00:00
Jason Ekstrand
1b693341ac anv: Add an anv_batch_set_storage helper 
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5457>
 2020-06-16 17:02:44 +00:00
Jan Beich
fcdefa7e47 anv,iris: unbreak on BSDs after 812cf5f522ab,abf8aed68047 
../src/intel/vulkan/anv_gem.c:31:10: fatal error: 'linux/sync_file.h' file not found
 #include <linux/sync_file.h>
          ^~~~~~~~~~~~~~~~~~~
../src/gallium/drivers/iris/iris_fence.c:29:10: fatal error: 'linux/sync_file.h' file not found
 #include <linux/sync_file.h>
          ^~~~~~~~~~~~~~~~~~~

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5463>
 2020-06-16 16:02:33 +00:00