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1686 Commits

Author SHA1 Message Date
Timur Kristóf e97f0463a8 ac/nir: Implement NGG deferred attribute culling in NIR. 
Culling is traditionally done by the rasterizer, but that
can be a bottleneck when an app creates a large number
of primitives. Eg. a lot of tiny triangles reduce the
rasterziation efficiency.

NGG makes it possible for the shader to check primitives
and delete those that it can prove are not needed.

After this is done, we have to repack the surviving invocations
so they remain compact. This also saves bandwidth, because
some memory loads are only executed by those vertices that
survived the culling.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10525>
 2021-07-13 23:56:33 +00:00
Timur Kristóf 556a690bac ac/nir: Use a ballot that matches the wave size during NGG lowering. 
This generates slightly more efficient code in Wave32 mode.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10525>
 2021-07-13 23:56:33 +00:00
Timur Kristóf 651a3da1b5 ac/nir: Add a NIR port of ac_llvm_cull. 
The algorithms were originally implemented by Marek Olšák,
hence the copyright to AMD.

This commit just ports the LLVM based implementation to NIR,
using the new intrinsics added earlier.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10525>
 2021-07-13 23:56:33 +00:00
Samuel Pitoiset 29f264f258 ac,radv: implement the cs_regalloc_hang HW bug workaround 
Might fix spurious failures on GFX6 and some GFX7 chips.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11675>
 2021-07-09 13:37:37 +00:00
Marek Olšák b2397c394d ac,radeonsi: move late alloc computation into common code and shader states 
This also fixes a rare deadlock when a scratch buffer is used.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11754>
 2021-07-08 18:37:41 +00:00
Marek Olšák c4644bf3e6 ac/surface/tests: fix the ARM build 
Fixes: 8771d45a "ac/surface/tests: fix a random segfault in the modifier test"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4655

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11754>
 2021-07-08 18:37:41 +00:00
Dave Airlie e5d158881b ac: fix win32 build 
Fixes: e2e9dd44f4 ("ac/surface: Handle non-retiled displayable DCC correctly for modifiers.")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11725>
 2021-07-06 14:49:24 +00:00
Bas Nieuwenhuizen e2e9dd44f4 ac/surface: Handle non-retiled displayable DCC correctly for modifiers. 
There is some hardware with num_render_backends == 1, but the number
of render backends in GB_ADDR_CFG > 1. Turns out this can be turned
off by making them rb unaligned which is valid with only 1 render
backend.

Fixes: 0833dd7d12 ("amd/common: Add support for modifiers.")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10575>
 2021-07-05 22:34:13 +00:00
Pierre-Eric Pelloux-Prayer c564841fae ac/surface: don't print stencil info if tex has no stencil 
color/zs are stored in a union so testing for zs.stencil_offset
isn't the correct way to test for stencil.

Fixes: 988f148db3 ("ac/surface: overlap color and Z/S fields using a union in gfx9_surf_layout")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11625>
 2021-06-29 23:38:21 +02:00
Marek Olšák 86355b5984 ac/gpu_info: adjust the condition for use_late_alloc 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11509>
 2021-06-23 22:37:32 -04:00
Samuel Pitoiset 8f9368ddb7 ac/perfcounters: add a GPU block ID to every block definitions 
The enumeration comes from AMDVLK.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11186>
 2021-06-22 06:38:55 +00:00
Samuel Pitoiset 5a8776fd8c ac/perfcounters: add more SPM configuration fields 
Add the number of SPM wires because sometimes a block has eg.
2 counters but only holds 3 16-bit counters instead of 4.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11186>
 2021-06-22 06:38:55 +00:00
Samuel Pitoiset 3d8d6ebcb0 ac/perfcounters: rename num_multi to num_spm_counters 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11186>
 2021-06-22 06:38:54 +00:00
Samuel Pitoiset da94772510 ac/perfcounters,radeonsi: rework performance counters layout 
Instead of having different layouts which might complicate things when
some registers are missing, hardcode the SELECT and SELECT1 registers
into separate arrays.

The SELECT registers are "legacy" counters, while the SELECT1 registers
are SPM counters.

This is more verbose and emit more UCONFIG registers, but emitting the
SELECT registers is now much simpler and it seems less error prone.
This will also help emitting the SPM configuration.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11186>
 2021-06-22 06:38:54 +00:00
Samuel Pitoiset 66a34be6ac ac/perfcounters: remove ac_pc_block_base::num_prelude 
This seems unnecessary if the first select register is correctly set.
This CB filter was always disabled anyways.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11186>
 2021-06-22 06:38:54 +00:00
Timur Kristóf 72174a3eef ac/nir: Update TCS output barriers with nir_var_mem_shared. 
Output loads and stores are lowered to shared memory access,
so we have to update the barriers to also reflect this.

Closes: #4955
Fixes: bf966d1c1d

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11484>
 2021-06-21 08:27:14 +00:00
Marek Olšák 61a845ca19 ac/surface: don't set DCC_PIPE_ALIGN modifier bit for gfx10 with 1 RB 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11486>
 2021-06-20 01:22:01 -04:00
Marek Olšák 2acd34f266 ac/surface/tests: fix RB counts 
The real number of RBs can be less than what GB_ADDR_CONFIG contains.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11486>
 2021-06-20 01:22:01 -04:00
Georg Lehmann d3f735a249 ac: Enable 32bit predication on gfx9 with fw feature version 52. 
Amdvlk does this as well and it passes the vulkan CTS on renoir.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11297>
 2021-06-11 06:07:10 +00:00
Georg Lehmann fc437ef944 ac: Enable 32bit predication on gfx10. 
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11297>
 2021-06-11 06:07:10 +00:00
Georg Lehmann a41ba20cbd ac: Check me_fw_feature for 32bit predication on gfx10.3 
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11297>
 2021-06-11 06:07:10 +00:00
Timur Kristóf 1e49018ced amd: Add extra source to the mbcnt_amd NIR intrinsic. 
The v_mbcnt instructions can take an extra source that they add to
the result. This is not exposed in SPIR-V but we now expose it in NIR.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
 2021-06-09 16:48:51 +00:00
Timur Kristóf f6b2db298f ac/nir: Refactor and optimize the repacking sequence. 
According to feedback, the terminology with "exclusive scan"
and "reduction" is difficult. Change it to use "repack" instead,
which better fits what this sequence is actually used for.

The new sequence stores only 1 byte / wave to LDS, and uses packed
instructions to produce the results. This has lower latency and
fewer instructions than what we previously had.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
 2021-06-09 16:48:51 +00:00
Leo Liu 43c04ab2b4 radeonsi: separate video hw info based on HW engine individually 
This removes previous "has_hw_decode" and "uvd_enc_supported" and
makes information more accuate for cases where HW decode, HW encode,
and HW JPEG decode might partially available.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11201>
 2021-06-08 09:32:48 -04:00
Samuel Pitoiset 9f7e63e12a ac/debug: fix color printing PKT3 when count in header is too low 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11211>
 2021-06-08 11:19:00 +02:00
Samuel Pitoiset aff92f50c6 ac: add ac_thread_trace::data 
Instead of passing two different structs to ac_dump_rgp_capture().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11156>
 2021-06-03 15:39:34 +00:00
Samuel Pitoiset 416496a0c4 ac/rgp: fix ac_fill_sqtt_asic_info() name 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11156>
 2021-06-03 15:39:34 +00:00
Samuel Pitoiset ea3f72c9d9 ac: rename ac_dump_thread_trace() to ac_dump_rgp_capture() 
RGP captures can contain both SQTT and SPM data. While we are at it,
move it to ac_rgp.h and adjust a message.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11156>
 2021-06-03 15:39:34 +00:00
Samuel Pitoiset 380ac28891 ac: import performance counters from RadeonSI 
Performance counters will be used by RADV for VK_KHR_performance_query
and also for adding SPM support.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11140>
 2021-06-03 07:15:21 +00:00
Samuel Pitoiset a70c3e5c8a ac/rgp: bump the SQTT file minor version to 5 
To match latest RGP spec. Captures generated by RADV still work
with latest RGP (v1.10).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11063>
 2021-06-01 06:09:49 +00:00
Samuel Pitoiset c3a4ca2908 ac/rgp: mark SQTT_FILE_CHUNK_TYPE_ISA_DATABASE as deprecated 
This is now deprecated and reserved for future uses.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11063>
 2021-06-01 06:09:49 +00:00
Marek Olšák 38d3c4251d ac/gpu_info: set has_zero_index_buffer_bug for Navi12 too 
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: mesa-stable@lists.freedesktop.org
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
 2021-05-25 16:15:44 +00:00
Marek Olšák 80f0726e4c amd: add Beige Goby support 
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10878>
 2021-05-24 17:41:34 +00:00
Aaron Liu c54bb135aa amd: add Yellow Carp support 
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10878>
 2021-05-24 17:41:34 +00:00
Samuel Pitoiset 726cb2d6f6 ac: ac_gpu_info::has_vgt_flush_ngg_legacy_bug 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10911>
 2021-05-21 19:46:56 +00:00
Bas Nieuwenhuizen 197d9f008e radv: Add sbt descriptors user SGPR input. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9767>
 2021-05-18 18:29:36 +00:00
Timur Kristóf 60ac5dda82 ac: Add NIR lowering for NGG GS. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
 2021-05-12 13:47:04 +00:00
Timur Kristóf 3d589b8b46 ac: Add new NIR pass to lower NGG VS/TES. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
 2021-05-12 13:47:04 +00:00
Samuel Pitoiset 33ede796d5 radv: fix missing ITERATE_256 for D/S MSAA images that are TC-compat HTILE 
To make them readable by shaders, only needed on GFX10+.

This also fixes corruption with Control and MSAA.

Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10610>
 2021-05-06 06:30:05 +00:00
Marek Olšák f3112c532b ac/surface: document more meta equation dependencies 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10343>
 2021-04-26 22:53:30 +00:00
James Park 1351fcf3c3 amd: Fix warnings around variable sizes 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6162>
 2021-04-23 10:37:22 +00:00
Samuel Pitoiset 1c702a8239 ac: move ac_lower_indirect_derefs() outside of the LLVM dir 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10403>
 2021-04-23 11:52:01 +02:00
James Park a64b36ecaf ac/surface: Move drm_fourcc.h to common header 
Useful for including from RADV without copy/paste.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9709>
 2021-04-22 08:16:11 +00:00
Bas Nieuwenhuizen 9da4590df8 amd/common: Use cap to test kernel modifier support. 
Turns out both kernel v5.10 and v5.11 have the same amdgpu driver
version and only one has modifiers ... In addition the version check
is kinda annoying for backports.

So lets use the cap. Since the cap is technically about ADDFB2 I
tested that this works on rendernodes (and reading the code there
is no distinction from what kind of node this is called).

Fixes: 9a937330ef ("radeonsi: Only set modifier creation function for GFX9+ & with kernel support.")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10337>
 2021-04-20 11:59:43 +00:00
Marek Olšák ec1ddb976a amd/registers: rename IMG_FORMAT to GFX10_FORMAT to disambiguate the meaning 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10261>
 2021-04-17 02:37:49 +00:00
Simon Ser 35e25ea1d0 ac/surface: allow non-DCC modifiers for YUV on GFX9+ 
Accept non-linear tiling for multi-planar formats on GFX9+, as long
as DCC is disabled. DCC support is possible in theory, but untested
for now.

GFX8 is still restricted to linear tiling because it's not yet clear
how modifiers should be handled on these chips for multi-planar
formats. Each plane may need a different modifier.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10134>
 2021-04-15 09:43:17 +00:00
Simon Ser 19378dfe3c ac/surface: use blocksizebits instead of blocksize 
util_format_get_blocksize asserts that the blocksize isn't zero.
However the blocksize will be zero if the format's channel encoding
is unspecified. The channel encoding is only meaningful for the
plain u_format layout, so util_format_get_blocksize can't be used
for formats with another layout. For example, YUV formats don't have
the channel encoding specified.

Use util_format_get_blocksizebits, which just returns zero without
an assertion for formats which don't have a channel encoding.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10134>
 2021-04-15 09:43:17 +00:00
Samuel Pitoiset 97e7b21c42 ac: add missing BUF_DATA_FORMAT_10_11_11 vertex format on GFX10+ 
This format is supported by the driver.

Fixes vertex explosion in Dirt 5.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4635
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10226>
 2021-04-14 18:07:41 +00:00
Samuel Pitoiset f232c404d3 ac/surface: store the HTILE pitch to the surface 
This will be used to copy VRS rates to the HTILE buffer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10187>
 2021-04-14 09:31:13 +00:00
Samuel Pitoiset b9c7c5098e ac/surface: implement HtileAddrFromCoord in NIR 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10187>
 2021-04-14 09:31:13 +00:00