AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
133,328 Commits 1 Branch 0 Tags
987a0e6a67c856be207364ada4b838073710ba7d
Commit Graph

6477 Commits

Author SHA1 Message Date
Daniel Schürmann 987a0e6a67 radv: call nir_opt_algebraic_late() after lowering idiv for small bitsizes 
This is needed because lower_idiv() introduces ineg again
which we'll remove next.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8425>
 2021-01-12 16:14:00 +00:00
Daniel Schürmann 1ab9dd22a2 radv: optimize idiv_const for small bitsizes 
No fossil-db changes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8425>
 2021-01-12 16:14:00 +00:00
Samuel Pitoiset 20af07d089 radv: fix color resolves if the dest image has DCC 
Using the graphics resolve path when DCC is enabled should only be
a hint to avoid DCC fixup.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3388
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8326>
 2021-01-12 16:03:36 +00:00
Samuel Pitoiset 3e781056b9 radv: fixup DCC after color resolves using the compute path 
If the dest image has DCC it should be re-initialized to the
uncompressed state.

Note that the driver always selects the graphics path if the dest
image has DCC, so this has no effect for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8326>
 2021-01-12 16:03:36 +00:00
Samuel Pitoiset 1f548b7670 radv: decompress DCC for partial resolves using the compute path 
Because DCC is re-initialized to the uncompressed state after the
resolve, so if the app does a partial resolve it should be
decompressed first.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8326>
 2021-01-12 16:03:36 +00:00
Samuel Pitoiset 095a428844 radv: set depth to 1 for subpass resolves using the compute path 
To match Vulkan convention.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8326>
 2021-01-12 16:03:36 +00:00
Rhys Perry 04e3d7ad93 aco: improve nir_op_vec with constant operands 
Could still be improved a little. For example, 8-bit pack without
constants could be:
(s_pack_ll(x, z) & 0x00ff00ff) | ((s_pack_ll(y, w) & 0x00ff00ff) << 8)

fossil-db (Sienna):
Totals from 136 (0.10% of 139391) affected shaders:
CodeSize: 279776 -> 278144 (-0.58%)
Instrs: 50742 -> 50470 (-0.54%)
Cycles: 211560 -> 210472 (-0.51%)
SMEM: 3607 -> 3557 (-1.39%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8421>
 2021-01-12 15:50:54 +00:00
Rhys Perry 255ca7ecda radv: set invariantgeom for Shadow of the Tomb Raider 
Work around flickering foliage on GFX10.3

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4064
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8104>
 2021-01-12 15:11:49 +00:00
Rhys Perry f17de6a803 radv: add RADV_DEBUG=invariantgeom 
This can be used to work around a common class of bugs appearing as
flickering.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8104>
 2021-01-12 15:11:49 +00:00
Samuel Pitoiset c24d6916e6 aco: fix inserting expcnt for MIMG on GFX6 
MIMG VDATA has moved to its own operand.

Fixes: 962c917cea ("aco: move MIMG VDATA to its own operand")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8435>
 2021-01-12 11:32:12 +00:00
Daniel Schürmann bd8e84eb8d nir: replace .lower_sub with .has_fsub and .has_isub 
This allows a more fine-grained control about whether
a backend supports one of these instructions.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6597>
 2021-01-11 19:13:51 +00:00
Samuel Pitoiset d2524ed4a0 radv: mark VK_IMAGE_CREATE_SPARSE_RESIDENCY_BIT as unsupported on GFX6-7 
This is only supported on GFX8+, this fixes a ton of CTS failures
on my Pitcairn (GFX6).

Fixes: af7fb4df50 ("radv: Add sparse image queries.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8415>
 2021-01-11 17:17:42 +00:00
Rhys Perry 4ea0ce2f55 aco: remove can_reorder semantic in get_sync_info_with_hack 
No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8416>
 2021-01-11 16:35:19 +00:00
Rhys Perry f8c7661eca aco: try to better align 8+ dword SGPR vectors 
This doesn't have much of an effect, but it helps avoid a
pathological case for Assassin's Creed Valhalla and a RDR2 shader with a
future change.

fossil-db (Sienna):
Totals from 55074 (39.51% of 139391) affected shaders:
SGPRs: 3515076 -> 3567744 (+1.50%); split: -0.01%, +1.51%
CodeSize: 206942120 -> 206941868 (-0.00%); split: -0.00%, +0.00%
Instrs: 39625900 -> 39625837 (-0.00%); split: -0.00%, +0.00%
Cycles: 1640088780 -> 1640088828 (+0.00%); split: -0.00%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4070
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8416>
 2021-01-11 16:35:19 +00:00
Samuel Pitoiset 7d44ba7217 radv: enable DCC for layered color images on GFX10+ 
There is still some CTS failures on GFX9.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8368>
 2021-01-11 15:42:22 +00:00
Samuel Pitoiset 8754f9e8f9 radv: do not use predication when the range doesn't cover the whole image 
The predication is based on the mip level, so if the image has layers
and DCC is enabled, it should only be used if the range of layers
covers the whole image.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8368>
 2021-01-11 15:42:22 +00:00
Samuel Pitoiset 5420ab9cdf radv: clean up radv_decompress_dcc_compute() 
Remove one old comment because it supports decompressing layers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8368>
 2021-01-11 15:42:22 +00:00
Samuel Pitoiset 5e8f6967b1 radv: add support for fast-clearing DCC layers on GFX9+ 
Layers are contiguous in memory.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8368>
 2021-01-11 15:42:22 +00:00
Samuel Pitoiset 7a3e6f5ac2 ac/surface: initialize dcc_slice_size on GFX9+ 
Will be used by RADV to implement DCC layers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8368>
 2021-01-11 15:42:22 +00:00
Timur Kristóf b75d8052a7 aco: Spill more optimally before loops. 
This further reduces the dead code emitted by the spiller.
Some minimal amount of dead IR is still emitted sometimes,
but that doesn't generate any compiled code at the end.

Totals from 1953 (1.40% of 139391) affected shaders:
VGPRs: 206980 -> 206588 (-0.19%)
SpillSGPRs: 24719 -> 16423 (-33.56%); split: -33.58%, +0.02%
CodeSize: 28448516 -> 28343836 (-0.37%); split: -0.38%, +0.01%
MaxWaves: 8960 -> 8992 (+0.36%)
Instrs: 5422049 -> 5408334 (-0.25%); split: -0.26%, +0.01%
Cycles: 511240864 -> 512460764 (+0.24%); split: -0.02%, +0.26%
VMEM: 346681 -> 346468 (-0.06%); split: +0.27%, -0.33%
SMEM: 124160 -> 122802 (-1.09%); split: +0.33%, -1.42%
VClause: 81102 -> 81163 (+0.08%); split: -0.01%, +0.09%
SClause: 174404 -> 174237 (-0.10%); split: -0.23%, +0.13%
Copies: 530216 -> 532961 (+0.52%); split: -0.90%, +1.42%
Branches: 189114 -> 189221 (+0.06%); split: -0.13%, +0.18%
PreSGPRs: 206017 -> 206526 (+0.25%); split: -0.08%, +0.33%
PreVGPRs: 183103 -> 182964 (-0.08%)

Co-authored-by: Daniel Schürmann <daniel@schuermann.dev>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8026>
 2021-01-11 12:25:29 +00:00
Timur Kristóf b03fbec4f1 aco: Keep live-though variables and constants spilled. 
This noticably reduces the amount of dead code emitted by our
spiller, when eg. previously a constant was spilled then
rematerialized before a loop, but then spilled again inside the loop.

Fossil DB changes on Navi 10:
Totals from 263 (0.19% of 139391) affected shaders:
VGPRs: 30044 -> 30028 (-0.05%)
SpillSGPRs: 8800 -> 4948 (-43.77%)
CodeSize: 4496040 -> 4335448 (-3.57%); split: -3.57%, +0.00%
Instrs: 843942 -> 819219 (-2.93%); split: -2.93%, +0.00%
Cycles: 76485744 -> 73549080 (-3.84%); split: -4.04%, +0.20%
VMEM: 38204 -> 38147 (-0.15%); split: +0.08%, -0.23%
SMEM: 17872 -> 17959 (+0.49%)
SClause: 24298 -> 24012 (-1.18%)
Copies: 98023 -> 82960 (-15.37%); split: -15.38%, +0.01%
Branches: 29074 -> 27632 (-4.96%)
PreVGPRs: 25291 -> 25241 (-0.20%)

Co-authored-by: Daniel Schürmann <daniel@schuermann.dev>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8026>
 2021-01-11 12:25:29 +00:00
Bas Nieuwenhuizen 9f43b44bf0 radv: Enable sparse buffer and image support. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
 2021-01-11 12:01:34 +00:00
Bas Nieuwenhuizen af7fb4df50 radv: Add sparse image queries. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
 2021-01-11 12:01:34 +00:00
Bas Nieuwenhuizen 3ac8804829 radv: Add image sparse memory update implementation. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
 2021-01-11 12:01:34 +00:00
Bas Nieuwenhuizen e553ea51e8 radv: Create sparse images. 
Disable all metadata for now.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
 2021-01-11 12:01:34 +00:00
Bas Nieuwenhuizen d3286bdd76 radv/winsys: Fix offset in range merging. 
If we change the virtual address we also have to change the offset in the buffer
to be mapped.

Fixes: 715df30a4e "radv/amdgpu: Add winsys implementation of virtual buffers."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
 2021-01-11 12:01:34 +00:00
Bas Nieuwenhuizen 2b12e6931e radv/winsys: Fix inequality for sparse buffer remapping. 
Found a case where we mapped a range too many.

Per the comment the constraint is:

	/* [first, last] is exactly the range of ranges that either overlap the
	 * new parent, or are adjacent to it. This corresponds to the bind ranges
	 * that may change.
	 */

So that means that after the ++last we the ranges[last] should still
be adjacent. So we need to test the post-increment value to see whether
it is adjacent.

Failure case:
  ranges:
    0: 0 - ffff
    1: 10000 - 1ffff
    2: 20000 - 2ffff
    3: 30000 - 3ffff
  new range: 10000 - 1ffff

wrong first, last: 0,3
  However range 3 clearly isn't adjacent at all.

Fixes: 715df30a4e "radv/amdgpu: Add winsys implementation of virtual buffers."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
 2021-01-11 12:01:34 +00:00
Bas Nieuwenhuizen f56a28daa4 ac/surf: Use correct tilemodes on GFX8 for PRT. 
Otherwise addrlib will assign the non-PRT tiling indices anyway ...

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
 2021-01-11 12:01:34 +00:00
Bas Nieuwenhuizen 50bafb85ec ac/surf: Add sparse texture info to radeon_surf. 
For GFX9 I didn't reuse the existing mipmap offset/pitch because
last time we did that there was a revert request from Marek.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
 2021-01-11 12:01:34 +00:00
Bas Nieuwenhuizen cd5458f367 ac/surf: Implement PRT layout. 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
 2021-01-11 12:01:34 +00:00
Bas Nieuwenhuizen dea1c06c9b ac/surf: Prepare for 64-bit flags. 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
 2021-01-11 12:01:34 +00:00
Samuel Pitoiset 8914efb5b7 radv: only re-initialize HTILE after ds compute resolves if compressed 
If the current layout isn't compressed we don't have to re-initialize
the HTILE metadata.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8389>
 2021-01-11 11:27:05 +00:00
Samuel Pitoiset 1645d9ebab radv: re-initialize HTILE properly after depth/stencil compute resolves 
This was added to workaround some CTS failures which no longer happen.
Note that radv_clear_htile() will only clear the depth or stencil
bytes of the HTILE buffer based on the aspect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8389>
 2021-01-11 11:27:05 +00:00
Samuel Pitoiset 52b6adfbfb radv: disable TC-compat HTILE in GENERAL for Detroit: Become Human 
The game has invalid usage of render loops and enabling TC-compat
HTILE in GENERAL introduces rendering issues.

Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3063
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8359>
 2021-01-11 11:15:56 +00:00
Samuel Pitoiset 8f9b2afe70 radv: fix crashes when fast-clearing in a secondary command buffer 
iview can be NULL inside a secondary command buffer.

Fixes: 00064713a3 ("radv: determine at creation if an image view can be fast cleared")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8408>
 2021-01-11 11:07:09 +00:00
Pierre-Eric Pelloux-Prayer c4427c2b53 ac/rgp: add missing include 
The build would fail without this include if -std=gnu17 is used.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4057
Fixes: ffdfe136e6 ("ac/sqtt: move rgp/sqtt def to ac")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8376>
 2021-01-11 10:11:09 +00:00
Samuel Pitoiset 6e7008e94b radv: do not predicate FMASK decompression when DCC+MSAA is used 
Even if the FCE predicate is FALSE, we might still need to decompress
FMASK if compressed rendering was used. FMASK decompressions should
never been predicated.

This fixes a ton of CTS failures and a rendering issue with Control
when DCC+MSAA is force-enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8331>
 2021-01-11 09:30:41 +00:00
Samuel Pitoiset 00064713a3 radv: determine at creation if an image view can be fast cleared 
This can be determined earlier than every time a clear is performed
by the driver, it probably saves a bunch of CPU cycles.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8370>
 2021-01-11 08:31:11 +01:00
Mauro Rossi e7444bd3a6 android: ac/radv: fix typo in ac_rgp.h listed in Makefile.sources 
Fixes the following building error:

error: external/mesa/src/amd/Android.mk: libmesa_amd_common: Unused source files: common/ac_rgph.

Fixes: 4ec5cf5318 ("ac/radv: move radv_rgp.c to ac")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8371>
 2021-01-09 11:15:09 +01:00
Rhys Perry f01bca8100 radv/winsys: set has_packed_math_16bit in null winsys 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8392>
 2021-01-08 16:16:19 +00:00
Simon Ser 7ef2046065 radv: only set BO metadata for the first plane 
To properly support multi-planar images, we don't want to set metadata
on anything other than the first plane. To achieve this radv currently
checks for the image TILING and assumes LINEAR means it's not the first
plane.

However this doesn't account for images with a single LINEAR plane. We
still want to set metadata on those, e.g. to properly set the scanout
bit in the tiling flags.

Instead of checking for LINEAR, check if the offset is zero. Only the
first plane has a zero offset on AMD.

This mirrors the radeonsi logic [1].

While at it, move the metadata declaration into the if block.

[1]: https://gitlab.freedesktop.org/mesa/mesa/-/blob/6fecdc6dda6da15d616a31900508214c81cd256e/src/gallium/drivers/radeonsi/si_texture.c#L710

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8086>
 2021-01-08 14:52:18 +00:00
Rhys Perry d95fe8a25e radv: support SpvCapabilitySparseResidency 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
 2021-01-08 14:27:07 +00:00
Rhys Perry 4c67423e99 radv: implement is_sparse_texels_resident and sparse_residency_code_and 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
 2021-01-08 14:27:07 +00:00
Rhys Perry 6d5e26752c ac/nir: implement sparse image/texture loads 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
 2021-01-08 14:27:07 +00:00
Rhys Perry 55aeac7af4 ac/nir: implement nir_op_vec5 
Since sparse fetch/load uses vec5 destinations, it may be possible that we
encounter nir_op_vec5.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
 2021-01-08 14:27:07 +00:00
Rhys Perry a502aa7b04 aco: form sparse load clauses 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
 2021-01-08 14:27:07 +00:00
Rhys Perry 0bd14be962 aco: implement sparse image loads 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
 2021-01-08 14:27:07 +00:00
Rhys Perry 382f50ad2c aco: implement sparse texture fetches 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
 2021-01-08 14:27:07 +00:00
Rhys Perry 5a4f6313b1 aco: implement nir_op_vec5 
Since sparse fetch/load uses vec5 destinations, it may be possible that we
encounter nir_op_vec5.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
 2021-01-08 14:27:07 +00:00
Rhys Perry 962c917cea aco: move MIMG VDATA to its own operand 
We will want both a VDATA operand and a sampler for some TFE/LWE MIMG
instructions.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
 2021-01-08 14:27:07 +00:00