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179254 Commits

Author SHA1 Message Date
Job Noorman 849005a471 ir3: print (sat) modifier of instructions 
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28341>
 2024-08-15 12:07:27 +00:00
Job Noorman cd171964a6 ir3: add debug option to expand rpt instructions 
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28341>
 2024-08-15 12:07:27 +00:00
Job Noorman ef162f9a6f ir3: correctly count vectorized instructions for tex prefetch 
The tex prefetch heuristic simply counts the number of NIR instructions.
Since a vectorized NIR instruction expands to an ir3 instruction per
component, we have to take this into account while counting them.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28341>
 2024-08-15 12:07:27 +00:00
Job Noorman fe09ea29b9 ir3: fix counting of repeated registers 
(r) registers also have their wrmask set so the instruction's rpt field
should not be taken into account.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28341>
 2024-08-15 12:07:27 +00:00
Job Noorman ddb0f5f4e6 ir3: fix wrong dstn used in postsched 
Fixes: 750e6843c0 ("ir3: Rewrite postsched dependency handling")
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28341>
 2024-08-15 12:07:26 +00:00
Job Noorman 28d2a27030 ir3: fix clearing merge sets after shared RA 
After spilling during regular RA, merge sets need to be fixed up. To
find all merge sets, fixup_merge_sets used ra_foreach_dst. However,
after shared RA has run, shared dsts wouldn't have the IR3_REG_SSA flag
set anymore leaving their merge sets lingering. This patch fixes this by
using foreach_dst instead.

Fixes: fa22b0901a ("ir3/ra: Add specialized shared register RA/spilling")
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28341>
 2024-08-15 12:07:26 +00:00
Job Noorman 9013e11d8c ir3: update merge set affinity in shared RA 
The preferred register for merge sets was not updated after allocating
one. This caused a new merge set to be allocated for every register it
contains. This patch fixes this by reusing the update function from the
standard RA.

Fixes: fa22b0901a ("ir3/ra: Add specialized shared register RA/spilling")
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28341>
 2024-08-15 12:07:26 +00:00
Connor Abbott de1d36d054 ci: Uprev VK-CTS to 1.3.9.0 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29766>
 2024-08-15 09:01:26 +00:00
Connor Abbott bc1521e601 ci: Move two failing loader-related tests to all-skips.txt 
There's no value testing these tests in CI until the loader is upgraded,
so don't force every driver to add them to their fails list.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29766>
 2024-08-15 09:01:26 +00:00
Connor Abbott f146c1d562 freedreno/ci: Combine and document failures due to test bug 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29766>
 2024-08-15 09:01:26 +00:00
Pavel Ondračka a1a06f386e r300: fix RGB10_A2 CONSTANT_COLOR blending 
Just reverse the color order the same way we do for RGBA8.

Fixes: 910bac63df
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30656>
 2024-08-15 07:02:44 +00:00
David Rosca 4b60918138 radeonsi: Don't allow DCC for encode in is_video_target_buffer_supported 
This accidentally allowed DCC with format conversion, which is not supported.
Also disable EFC with VCN5 for now.

Fixes: 40c3a53fec ("radeonsi: Implement is_video_target_buffer_supported")
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30562>
 2024-08-15 06:26:16 +00:00
David Rosca 79ce0e3b2f frontends/va: Fix use after free with EFC 
This happens when the source surface is destroyed before being used
in encoding operation. It also needs to disable EFC in this case.

Fixes: a7469a9ffd ("frontends/va: Rework EFC logic")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11653
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30562>
 2024-08-15 06:26:16 +00:00
Caio Oliveira 2150bc6d80 intel/brw: Use %td format for pointer difference 
Fixes build for 32-bit, again.

Fixes: e72bf2d02f ("intel: Add executor tool")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30669>
 2024-08-14 17:28:41 -07:00
Caio Oliveira 8a44b4812a intel/executor: Use PRIx64 to fix building in 32-bit 
Fixes: e72bf2d02f ("intel: Add executor tool")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30668>
 2024-08-14 21:41:28 +00:00
Karol Herbst 5d0c870c00 rusticl/mem: do not check against image base alignment for 1Dbuffer images 
The CL cap in question is only valid for 2D images created from buffer.

Fixes: 20c90fed5a ("rusticl: added")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30655>
 2024-08-14 15:33:01 +00:00
Hans-Kristian Arntzen 5a97916fdc wsi/x11: Bump maximum number of outstanding COMPLETE events. 
Fixes a "regression" where comically large FPS tests regressed.

Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Fixes: 19dba854 ("wsi/x11: Rewrite implementation to always use threads.")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30638>
 2024-08-14 14:00:03 +00:00
David Rosca 214b6c3040 radeonsi/vcn: Only insert headers when requested for H264/5 
Currently sequence headers (VPS, SPS, PPS) are always inserted
on each IDR frame and AUD is inserted on every frame, but this
should be decided by application what headers it wants.
AUD is optional and is almost never needed, in some cases sequence
headers also are not needed each IDR frame and currently this only
wastes bits.
With FFmpeg/GStreamer this changes AUD to not be inserted by default,
there is no change to sequence headers as those are already requested
to be inserted on each IDR.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30585>
 2024-08-14 13:26:03 +00:00
David Rosca c9ccce5271 frontends/omx: Request SPS PPS for IDR pictures 
Also request AUD every frame to match old behavior.

Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30585>
 2024-08-14 13:26:03 +00:00
David Rosca 31f6fe1356 frontends/va: Keep track if VPS/SPS/PPS/AUD was sent 
FFmpeg sends AUD as part of VA_ENC_PACKED_HEADER_SEQUENCE and
VA_ENC_PACKED_HEADER_SLICE.
GStreamer sends it separately as VA_ENC_PACKED_HEADER_RAW_DATA.

It's now also needed to keep track what packed headers were enabled
to include VPS/SPS/PPS with VAEncSequenceParameterBuffer when sequence
packed headers are disabled.

Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30585>
 2024-08-14 13:26:02 +00:00
David Rosca ba1bc7c495 frontends/va: Don't check header type for packed header buffers 
Applications should not send types that were not enabled when creating
config and even if they do it will not cause any unexpected issues.
Remove the checks as it is another place that would need to be
updated when adding support for new packed header types.

Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30585>
 2024-08-14 13:26:02 +00:00
David Rosca f8dcf15ed2 gallium: Add header_flags to pipe_h2645_enc_picture_desc 
Indicates what headers should be inserted.
Move pipe_h265_enc_picture_desc metadata_flags into header_flags

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30585>
 2024-08-14 13:26:02 +00:00
Tapani Pälli a43f18dd04 intel/dev: update mesa_defs.json from workaround database 
Most importantly this enables 18038825448 for LNL.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30639>
 2024-08-14 11:20:40 +00:00
Icenowy Zheng e9fe18727e pvr: emit tpu_tag_cdm_ctrl in compute stream when present 
An extra control register word, tpu_tag_cdm_ctrl, will be present when
TPU_DM_GLOBAL_REGISTERS feature is present.

Emit it when it's needed.

The document of this register is available, however I don't think any of
the bits are needed to be set for our current feature set, so just emit
0 now.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30552>
 2024-08-14 18:07:41 +08:00
Icenowy Zheng 19bf1b661b pvr: add tpu_dm_global_registers feature 
This corresponds to the RGX_FEATURE_TPU_DM_GLOBAL_REGISTERS in the DDK
kernel module source code, and will introduce one more control word to
compute command streams.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30552>
 2024-08-14 18:07:24 +08:00
Icenowy Zheng c6dafb5c1a pvr: enlarge transfer fw_stream buffer for multicore 
The currently allocated transfer fw_stream buffer lacks the space for a
field that exists conditionally for multicore GPUs, frag_screen.

Enlarge the transfer fw_stream buffer for this field.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30543>
 2024-08-14 09:48:38 +00:00
Antonio Ospite 2d2bc5b307 android: simplify building libgallium_dri on Android 
The versioned libgallium library can be confusing on Android, and it is
probably not even needed there, so simplify the build on Android by
always build the unversioned `libgallium_dri.so` overriding the
`-Dunversion-libgallium=true` option added in
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30579

Remove also all the bits that deal with the versioned library which are
not needed anymore.

Fixes: 9568976c52 ("android: fix build in multiple ways")
Acked-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30641>
 2024-08-14 09:11:44 +00:00
Samuel Pitoiset cf0884d161 radv/meta: create DGC prepare pipeline on-demand 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30640>
 2024-08-14 08:48:53 +00:00
Samuel Pitoiset 3a4ce4a5a3 radv/meta: simplify initializing bufimage pipelines 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30640>
 2024-08-14 08:48:53 +00:00
Samuel Pitoiset 586d6cb588 radv/meta: create cleari layouts on-demand 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30640>
 2024-08-14 08:48:53 +00:00
Samuel Pitoiset 1dfb6e19d5 radv/meta: create itoi layouts on-demand 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30640>
 2024-08-14 08:48:53 +00:00
Samuel Pitoiset bd00446bb0 radv/meta: create btoi layouts on-demand 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30640>
 2024-08-14 08:48:53 +00:00
Samuel Pitoiset f1b8e7fa73 radv/meta: create itob layouts on-demand 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30640>
 2024-08-14 08:48:53 +00:00
Samuel Pitoiset db94ee1e64 radv/meta: create blit2d layouts on-demand 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30640>
 2024-08-14 08:48:53 +00:00
Samuel Pitoiset 2352cb2244 radv/meta: remove unused parameter from some blit init functions 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30640>
 2024-08-14 08:48:53 +00:00
Samuel Pitoiset eabbd077cc radv/meta: simplify initializing DCC comp-to-single pipelines 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30640>
 2024-08-14 08:48:53 +00:00
Samuel Pitoiset 9c591d0c27 radv/meta: rework creating blit pipelines 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30640>
 2024-08-14 08:48:53 +00:00
Samuel Pitoiset 978599a052 radv/meta: simplify radv_meta_blit2d_normal_dst() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30640>
 2024-08-14 08:48:52 +00:00
Lucas Stach c90e2bccf7 etnaviv: properly set PIPE_CAP_GRAPHICS 
Only advertise graphics capabilities if the GPU isn't compute only.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30606>
 2024-08-14 08:35:36 +00:00
Lucas Stach 8725ec90a3 etnaviv: hwdb: add COMPUTE_ONLY cap 
Used to tell if the GPU core includes a graphics pipeline.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30606>
 2024-08-14 08:35:36 +00:00
Daniel Schürmann 1d0a12438d aco/cssa: short-cut some trivial case 
If a phi-operand is not flagged as kill, it cannot be coalesced
because it interferes with the live-out variable.
Also do the regClass check earlier.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30182>
 2024-08-14 08:11:48 +00:00
Daniel Schürmann d3e9aef5a2 aco/cssa: update RegisterDemand and validate live variable information 
instead of recomputing it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30182>
 2024-08-14 08:11:48 +00:00
Daniel Schürmann 5a39cbdef6 aco: change signature of get_live_changes() and get_temp_registers() 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30182>
 2024-08-14 08:11:48 +00:00
Daniel Schürmann d494c2a741 aco/cssa: fix kill flags during lowering to CSSA 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30182>
 2024-08-14 08:11:48 +00:00
Daniel Schürmann 541cfb21ba aco: don't attempt to spill dead phis 
These don't affect register pressure.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30182>
 2024-08-14 08:11:48 +00:00
Daniel Schürmann e5d920e0b9 aco/scheduler: enable live variables validation when ACO_DEBUG=validate-livevars is set 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30182>
 2024-08-14 08:11:48 +00:00
Daniel Schürmann b0c8c5e42e aco: implement aco::validate_live_vars() 
This is intended for passes which manually update live variables
and RegisterDemand, like e.g. the scheduler, and can be enabled
with ACO_DEBUG=validate-livevars.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30182>
 2024-08-14 08:11:48 +00:00
Daniel Schürmann c1a3330ac7 aco/reindex_ssa: free memory of previous live variable sets 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30182>
 2024-08-14 08:11:47 +00:00
Samuel Pitoiset d776f3d3f9 radv: allow VK_EXT_vertex_input_dynamic_state with DGC 
It should be supported now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29831>
 2024-08-14 07:47:12 +00:00
Samuel Pitoiset 55b497ef19 radv: add support for dynamic vertex input state with DGC 
DGC preprocessing is disabled for VBOs, so the dynamic vertex input
should always be initialized. Null VBO descriptors are slightly
different when used with dynamic VS inputs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29831>
 2024-08-14 07:47:12 +00:00