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Author SHA1 Message Date
Georg Lehmann 7fa7812219 nir: merge out of loop decision with nir_can_move_instr logic 
One place to modify instead of two when adding new intrinsics here.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30906>
 2024-09-12 21:49:34 +00:00
Georg Lehmann 91f8e32a85 nir/opt_sink: do not sink inverse_ballot out of loops 
Inverse_ballot result is undefined if the input is not dynamically uniform.
And sinking out of loops might make the input divergent.

Fixes: 18a0ff137f ("nir: sink/move inverse_ballot like moves")

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30906>
 2024-09-12 21:49:34 +00:00
Georg Lehmann 1ec3cc2aed nir/opt_sink: do not sink load_ubo_vec4 out of loops 
Same reason as for load_ubo.

Fixes: d199d65c3a ("nir/nir_opt_move,sink: Include load_ubo_vec4 as a load_ubo instr.")

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30906>
 2024-09-12 21:49:34 +00:00
Caio Oliveira 1e7f1c2039 nir: Allow Mesh/Task to use implicit LOD when DERIVATIVE_GROUP is set 
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30956>
 2024-09-10 18:22:42 +00:00
David Heidelberg 6bf7b5bcd8 nir_lower_mem_access_bit_sizes: Assert when 0 components or bits are requested 
Prevent the accidental passing of 0 components or bits, as it makes no sense.

Cc: mesa-stable
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Suggested-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31103>
 2024-09-10 11:17:48 +00:00
Ian Romanick a780305818 nir/algebraic: Optimize more comparisons with b2f 
shader-db:

All Intel platforms had similar results. (Meteor Lake shown)
total instructions in shared programs: 19781108 -> 19772614 (-0.04%)
instructions in affected programs: 372638 -> 364144 (-2.28%)
helped: 2915 / HURT: 0

total cycles in shared programs: 905907644 -> 905822682 (<.01%)
cycles in affected programs: 5573453 -> 5488491 (-1.52%)
helped: 2363 / HURT: 234

LOST:   42
GAINED: 16

fossil-db:

All Intel platforms had similar results. (Meteor Lake shown)
Totals:
Instrs: 152519634 -> 152519610 (-0.00%)
Cycle count: 17122707642 -> 17122710974 (+0.00%); split: -0.00%, +0.00%

Totals from 5 (0.00% of 633222) affected shaders:
Instrs: 2827 -> 2803 (-0.85%)
Cycle count: 83089 -> 86421 (+4.01%); split: -0.12%, +4.13%

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31068>
 2024-09-10 04:15:58 +00:00
Alyssa Rosenzweig b7542c4390 nir: CSE comparisons in atan2 
Same code generated on AGX but simplified NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 7546ae96a7 nir: drop NaN fixup for atan 
this existed due to the min/max, per the comment. now that we don't do min/max,
the whole routine is NaN correct so the fixup is pointless.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Suggested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig ab8547a002 nir: push up abs in atan2 calculation 
everybody has abs on fmul, not everyone has abs on bcsel. should help agx and
bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 398e1ad46c nir: fuse ffma for atan range fixup 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 47e7cd268c nir: negate an expression in atan 
we're going to fix up the sign immediately anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 5318b8868b nir: simplify atan range reduction fixup 
the original version sure is creative.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 87b99d5797 nir: use copysign for atan 
this does two things:

* ignores sign of negative numbers which let us play fast and loose later in th
  series
* avoids an expensive fsign instruction in favour of a cheap bitwise op

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 95215a094a nir: extend copysign for no-integer hw 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 0a4a0df283 nir: push down fabs for atan 
worse in terms of NIR instruction count but lets the fabs fold easier. (on agx,
which has fabs on comparisons and fmul but not on bcsel. should be no worse if
ISA has fabs on all 3.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 8579375777 nir: simplify atan range reduction 
just implement what the comment says, don't be clever. the clever thing is worse
on all architectures i'm familiar with, because the fdiv will turn into
fmul+frcp.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig a32b1a975d nir: correct comment for atan range reduction 
the code did not match the comment, blew a sign.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Alyssa Rosenzweig 4fc3e34f2f nir: use Horner's method for atan 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30934>
 2024-09-07 00:54:35 +00:00
Georg Lehmann 6378bbaa82 nir/opt_algebraic: reassociate constants in ior(iand) chains 
Mostly affects one F1_23 shader that packs bitfields bit by bit.

Totals from 3 (0.00% of 79395) affected shaders:
Instrs: 5004 -> 4202 (-16.03%)
CodeSize: 30992 -> 23952 (-22.72%)
Latency: 28894 -> 28464 (-1.49%)
InvThroughput: 4095 -> 3934 (-3.93%)
Copies: 363 -> 376 (+3.58%)
PreVGPRs: 110 -> 109 (-0.91%)
VALU: 3035 -> 2504 (-17.50%)
SALU: 463 -> 459 (-0.86%)

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31009>
 2024-09-05 22:04:05 +00:00
Caio Oliveira 74be809237 compiler: Allow derivative_group to be used for all stages in shader_info 
These will now also be used by stages that have workgroups.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30950>
 2024-09-03 20:03:18 +00:00
Alyssa Rosenzweig f977c52b84 ail: swallow up formats 
ail is a more sensible place for the format tables to live. this does create a
bit of dependency soup but hey.

nfc

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30981>
 2024-09-02 23:27:14 +00:00
Alyssa Rosenzweig afc7557cb6 nir,agx: make block image store an image() intrinsic 
so we can do a bindless version

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30981>
 2024-09-02 23:27:14 +00:00
Alyssa Rosenzweig 4941d71846 nir/divergence_analysis: handle load_agx 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30981>
 2024-09-02 23:27:14 +00:00
Qiang Yu d43c5003fc nir: add skip_lower_packing_ops shader compile option 
Drivers like radeonsi and radv prefer to not lowering
some packing ops.

Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30885>
 2024-08-30 05:46:51 +00:00
Ian Romanick c160ed212e nir/divergence: resource_intel is less divergent than you thought 
When the non_uniform flag is not set, the result is never divergent.

v2: Remove redundant assignment to is_divergent. Suggested by Caio.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30251>
 2024-08-30 03:39:30 +00:00
Ian Romanick f11a414645 nir/algebraic: Remove incorrect bfi of iand pattern 
The comment says, "This expands to (b & 3) & ~0xc which is (b & 3) &
3." This is not correct. ~0xc is actually 0xfffffff3.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Closes: #11695
Fixes: 1c7e35d4e0 ("nir/algebraic: Optimize some bit operation nonsense observed in some shaders")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30913>
 2024-08-29 22:21:55 +00:00
Timothy Arceri bb426b7f3c nir/tests: add basic terminator merge test 
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30862>
 2024-08-29 10:26:30 +00:00
Timothy Arceri 85741c6a15 nir/tests: make add_loop_terminators more flexible 
Here we update the helper to have an option to add the break to the else
blocks of the terminators.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30862>
 2024-08-29 10:26:30 +00:00
Daniel Schürmann 51bb0e68b3 nir/opt_if: merge IFs which have phis between them 
The phi-uses are rewritten on each side of the following if-stmt,
so that register pressure is kept the same.

Totals from 719 (0.91% of 79395) affected shaders: (Navi31)
MaxWaves: 18531 -> 18527 (-0.02%); split: +0.02%, -0.04%
Instrs: 4683616 -> 4621920 (-1.32%); split: -1.32%, +0.00%
CodeSize: 24154608 -> 23811472 (-1.42%); split: -1.42%, +0.00%
VGPRs: 46020 -> 46140 (+0.26%); split: -0.05%, +0.31%
SpillSGPRs: 1134 -> 1107 (-2.38%)
SpillVGPRs: 2221 -> 2202 (-0.86%)
Scratch: 603648 -> 602624 (-0.17%)
Latency: 30355976 -> 29516199 (-2.77%); split: -2.77%, +0.01%
InvThroughput: 7017283 -> 6878583 (-1.98%); split: -2.00%, +0.03%
VClause: 119826 -> 113392 (-5.37%); split: -5.37%, +0.00%
SClause: 100380 -> 93516 (-6.84%); split: -6.85%, +0.01%
Copies: 360589 -> 359154 (-0.40%); split: -1.13%, +0.73%
Branches: 146438 -> 138623 (-5.34%); split: -5.37%, +0.03%
PreSGPRs: 38237 -> 38317 (+0.21%); split: -0.52%, +0.72%
PreVGPRs: 37745 -> 37742 (-0.01%); split: -0.05%, +0.04%
VALU: 2594909 -> 2593667 (-0.05%); split: -0.12%, +0.07%
SALU: 572636 -> 554587 (-3.15%); split: -3.19%, +0.04%
VMEM: 203188 -> 201030 (-1.06%)
SMEM: 135731 -> 128683 (-5.19%)
VOPD: 1978 -> 1982 (+0.20%)

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7710>
 2024-08-29 09:42:55 +00:00
Daniel Schürmann 37881801c1 nir/opt_if: optimize phis between similar IFs 
This small optimization targets phis between two IF statements with
the same condition. If the phi dst is only used on one branch leg,
the 'unused' phi source gets replaced with undef.

Totals from 1773 (2.23% of 79395) affected shaders: (Navi31)
Instrs: 6546338 -> 6539039 (-0.11%); split: -0.11%, +0.00%
CodeSize: 34819124 -> 34780660 (-0.11%); split: -0.11%, +0.00%
VGPRs: 92100 -> 92052 (-0.05%); split: -0.07%, +0.01%
SpillVGPRs: 2211 -> 2206 (-0.23%)
Latency: 51621404 -> 51620966 (-0.00%); split: -0.03%, +0.03%
InvThroughput: 7907110 -> 7905382 (-0.02%); split: -0.05%, +0.03%
VClause: 159268 -> 159273 (+0.00%); split: -0.00%, +0.01%
SClause: 180166 -> 180155 (-0.01%)
Copies: 559867 -> 553966 (-1.05%); split: -1.07%, +0.01%
Branches: 237327 -> 236366 (-0.40%); split: -0.41%, +0.00%
PreSGPRs: 81128 -> 81116 (-0.01%); split: -0.02%, +0.01%
PreVGPRs: 74264 -> 74245 (-0.03%)
VALU: 3547408 -> 3541257 (-0.17%); split: -0.18%, +0.00%
SALU: 824426 -> 824104 (-0.04%); split: -0.04%, +0.00%
VMEM: 265009 -> 265003 (-0.00%)
SMEM: 235766 -> 235760 (-0.00%)
VOPD: 1853 -> 1839 (-0.76%)

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7710>
 2024-08-29 09:42:55 +00:00
Daniel Schürmann 50d416fe89 nir: add nir_block *nir_src_get_block(src) helper 
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7710>
 2024-08-29 09:42:55 +00:00
Konstantin Seurer 0fc3c52e43 nir/opt_loop: Fix handling else-breaks in merge_terminators 
If both breaks are in the else branch, we have to use iand.

Fixes: 9995f33 ("nir: add merge loop terminators optimisation")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11726
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30850>
 2024-08-29 05:49:35 +00:00
Faith Ekstrand 518b2d548f nir: Preserve fp_fast_math in nir_opt_vectorize() 
Fixes the following CTS tests on NVK:

dEQP-VK.spirv_assembly.instruction.*.float_controls.fp16.generated_args.signed_zero_sub_var_preserve*

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30859>
 2024-08-28 12:29:06 +00:00
Georg Lehmann ef970c5a9d nir: optimize pack_uint_2x16 of pack_half(a, 0) 
Foz-DB Navi31:
Totals from 31 (0.04% of 79395) affected shaders:
Instrs: 6157 -> 6065 (-1.49%)
CodeSize: 35676 -> 34936 (-2.07%)
Latency: 23979 -> 23805 (-0.73%); split: -0.79%, +0.07%
InvThroughput: 5248 -> 5124 (-2.36%)
VALU: 3224 -> 3162 (-1.92%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30855>
 2024-08-28 07:16:55 +00:00
Karol Herbst fc88f04ba1 vtn, nir: handle OpImageQueryLevels on images 
This is needed for cl_khr_mipmap_image, specifically the OpenCL C
function get_image_num_mip_levels.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30834>
 2024-08-27 15:06:17 +00:00
Karol Herbst 260a50add5 nir: Support multisampled images in lower_read_only_images_to_tex() 
This is needed for cl_khr_gl_msaa_sharing

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30834>
 2024-08-27 15:06:16 +00:00
Lionel Landwerlin 2158fe2ae2 nir/divergence: add missing load_constant_base_ptr 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30712>
 2024-08-27 01:33:52 +00:00
Konstantin Seurer 81e3930ec0 nir/print: Add a helper for generating debug info 
Prints the shader to a string and assigns source locations based on
that.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18903>
 2024-08-25 10:26:33 +00:00
Konstantin Seurer ce24486ee4 nir: Introduce nir_debug_info_instr 
Adds a new instruction type that stores metadata that might be useful
for debugging purposes. Passes must ignore these instructions when
making decisions.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18903>
 2024-08-25 10:26:33 +00:00
Lionel Landwerlin cf986dd589 nir: remove unused intel intrinsics 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30713>
 2024-08-22 19:44:40 +00:00
Boris Brezillon ff2ebdc4d6 nir/format_convert: Promote input to 32-bit before packing integers 
If we don't do that and the source is not 32-bit we end up with a
bit_size mismatch when doing the ior operation.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29333>
 2024-08-20 15:11:14 +00:00
Timothy Arceri d681cf96fb nir/glsl: set deref cast mode during function inlining 
See code comment for details.

Issue: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11535
Fixes: c6c150b4cd ("glsl_to_nir: support conversion of opaque function params")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30338>
 2024-08-19 23:54:49 +00:00
Rob Clark 563ec4754a nir/opt_loop: Don't peel initial break if loop ends in break 
A loop that looks like:

   loop {
      do_work_1();
      if (cond) {
         break;
      } else {
      }
      do_work_2();
      break;
   }

We can't pull that break ahead of do_work_1() after hoisting the initial
do_work_1() out of the loop.  So bail in this case.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11711
Fixes: 6b4b044739 ("nir/opt_loop: add loop peeling optimization")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30702>
 2024-08-17 14:27:02 +00:00
Ian Romanick 198d8d9c03 nir/algebraic: Improve some find_lsb and ifind_msb patterns 
These patterns were observed in shaders from parallel-rdp.

No shader-db changes on any Intel platform.

fossil-db:

Meteor Lake, DG2, Ice Lake had Skylake similar results. (Meteor Lake shown)
Totals:
Instrs: 152535883 -> 152535673 (-0.00%); split: -0.00%, +0.00%
Cycle count: 17112406110 -> 17122827810 (+0.06%); split: -0.01%, +0.07%
Spill count: 78525 -> 78523 (-0.00%)
Fill count: 148132 -> 148127 (-0.00%); split: -0.01%, +0.00%
Max live registers: 31855320 -> 31855314 (-0.00%)

Totals from 206 (0.03% of 633223) affected shaders:
Instrs: 797124 -> 796914 (-0.03%); split: -0.03%, +0.00%
Cycle count: 4716743323 -> 4727165023 (+0.22%); split: -0.05%, +0.27%
Spill count: 18781 -> 18779 (-0.01%)
Fill count: 31381 -> 31376 (-0.02%); split: -0.03%, +0.01%
Max live registers: 31872 -> 31866 (-0.02%)

Tiger Lake
Totals:
Instrs: 150560465 -> 150560343 (-0.00%); split: -0.00%, +0.00%
Cycle count: 15482372893 -> 15479328542 (-0.02%); split: -0.02%, +0.00%
Fill count: 103509 -> 103512 (+0.00%)
Max live registers: 31760378 -> 31760374 (-0.00%)

Totals from 199 (0.03% of 632445) affected shaders:
Instrs: 679513 -> 679391 (-0.02%); split: -0.02%, +0.00%
Cycle count: 4258406125 -> 4255361774 (-0.07%); split: -0.09%, +0.02%
Fill count: 30609 -> 30612 (+0.01%)
Max live registers: 30502 -> 30498 (-0.01%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30650>
 2024-08-16 14:52:04 +00:00
Lionel Landwerlin fbafa9cabd intel/nir: remove load_global_const_block_intel intrinsic 
load_global_constant_uniform_block_intel is equivalent in terms of
loading, then for the predicate we just do a bcsel afterward in places
where that is required.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30659>
 2024-08-16 11:12:39 +00:00
Timothy Arceri 08b93c841a nir: make static assert more flexible 
The static assert used in encode deref modes used the fact there was
less than 16 modes that we wanted to compress as an opportunity to reuse
MODE_ENC_GENERIC_BIT as it just happened to represent 16. However if we
add more than 16 modes i.e need to compress to 6 bits not 5 bits then
MODE_ENC_GENERIC_BIT becomes 32 and the logic in the assert breaks.

Instead we more precisely make sure MODE_ENC_GENERIC_BIT is large
enough to fit all but the last 4 generic modes and that the last 4 modes
defined in the enum are in fact the 4 generic modes.

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30654>
 2024-08-15 23:02:20 +00:00
Matt Turner c437f2e79c nir/tests: Add tests for opt_if_merge 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30629>
 2024-08-15 20:34:54 +00:00
Matt Turner d2e6be94ae nir: Skip opt_if_merge when next_if has block ending in a jump 
Similar to commit 6cef804067 ("nir/opt_if: fix opt_if_merge when
destination branch has a jump"), we shouldn't combine if statements when
the second if-then-else has a block that ends in a jump.

This fixes a case where opt_if_merge combines

    if (cond) {
        [then-block-1]
    } else {
        [else-block-1]
    }

    if (cond) {
        [then-block-2]
    } else {
        [else-block-2]
    }

where `then-block-2` or `else-block-2` ends in a jump. The phi nodes
following the control flow will be incorrectly updated to have an input
from a block that is not a predecessor.

Fixes: 4d3f6cb973 ("nir: merge some basic consecutive ifs")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30629>
 2024-08-15 20:34:54 +00:00
Job Noorman 9998b65695 nir/load_store_vectorize: add load/store_const_ir3 
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28341>
 2024-08-15 12:07:27 +00:00
Job Noorman db2859cb7f nir/load_store_vectorize: support stores without wrmask 
Some store intrinsics (e.g., store_const_ir3) don't have a wrmask so
don't assume it always exists.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28341>
 2024-08-15 12:07:27 +00:00