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Author SHA1 Message Date
Jordan Justen b602c14fc5 intel/devinfo: Define PAT indices used on MTL 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878>
 2023-06-27 22:06:19 +00:00
Jordan Justen e896b81322 intel/devinfo: Add has_set_pat_uapi 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878>
 2023-06-27 22:06:19 +00:00
Tapani Pälli 15433897b2 intel/dev: add parentheses around intel_needs_workaround macro 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23596>
 2023-06-13 13:27:30 +00:00
Tapani Pälli abcef5a476 intel/dev: provide helper to check if devinfo is ATS-M 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20784>
 2023-05-24 04:42:59 +00:00
Mark Janes 8eceff48cd intel/dev: use GFX_VERx10 to detect genX compilation 
Depending on the ordering of includes, GFX_VER may not defined for
intel_device_info.h.  The failure mode of this case is silent:
BITSET_TEST will be called when it could be compiled out.

GFX_VERx10 should be used in place of GFX_VER.  GFX_VERx10 is defined
by a compiler flag, and is always present for genX compilation units.

Fixes: 3c9a8f7a6d ("intel/dev: generate helpers to identify platform workarounds")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21908>
 2023-03-23 23:23:52 +00:00
Mark Janes 52c71cf959 intel/dev: fix macro string concatenation for INTEL_WA_{id}_GFX_VER 
`INTEL_WA_##id_GFX_VER` evaluates to `INTEL_WA_id_GFX_VER`
instead of numbered identifiers like `INTEL_WA_220579888_GFX_VER`.

Fixes: 3c9a8f7a6d ("intel/dev: generate helpers to identify platform workarounds")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21908>
 2023-03-23 23:23:52 +00:00
José Roberto de Souza 2ab3d5f436 intel: Move memory aligment information to intel_device_info 
This same information is also used in ANV, so intel_device_info is
a better place to have it.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21972>
 2023-03-20 17:18:03 +00:00
Mark Janes 3c9a8f7a6d intel/dev: generate helpers to identify platform workarounds 
Workarounds for defects in Intel silicon have been manually
implemented:

 - consult defect database for the current platform

 - add workaround code behind platform ifdef or devinfo->ver checks

Some bugs have occurred due to the manual process.  Typical failure
modes:

 - defect database is updated after a platform is enabled

 - version checks are overly broad (eg gfx11+) for defects that were
   fixed (eg in gfx12)

 - version checks are too narrow for defects that were extended to
   subsequent platforms.

 - missed workarounds

This commit automates workaround handling:

 - Internal automation queries the defect database to collate and
   summarize defect documentation in json.

 - mesa_defs.json describes all public defects and impacted platforms.
   Defects which are extended to subsequent platforms are listed under
   the original defect.

 - gen_wa_helpers.py generates workaround helpers to be called
   in place of version checks:

   - NEEDS_WORKAROUND_{ID} provides a compile time check suitable for
     use in genX routines.

   - intel_device_info_needs_wa() provides a more precise runtime
     check, differentiating platforms within a generation and
     platform steppings.

Internal automation will generate new mesa_defs.json as needed.
Workarounds enabled with these helpers will apply correctly based on
updated information in Intel's defect database.

Reviewed-by: Dylan Baker <dylan@pnwbakers>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20825>
 2023-03-02 00:01:27 +00:00
Marcin Ślusarz e74a3284f5 anv: halve the push constants space in mesh pipelines 
It's only used by fragment shaders, so halving it matches the size
used in the most optimal primitive pipeline (VS + FS).

This change frees some URB space for mesh and task shaders and as
a result improves vk_meshlet_cadscene performance by up to 2%,
depending on the model.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21559>
 2023-02-28 20:18:01 +00:00
José Roberto de Souza a364f23a6c intel: Make gen12 URB space reservation dependent on compute engine presence 
Tigerlake PRM: Volume 2c: Command Reference: Registers Part 2 - Registers M through Z
RCU_MODE :: Compute Engine Enable

   This bit indicates if Compute Engine (a.k.a Dual Context or Multi
   Context) is enabled or not. This bit must be treated as global
   control for enabling and disabling of compute engine. Hardware
   allocates required resources for the compute engine based on this
   bit.
   ....
   HW reserves 4KB of URB space...

Right now no gen12 platform has Dual Context enabled in kernel side,
exposing a compute engine but that can change, so here adding
has_compute_engine to intel_device_info and only reserving URB space
if compute engine is available.

While at it also fixing the error path when pb_slabs_init() fails.

Bspec: 46034
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21031>
 2023-02-23 14:27:30 +00:00
José Roberto de Souza 9fc224631c intel: Add intel_memory_class_instance 
This is a KMD independent struct to hold memory class and instance
values.

drm_i915_gem_memory_class_instance usage will be gradually replaced.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20948>
 2023-02-09 02:57:32 +00:00
José Roberto de Souza 2c42641994 intel/dev: Detect what is the kernel mode driver loaded 
Intel GPUs will have a new kernel mode driver, support for some
platforms will overlap so we will need to detect in runtime what is
the kernel mode driver loaded for each device.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20773>
 2023-01-25 09:16:55 -08:00
José Roberto de Souza c1d99283e6 intel/dev: Split hwconfig i915 specific code 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20437>
 2023-01-20 17:26:08 +00:00
José Roberto de Souza 1332702cf4 intel/dev: Export functions that will be used by different kernel drivers 
No behavior changes here.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20437>
 2023-01-20 17:26:08 +00:00
Paulo Zanoni a099d6ae4d intel: add devinfo->has_64bit_float_via_math_pipe 
Unusual hardware features that require special hanlding usually get a
devinfo field, so do this for MTL's unordered DF types. This will
guarantee that any platform based on MTL (thus inheriting from
MTL_FEATURES) will automatically be handled in these special cases.

v2: s/has_unordered_64bit_float/has_64bit_float_via_math_pipe/ (Curro).

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20072>
 2022-12-10 03:59:19 +00:00
Nanley Chery 822687f4c0 intel/dev: Add a has_illegal_ccs_values flag 
Whether or not CCS can be used without initialization depends on the
platform:

- On gfx7-8, each CCS element is 1-bit and encodes "fast-cleared" or
  "pass-through". So, those platforms have no illegal values.

- On gfx9-11, each CCS element is 2-bits and some bit combinations
  are invalid.

- On gfx12+, each CCS element is 4-bits but they have no truly illegal
  values. Unused encodings are interpreted as "pass-through".

Refer to the "MCS/CCS Buffers for Render Target(s)" sections of the
PRMs for more info.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20118>
 2022-12-06 00:49:17 +00:00
Jordan Justen ed84f163ff intel/dev: Add devinfo::has_caching_uapi (and disable for dg1 and dg2+) 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19911>
 2022-11-28 21:54:20 +00:00
José Roberto de Souza 29550bc50a intel: Add has_context_isolation to intel_device_info 
Iris, hasvk and anv were fetching the same information, better do it
on one place.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19425>
 2022-11-07 17:22:14 +00:00
José Roberto de Souza d5d1331381 intel: Add has_userptr_probe to intel_device_info 
Iris, hasvk and anv were fetching the same information, better do it
on one place.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19425>
 2022-11-07 17:22:14 +00:00
José Roberto de Souza e9eceb1106 intel: Add has_mmap_offset to intel_device_info 
All 4 drivers were fetching the same information, better do it on one
place.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19425>
 2022-11-07 17:22:14 +00:00
José Roberto de Souza 5269d91efc intel: Convert missing i915 engine types to intel 
This convertions were missed due to bad rebased in my end, sorry.

Fixes: 03b959286e ("intel: Make engine related functions and types not i915 dependent")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18975>
 2022-10-15 20:04:51 +00:00
Lionel Landwerlin c6a7f4b34e intel/devinfo: Rename & implement num_dual_subslices 
v2: Use the upper bound of dual subslices as the ID is not remapped
with fused off parts and this is what we'll use for a bunch of
computation in RT.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:36 +00:00
José Roberto de Souza 89d2cdad37 intel/dev: Adjust prefetch_size values for MTL engines 
MTL has different CS prefetch sizes for each CS type.
So here replacing the cs_prefetch_size in intel_device_info struct
by a function that takes as argument the i915 engine class.

Fixes:
- func.cmd-buffer.small-secondaries.q0
- dEQP-VK.multiview.secondary_cmd_buffer.*
- Several other VK CTS tests that uses secondary_cmd_buffer

v2:
- renamed to intel_device_info_get_engine_prefetch() (Jordan)

v3:
- renamed to intel_device_info_calc_engine_prefetch()
- store each engine class prefetch in intel_device_info

BSpec: 45718
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18597>
 2022-09-22 02:14:47 +00:00
Jordan Justen 582bad0256 intel/devinfo: Add MTL platforms enums and intel_device_info_is_mtl() 
Ref: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/drm/i915_pciids.h?h=v6.0-rc4#n736
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18482>
 2022-09-13 00:30:22 +00:00
Jordan Justen 7bd3a6b757 intel/dev: Add intel_vram_all_mappable() 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17349>
 2022-07-21 20:27:10 +00:00
Jordan Justen d2829ffe4e intel/dev: Add vram.unmappable.size region info 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17349>
 2022-07-21 20:27:10 +00:00
Marcin Ślusarz f4386b81e6 intel: fix typos found by codespell 
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17191>
 2022-06-27 10:20:55 +00:00
Lionel Landwerlin 4e727297e8 intel/dev: add a helper to update memory info 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17075>
 2022-06-22 00:30:49 +00:00
Jordan Justen 4aecfbf0f4 intel/dev: Add devinfo::mem to store i915 regions information 
Reworks:
 * Lionel: Change check on memory region valid to vram size
 * Jordan: Drop regions.valid (Lionel implemented a fallback)
 * Jordan: Rename devinfo::regions to devinfo::mem.
 * Jordan: Add devinfo::mem::use_class_instance
 * Add mesa_logw for lmem requiring regions. (s-b Lionel)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17075>
 2022-06-22 00:30:49 +00:00
Jordan Justen 4456209ce5 intel/dev: Add INTEL_PLATFORM_DG2_G12 
Cc: 22.1 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16449>
 2022-05-12 03:03:57 -07:00
Lionel Landwerlin 5d3e419378 anv: enable ray queries 
Only on platforms that support it.

v3: Split out code setting up ray query shadow buffer (Caio)
    Don't forget to setup ray query globals even when no shadow buffer
    is used (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
 2022-02-08 12:55:25 +00:00
Lionel Landwerlin 8d90fe587f intel/dev: details CPS feature support 
DG2 introduces per primitive coarse pixel settings (in stages
preceding the PS shader) and also a control surface specifying the
rate at through the resulting surface.

v2: update comment (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Jordan Justen 4e0eca7dc3 intel/dev: Add device info for RPL 
Ref: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=52407c220c44c8dcc6aa8aa35ffc8a2db3c849a9
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14664>
 2022-01-25 12:47:44 +00:00
Kenneth Graunke 5262475242 intel/dev: Add a has_flat_ccs flag 
This should only be set on XeHP.  It implies that CCS works via based on
the virtual addresses involved and a flat memory carve-out, rather than
treating CCS like a surface, or using auxiliary maps.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687>
 2022-01-24 23:27:25 +00:00
Jordan Justen a15f18c886 intel/dev: Add intel_device_info::apply_hwconfig 
This will be used to conditionally use hwconfig values to update
intel_device_info at runtime.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13866>
 2022-01-19 00:29:35 +00:00
Jordan Justen 08a897fa38 intel/dev: Add max_threads_per_psd field to devinfo for gfx8+ 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13866>
 2022-01-19 00:29:35 +00:00
Lionel Landwerlin d3724de894 intel/dev,perf: Use a single timescale function 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13996>
 2022-01-14 20:17:44 +00:00
Jianxun Zhang f43c7185e0 intel: remove chipset_id 
The chipset_id should be named after i915 ioctl that's called
to get the device id. In user space this field holds pci device
id in reality. We now have a pci_device_id queried from drm
instead using the ioctl, so there is no much reason to keep
the chipset_id for the same purpose.

Signed-off-by: Jianxun Zhang <jianxun.zhang@linux.intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13936>
 2022-01-13 03:09:36 +00:00
Jianxun Zhang db8405670a intel: provide pci bus and dev info in base device struct 
Having PCI bus and dev info in the base struct
'intel_device_info' enables us to utilize the info across
multiple drivers for several purposes, such as computing
device uuids in a multi-gpu system.

Signed-off-by: Jianxun Zhang <jianxun.zhang@linux.intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13936>
 2022-01-13 03:09:36 +00:00
Lionel Landwerlin 8ef9350ff0 intel/devinfo: drop num_eus_per_subslice field 
This field is an average computation that is not actually useful for
any of our driver code.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14510>
 2022-01-12 12:53:21 +00:00
Lionel Landwerlin 5d5a1b660b intel/devinfo: add a helper to check for slice availability 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14510>
 2022-01-12 12:53:21 +00:00
Francisco Jerez e48c29acca intel/dev: Add support for pixel pipe subslice accounting on multi-slice GPUs. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14436>
 2022-01-07 07:58:27 +00:00
Francisco Jerez f3274e94fd intel/dev: Fix size of device info num_subslices array. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14436>
 2022-01-07 07:58:27 +00:00
Lionel Landwerlin eca7b24e74 intel/devinfo: adjust subslice array size 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14324>
 2021-12-28 14:22:53 -08:00
Jason Ekstrand 88e97d75d0 intel/dev: Add gtt_size to devinfo 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13647>
 2021-12-11 05:05:19 +00:00
Jordan Justen 29c2f32a57 intel/dev: Add platform enum with DG2 G10 & G11 
Based on Lionel's "intel/devinfo: store the different kind of DG2".

Ref: 361b3fee3c ("intel: move away from booleans to identify platforms")
Ref: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9e22cfc5e9b92556a56d8a564cdab31045f29010
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13797>
 2021-11-15 21:39:27 +00:00
Jason Ekstrand 0b2b9b49af anv: Pull aperture size from devinfo 
Reviwed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13610>
 2021-11-09 02:48:24 +00:00
Lionel Landwerlin 361b3fee3c intel: move away from booleans to identify platforms 
v2: Drop changes around GFX_VERx10 == 75 (Luis)

v3: Replace
   (GFX_VERx10 < 75 && devinfo->platform != INTEL_PLATFORM_BYT)
   by
   (devinfo->platform == INTEL_PLATFORM_IVB)
   Replace
   (devinfo->ver >= 5 || devinfo->platform == INTEL_PLATFORM_G4X)
   by
   (devinfo->verx10 >= 45)
   Replace
   (devinfo->platform != INTEL_PLATFORM_G4X)
   by
   (devinfo->verx10 != 45)

v4: Fix crocus typo

v5: Rebase

v6: Add GFX3, ILK & I965 platforms (Jordan)
    Move ifdef to code expressions (Jordan)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12981>
 2021-11-08 16:48:06 +00:00
Lionel Landwerlin 718c97d525 intel/devinfo: use compatible type for ARRAY_SIZE 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10015>
 2021-11-05 10:22:18 +00:00
Lionel Landwerlin a543a94404 intel/dev: fix subslice/eu total computations with some fused configurations 
When a device has its first slice/subslice fused off, we can't use the
number of slices/subslices to iterate the mask array.

v2: Fix spelling (Marcin)
    Use size_t for iterator (Marcin)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reported-by: Matt Roper <matthew.d.roper@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5601
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10015>
 2021-11-05 10:22:18 +00:00