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175210 Commits

Author SHA1 Message Date
Faith Ekstrand
6cd58de4eb nouveau/winsys: Make BO_LOCAL and BO_GART separate flags 
It's sometimes useful to specify both to allow migration.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24795>
 2024-05-14 04:04:34 +00:00
Faith Ekstrand
19b143b7bc nouveau/winsys: Take a reference to BOs found in the cache 
Fixes: c370260a8f ("nouveau/winsys: Add dma-buf import support")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24795>
 2024-05-14 04:04:33 +00:00
Faith Ekstrand
d63f015d0b nvk: Improve the GetMemoryFdKHR error 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24795>
 2024-05-14 04:04:33 +00:00
Faith Ekstrand
756cbb41a2 nvk: Use the upload queue for NVK_DEBUG=zero_memory 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10800
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29183>
 2024-05-14 03:40:24 +00:00
Faith Ekstrand
22e44d54fd nvk/upload_queue: Add a _fill method 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29183>
 2024-05-14 03:40:24 +00:00
Faith Ekstrand
3132a49eb0 nvk/upload_queue: Add some useful asserts 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29183>
 2024-05-14 03:40:24 +00:00
Faith Ekstrand
9b098209b9 nvk/upload_queue: Only upload one line of data 
This only doesn't blow up beause we set multi_line_enable = FALSE.

Fixes: 2074e28a0d ("nvk: Add an upload queue")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29183>
 2024-05-14 03:40:24 +00:00
Mike Blumenkrantz
ac78076cd2 zink: hook up VK_EXT_legacy_vertex_attributes 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29069>
 2024-05-14 03:11:22 +00:00
Ian Romanick
97e3c6a12a intel/brw: Use range analysis to optimize fsign 
shader-db:

Meteor Lake, DG2, and Tiger Lake had similar results. (Meteor Lake shown)
total instructions in shared programs: 19674784 -> 19665960 (-0.04%)
instructions in affected programs: 933425 -> 924601 (-0.95%)
helped: 3656 / HURT: 0

total cycles in shared programs: 810343919 -> 810241030 (-0.01%)
cycles in affected programs: 56752034 -> 56649145 (-0.18%)
helped: 3032 / HURT: 434

LOST:   11
GAINED: 0

Ice Lake and Skylake had similar results. (Ice Lake shown)
total instructions in shared programs: 20315795 -> 20305856 (-0.05%)
instructions in affected programs: 979698 -> 969759 (-1.01%)
helped: 3845 / HURT: 0

total cycles in shared programs: 830600281 -> 830534694 (<.01%)
cycles in affected programs: 45675615 -> 45610028 (-0.14%)
helped: 3250 / HURT: 325

total spills in shared programs: 4583 -> 4565 (-0.39%)
spills in affected programs: 180 -> 162 (-10.00%)
helped: 3 / HURT: 0

total fills in shared programs: 5245 -> 5219 (-0.50%)
fills in affected programs: 379 -> 353 (-6.86%)
helped: 3 / HURT: 0

LOST:   14
GAINED: 8

fossil-db:

All Intel platforms except Tiger Lake had similar results. (Meteor Lake shown)
Totals:
Instrs: 154024263 -> 154023814 (-0.00%)
Cycle count: 17463341602 -> 17461726239 (-0.01%); split: -0.01%, +0.00%

Totals from 322 (0.05% of 631440) affected shaders:
Instrs: 199933 -> 199484 (-0.22%)
Cycle count: 168492537 -> 166877174 (-0.96%); split: -0.96%, +0.00%

Tiger Lake
Instrs: 149984723 -> 149984287 (-0.00%)
Cycle count: 15238596937 -> 15239260415 (+0.00%); split: -0.00%, +0.01%
Max dispatch width: 5553408 -> 5553424 (+0.00%)

Totals from 318 (0.05% of 631414) affected shaders:
Instrs: 179624 -> 179188 (-0.24%)
Cycle count: 160724533 -> 161388011 (+0.41%); split: -0.06%, +0.48%
Max dispatch width: 3296 -> 3312 (+0.49%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095>
 2024-05-14 01:28:21 +00:00
Ian Romanick
e578657313 intel/brw: Implement more strictly correct fsign lowering 
The huge amount of helped shaders is due to the "~" versions of the
patterns.

shader-db:

Meteor Lake and DG2 had similar results. (Meteor Lake shown)
total instructions in shared programs: 19672345 -> 19662605 (-0.05%)
instructions in affected programs: 1147766 -> 1138026 (-0.85%)
helped: 2691 / HURT: 1650

total cycles in shared programs: 810323688 -> 810145191 (-0.02%)
cycles in affected programs: 68918312 -> 68739815 (-0.26%)
helped: 3651 / HURT: 1832

LOST:   29
GAINED: 38

Tiger Lake
total instructions in shared programs: 19489619 -> 19479909 (-0.05%)
instructions in affected programs: 1124564 -> 1114854 (-0.86%)
helped: 2682 / HURT: 1643

total cycles in shared programs: 811468406 -> 811706747 (0.03%)
cycles in affected programs: 66397690 -> 66636031 (0.36%)
helped: 3692 / HURT: 1775

total spills in shared programs: 3906 -> 3907 (0.03%)
spills in affected programs: 16 -> 17 (6.25%)
helped: 0 / HURT: 1

total fills in shared programs: 3220 -> 3222 (0.06%)
fills in affected programs: 50 -> 52 (4.00%)
helped: 0 / HURT: 1

LOST:   33
GAINED: 36

Ice Lake and Skylake had similar results. (Ice Lake shown)
total instructions in shared programs: 20317882 -> 20307495 (-0.05%)
instructions in affected programs: 1199651 -> 1189264 (-0.87%)
helped: 2863 / HURT: 1680

total cycles in shared programs: 830880024 -> 830457927 (-0.05%)
cycles in affected programs: 63347102 -> 62925005 (-0.67%)
helped: 4118 / HURT: 1622

total spills in shared programs: 4593 -> 4583 (-0.22%)
spills in affected programs: 205 -> 195 (-4.88%)
helped: 4 / HURT: 0

total fills in shared programs: 5284 -> 5245 (-0.74%)
fills in affected programs: 464 -> 425 (-8.41%)
helped: 4 / HURT: 0

LOST:   70
GAINED: 33

fossil-db:

Meteor Lake and DG2 had similar results. (Meteor Lake shown)
Totals:
Instrs: 154025275 -> 154022035 (-0.00%); split: -0.00%, +0.00%
Cycle count: 17472869499 -> 17463289530 (-0.05%); split: -0.06%, +0.00%
Spill count: 141269 -> 141246 (-0.02%); split: -0.02%, +0.00%
Fill count: 265342 -> 265159 (-0.07%); split: -0.11%, +0.04%
Max live registers: 32597829 -> 32597986 (+0.00%); split: -0.00%, +0.00%
Max dispatch width: 5536776 -> 5537048 (+0.00%)

Totals from 1590 (0.25% of 631423) affected shaders:
Instrs: 1146532 -> 1143292 (-0.28%); split: -0.44%, +0.16%
Cycle count: 1230843330 -> 1221263361 (-0.78%); split: -0.83%, +0.05%
Spill count: 15832 -> 15809 (-0.15%); split: -0.19%, +0.04%
Fill count: 36071 -> 35888 (-0.51%); split: -0.79%, +0.29%
Max live registers: 93529 -> 93686 (+0.17%); split: -0.00%, +0.17%
Max dispatch width: 15168 -> 15440 (+1.79%)

Tiger Lake, Ice Lake, and Skylake had similar results. (Tiger Lake shown)
Totals:
Instrs: 149564084 -> 149562467 (-0.00%); split: -0.00%, +0.00%
Cycle count: 15151701515 -> 15158290114 (+0.04%); split: -0.00%, +0.04%
Max live registers: 32249443 -> 32249620 (+0.00%); split: -0.00%, +0.00%
Max dispatch width: 5540536 -> 5540488 (-0.00%)

Totals from 1605 (0.25% of 630303) affected shaders:
Instrs: 584950 -> 583333 (-0.28%); split: -0.49%, +0.21%
Cycle count: 160926321 -> 167514920 (+4.09%); split: -0.05%, +4.14%
Max live registers: 90851 -> 91028 (+0.19%); split: -0.00%, +0.20%
Max dispatch width: 15440 -> 15392 (-0.31%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095>
 2024-05-14 01:28:20 +00:00
Ian Romanick
864268ff0d intel/brw: Algebraic optimizations for CSEL 
No shader-db or fossil-db changes on any Intel platform. In this MR, the
only benefit of these changes is to convert some "-a > 0" CSEL
comparisons to "a < 0" for improved readability.

v2: Add integer CSEL support

v3: Use fs_inst::resize_sources and brw_type_is_sint. Both suggested by
Ken.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095>
 2024-05-14 01:28:20 +00:00
Ian Romanick
033405cd4b intel/brw: Combine constants and constant propagation for CSEL 
No shader-db or fossil-db changes on any Intel platform. This ends up
begin helpful in "intel/brw: Use range analysis to optimize fsign."

v2: Add integer CSEL support

v3: Massive simplification (-20 lines!) of constant propagation
logic. Suggested by Ken. Add missing CSEL case in supports_src_as_imm.
Noticed by Ken.

v4: While MAD can mix F and HF sources on some platforms, CSEL
cannot. Found by skqp on TGL.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v3]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095>
 2024-05-14 01:28:20 +00:00
Ian Romanick
504b742b83 intel/brw: Update CSEL source type validation 
Gfx9 can only have F, but newer GPUs can have F, HF, *D, or *W. The
source and destination types must still match in size.

v2: Simplify the float vs integer logic. Suggested by Ken.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095>
 2024-05-14 01:28:20 +00:00
Ian Romanick
3f151c03af intel/brw: Handle fsign optimization in a NIR algebraic pass 
This is a lot less code, and it makes it easier to experiment with other
pattern-based optimizations in the future.

The results here are nearly identical to the results I got from Ken's
"intel/brw: Make fsign (for 16/32-bit) in SSA form"... which are not
particularly good.

In this commit and in Ken's, all of the shader-db shaders hurt for
spills and fills are from Deus Ex Mankind Divided. Each shader has a
bunch of texture instructions with a single fsign between the
blocks. With the dependency on the flag removed, the scheduler puts all
of the texture instructions at the start... and there are a LOT of them.

shader-db:

All Intel platforms had similar results. (Meteor Lake shown)
total instructions in shared programs: 19647060 -> 19650207 (0.02%)
instructions in affected programs: 734718 -> 737865 (0.43%)
helped: 382 / HURT: 1984

total cycles in shared programs: 823238442 -> 822785913 (-0.05%)
cycles in affected programs: 426901157 -> 426448628 (-0.11%)
helped: 3408 / HURT: 3671

total spills in shared programs: 3887 -> 3891 (0.10%)
spills in affected programs: 256 -> 260 (1.56%)
helped: 0 / HURT: 4

total fills in shared programs: 3236 -> 3306 (2.16%)
fills in affected programs: 882 -> 952 (7.94%)
helped: 0 / HURT: 12

LOST:   37
GAINED: 34

fossil-db:

DG2 and Meteor Lake had similar results. (Meteor Lake shown)
Totals:
Instrs: 154005469 -> 154008294 (+0.00%); split: -0.00%, +0.00%
Cycle count: 17551859277 -> 17554293955 (+0.01%); split: -0.02%, +0.04%
Spill count: 142078 -> 142090 (+0.01%)
Fill count: 266761 -> 266729 (-0.01%); split: -0.02%, +0.01%
Max live registers: 32593578 -> 32593858 (+0.00%)
Max dispatch width: 5535944 -> 5536816 (+0.02%); split: +0.02%, -0.01%

Totals from 5867 (0.93% of 631350) affected shaders:
Instrs: 5475544 -> 5478369 (+0.05%); split: -0.04%, +0.09%
Cycle count: 1649032029 -> 1651466707 (+0.15%); split: -0.24%, +0.39%
Spill count: 26411 -> 26423 (+0.05%)
Fill count: 57364 -> 57332 (-0.06%); split: -0.10%, +0.04%
Max live registers: 431561 -> 431841 (+0.06%)
Max dispatch width: 49784 -> 50656 (+1.75%); split: +2.38%, -0.63%

Tiger Lake
Totals:
Instrs: 149530671 -> 149533588 (+0.00%); split: -0.00%, +0.00%
Cycle count: 15261418953 -> 15264764921 (+0.02%); split: -0.00%, +0.03%
Spill count: 60317 -> 60316 (-0.00%); split: -0.02%, +0.01%
Max live registers: 32249201 -> 32249464 (+0.00%)
Max dispatch width: 5540608 -> 5540584 (-0.00%)

Totals from 5862 (0.93% of 630309) affected shaders:
Instrs: 4740800 -> 4743717 (+0.06%); split: -0.04%, +0.10%
Cycle count: 566531248 -> 569877216 (+0.59%); split: -0.13%, +0.72%
Spill count: 11709 -> 11708 (-0.01%); split: -0.09%, +0.08%
Max live registers: 424560 -> 424823 (+0.06%)
Max dispatch width: 50304 -> 50280 (-0.05%)

Ice Lake
Totals:
Instrs: 150499705 -> 150502608 (+0.00%); split: -0.00%, +0.00%
Cycle count: 15105629116 -> 15105425880 (-0.00%); split: -0.00%, +0.00%
Spill count: 60087 -> 60090 (+0.00%)
Fill count: 100542 -> 100541 (-0.00%); split: -0.00%, +0.00%
Max live registers: 32605215 -> 32605495 (+0.00%)
Max dispatch width: 5617752 -> 5617792 (+0.00%); split: +0.00%, -0.00%

Totals from 5882 (0.93% of 634934) affected shaders:
Instrs: 4737206 -> 4740109 (+0.06%); split: -0.04%, +0.10%
Cycle count: 598882104 -> 598678868 (-0.03%); split: -0.08%, +0.05%
Spill count: 10278 -> 10281 (+0.03%)
Fill count: 22504 -> 22503 (-0.00%); split: -0.01%, +0.01%
Max live registers: 424184 -> 424464 (+0.07%)
Max dispatch width: 50216 -> 50256 (+0.08%); split: +0.25%, -0.18%

Skylake
Totals:
Instrs: 139092612 -> 139095257 (+0.00%); split: -0.00%, +0.00%
Cycle count: 14533550285 -> 14533544716 (-0.00%); split: -0.00%, +0.00%
Spill count: 58176 -> 58172 (-0.01%)
Fill count: 95877 -> 95796 (-0.08%)
Max live registers: 31924594 -> 31924874 (+0.00%)
Max dispatch width: 5484568 -> 5484552 (-0.00%); split: +0.00%, -0.00%

Totals from 5789 (0.93% of 625512) affected shaders:
Instrs: 4481987 -> 4484632 (+0.06%); split: -0.04%, +0.10%
Cycle count: 578310124 -> 578304555 (-0.00%); split: -0.05%, +0.05%
Spill count: 9248 -> 9244 (-0.04%)
Fill count: 19677 -> 19596 (-0.41%)
Max live registers: 415340 -> 415620 (+0.07%)
Max dispatch width: 49720 -> 49704 (-0.03%); split: +0.10%, -0.13%

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095>
 2024-05-14 01:28:20 +00:00
Ian Romanick
cd343fb9ac intel/brw: Add support for fcsel opcodes 
Don't enable nir_opt_algebraic to generate these opcodes yet.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095>
 2024-05-14 01:28:20 +00:00
Ian Romanick
d51ad9f4e0 intel/brw: Use fs_inst::resize_sources in brw_fs_opt_algebraic 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095>
 2024-05-14 01:28:20 +00:00
Ian Romanick
11c6b6c102 intel/elk: Remove dsign optimization 
This bit from the comment should have been a big red flag:

    There are currently zero instances of fsign(double(x))*IMM in
    shader-db or any test suite, so it is hard to care at this time.

The implementation of that path was incorrect. The XOR instructions
should be predicated like the OR instruction in the non-multiplication
path. As a result, dsign(zero_value) * x will not produce the correct
result.

Instead of fixing this code that is never exercised by anything, replace
it with the simple lowering in NIR.

Ironically, the vec4 implementation is correct. The odds of encountering
an application that is performace limited by dsign performance in vertex
processing stages on Ivy Bridge or Haswell is infinitesimal.

No shader-db changes on any Intel platform.

v2: Delete 's' in emit_fsign as it is now unused.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095>
 2024-05-14 01:28:20 +00:00
Ian Romanick
ded8690336 intel/brw: Remove dsign optimization 
This bit from the comment should have been a big red flag:

    There are currently zero instances of fsign(double(x))*IMM in
    shader-db or any test suite, so it is hard to care at this time.

The implementation of that path was incorrect. The XOR instructions
should be predicated like the OR instruction in the non-multiplication
path. As a result, dsign(zero_value) * x will not produce the correct
result.

Instead of fixing this code that is never exercised by anything, replace
it with the simple lowering in NIR.

No shader-db or fossil-db changes on any Intel platform.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095>
 2024-05-14 01:28:20 +00:00
Mary Guillemard
db2f2ee078 nvk, nak: Wire up conservative rasterization underestimate 
bit 611 in SPH actually control underestimate, let's wire that and
expose it.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28937>
 2024-05-14 00:03:36 +00:00
Arthur Huillet
715f2f1425 nvk: implement VK_EXT_conservative_rasterization 
This change is built on top of work originally done by Benjamin Lee.

Implement conservative rasterization on GPUs that support it.  This is done
through a MME method on pre-Volta, and through SET_CONSERVATIVE_RASTER* (newly
published) on more recent GPUs.

primitiveUnderestimation and fullyCoveredFragmentShaderInputVariable will be
supported later as they require SPH and compiler work.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9627
Signed-off-by: Arthur Huillet <ahuillet@nvidia.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28937>
 2024-05-14 00:03:36 +00:00
Benjamin Lee
4dd97b1d72 vk/graphics_state: Add last bits for extraPrimitiveOverestimationSize 
A couple pieces were missed when this was originally added in
b172fd62f5.  Without this, NVK doesn't
pick up the value of extraPrimitiveOverestimationSize in 'dyn->rs'.

Signed-off-by:  Benjamin Lee <benjamin@computer.surgery>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28937>
 2024-05-14 00:03:36 +00:00
Arthur Huillet
a875598d9e nvk: update 3d classes for conservative raster 
Signed-off-by: Arthur Huillet <ahuillet@nvidia.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28937>
 2024-05-14 00:03:36 +00:00
David Heidelberg
891730ac0b ci/panfrost: disable G52 until machines gets fixed 
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29181>
 2024-05-13 22:59:30 +00:00
David Heidelberg
3d5ad071bf freedreno/ci: re-enable a306_piglit 
Updated fails list.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29155>
 2024-05-13 22:21:55 +00:00
David Heidelberg
fed2c9df01 freedreno/ci: switch a306 to weston 
Haven't noted any functional difference.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29155>
 2024-05-13 22:21:55 +00:00
David Heidelberg
f6652d55da freedreno/ci: do not depend on single job rules for another jobs 
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29155>
 2024-05-13 22:21:55 +00:00
David Heidelberg
8cf60b4da7 freedreno/ci: Switch a306_* to deqp-runner 
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29155>
 2024-05-13 22:21:55 +00:00
David Heidelberg
d9a0373a65 freedreno/ci: move the disabled jobs from include to the main file 
Accidentally moved.

Fixes: 9442571664 ("ci: separate hiden jobs to -inc.yml files")

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29155>
 2024-05-13 22:21:55 +00:00
David Heidelberg
e0f44f817d freedreno/ci: move platform to the deqp toml file for a530 
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29155>
 2024-05-13 22:21:55 +00:00
Rob Clark
312150f524 freedreno/ci: Switch a618_piglit to deqp-runner 
Better match a630_piglit, and lets us share a common skips file in
follow-up commit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29155>
 2024-05-13 22:21:55 +00:00
Yiwei Zhang
758b639d1b venus: drop the workaround for excessive dma-buf import oom on turnip 
This reverts commit fdc21a95aa.

No longer needed per prior commit.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29173>
 2024-05-13 21:58:37 +00:00
Yiwei Zhang
a1392394ba turnip: msm: fix racy gem close for re-imported dma-buf 
For dma-buf, if the import and finish occur back-2-back for the same
dma-buf, zombie vma cleanup will unexpectedly close the re-imported
dma-buf gem handle. This change fixes it by trying to resurrect from
zombie vmas on the dma-buf import path.

Fixes: 63904240f2 ("tu: Re-enable bufferDeviceAddressCaptureReplay")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29173>
 2024-05-13 21:58:37 +00:00
Yiwei Zhang
3909803849 turnip: msm: clean up iova on error path 
Fixes: e23c4fbd9b ("tu: Switch to userspace iova allocations if kernel supports it")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29173>
 2024-05-13 21:58:37 +00:00
Georg Lehmann
80b8bbf0c5 aco/gfx11: use v_swap_b16 
I tested that v_swap_b16 can be encoded as VOP3, because the ISA doc doesn't list
it as a possible VOP3 opcode. VOP3 is nessecary to access v128+.

Foz-DB Navi31:
Totals from 32 (0.04% of 79395) affected shaders:
Instrs: 201865 -> 195168 (-3.32%)
CodeSize: 1082220 -> 1031228 (-4.71%); split: -4.71%, +0.00%
Latency: 2258198 -> 2238586 (-0.87%)
InvThroughput: 796731 -> 788934 (-0.98%)
Copies: 34514 -> 29220 (-15.34%)
VALU: 122457 -> 117163 (-4.32%)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29143>
 2024-05-13 18:42:19 +00:00
Eric Engestrom
5803a40e2f radeonsi/ci: document new crash (assert) 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29168>
 2024-05-13 18:23:35 +00:00
Rhys Perry
38cbc3c605 radv: advertise VK_EXT_legacy_vertex_attributes 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11094
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29071>
 2024-05-13 17:22:27 +00:00
Rhys Perry
6ddd675168 aco/util: improve small_vec assertion 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29071>
 2024-05-13 17:22:26 +00:00
Rhys Perry
869253b66c aco: support VS prologs with unaligned access 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29071>
 2024-05-13 17:22:26 +00:00
Rhys Perry
9ec2fa392f aco: copy VS prolog constants after loads 
This way, the loads start earlier.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29071>
 2024-05-13 17:22:26 +00:00
Rhys Perry
46b8ba8154 aco: form hard clauses in VS prologs 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29071>
 2024-05-13 17:22:26 +00:00
Rhys Perry
d48c8905f1 radv: keep track of unaligned dynamic vertex access 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29071>
 2024-05-13 17:22:26 +00:00
Samuel Pitoiset
62b4e9a779 radv: simplify radv_emit_hw_gs() slightly 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29132>
 2024-05-13 16:10:20 +00:00
Samuel Pitoiset
bdefab362c radv: simplify radv_emit_hw_vs() slightly 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29132>
 2024-05-13 16:10:20 +00:00
Samuel Pitoiset
5572a83b00 radv: simplify radv_emit_hw_ngg() slightly 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29132>
 2024-05-13 16:10:20 +00:00
Samuel Pitoiset
dd3ae170a7 radv: do not emit VGT_GS_OUT_PRIM_TYPE to ctx_cs on GFX11 
Missed that one but it doesn't cause any context rolls.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29132>
 2024-05-13 16:10:20 +00:00
Samuel Pitoiset
f228e7ed2d radv: remove gfx10_emit_ge_pc_alloc() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29132>
 2024-05-13 16:10:20 +00:00
Patrick Lerda
df39994d51 clover: fix memory leak related to optimize 
Indeed, the object returned by LLVMCreatePassBuilderOptions()
was not freed.

For instance, this issue is triggered with "piglit/bin/cl-api-build-program":
Direct leak of 32 byte(s) in 1 object(s) allocated from:
    #0 0x7f6b15abdf57 in operator new(unsigned long) (/usr/lib64/libasan.so.6+0xb2f57)
    #1 0x7f6afff6529e in LLVMCreatePassBuilderOptions llvm-18.1.5/lib/Passes/PassBuilderBindings.cpp:83
    #2 0x7f6b1186ee41 in optimize ../src/gallium/frontends/clover/llvm/invocation.cpp:521
    #3 0x7f6b1186ee41 in clover::llvm::link_program(std::vector<clover::binary, std::allocator<clover::binary> > const&, clover::device const&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >&) ../src/gallium/frontends/clover/llvm/invocation.cpp:554
    #4 0x7f6b1150ce67 in link_program ../src/gallium/frontends/clover/core/compiler.hpp:78
    #5 0x7f6b1150ce67 in clover::program::link(clover::ref_vector<clover::device> const&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, clover::ref_vector<clover::program> const&) ../src/gallium/frontends/clover/core/program.cpp:78
    #6 0x7f6b11401a2b in clBuildProgram ../src/gallium/frontends/clover/api/program.cpp:283

Fixes: 2d4fe5f229 ("clover/llvm: move to modern pass manager.")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29164>
 2024-05-13 15:47:55 +00:00
Juan A. Suarez Romero
28eb1b1eaf vc4: use IO semantics for location 
Use IO semantics to find the locations instead of more complex ways.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29133>
 2024-05-13 14:35:46 +00:00
Danylo Piliaiev
7eb6123e98 tu/a750: Disable HW binning when there is GS 
Blob doesn't use hw binning with GS on all a6xx and a7xx, however
in Turnip it worked without issues until a750. On a750 there are CTS
failures when e.g. dEQP-VK.subgroups.arithmetic.framebuffer.* in
parallel with "forcebin". It is exacerbated by using "syncdraw".

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29074>
 2024-05-13 13:50:53 +00:00
Samuel Pitoiset
8b85c58429 radeonsi: remove the _unused parameter in all radeon_xxx macros 
I plan to re-use all these macros in RADV, mostly for GFX11 paired
packets and for GFX12.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29130>
 2024-05-13 12:24:18 +00:00