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136109 Commits

Author SHA1 Message Date
Alyssa Rosenzweig
69ddbc4341 pan/bi: Suppress uniform validation for LD_BUFFER 
Seems to be ok and used by the DDK...

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
 2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig
36486f54e9 pan/bi: Confirm IDP unit on Valhall 
Based on Anandtech which gives 8-bit dot product throughput on Valhall
under FMA and not consistent with SFU.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
 2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig
b8ba909ca6 pan/bi: Forbid unaligned staging registers on Valhall 
Would've saved me some debugging with the computerator. I keep
forgetting about this nuance. Enforce it in the assembler.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
 2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig
df807cb839 pan/bi: Add XML for assembling Valhall image stores 
Not complete yet but let's get some tests in early. Document the new
instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
 2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig
58b65a340c pan/bi: Add Valhall's special FMA_RSCALE instructions 
Like Bifrost, but exposed as separate physical instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
 2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig
aee819d54c pan/bi: Add sqrt form of Valhall FREXPM 
Like Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
 2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig
137053c4f4 pan/bi: Add full form of Valhall MUX instruction 
Like Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
 2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig
855ab23d9a pan/bi: Annotate Valhall instructions with units 
Based on analyzing the cycle counts reported by the Mali offline
compiler.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
 2021-11-18 23:16:20 +00:00
Mike Blumenkrantz
04cc1b93b1 zink: enable PIPE_TEXTURE_TRANSFER_COMPUTE on non-cpu drivers 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13859>
 2021-11-18 22:12:58 +00:00
Mike Blumenkrantz
ea761a40d5 zink: use pb_slab_alloc_reclaimed(reclaim_all) for BAR heap sometimes 
this forces a full slab reclaim any time the device is known to have a
too-small BAR in order to keep memory usage at a minimum when it might otherwise
balloon out and crash us

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13850>
 2021-11-18 21:22:30 +00:00
Mike Blumenkrantz
da9acf7088 aux/pb: add a new slab alloc function for reclaiming all bo objects 
sometimes a driver might want to always reclaim all bo objects in the course
of allocating a new bo. this is useful when it's known that a given memory
heap is very small and will likely need to keep its usage minimized

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13850>
 2021-11-18 21:22:30 +00:00
Roland Scheidegger
b7e2214b3c llvmpipe: adjust rounding for viewport scissoring 
Some apps may try to use a viewport adjusted by 0.5 pixels (among other
things) to emulate d3d9 pixel center, and in this case we would end up
with incorrect "fake scissor" box (shifted by 1 pixel), hence pixels
being incorrectly scissored away when permit_linear_rasterizer is set
(this happens even if the linear rasterizer is not used in the end).

So adjust the offset so that the half-way points get rounded down instead
of up.
(This is all a bit iffy I think since we don't use fractional
boxes (with 8 subpixel bits) anywhere yet, but at least without msaa
it should work out.)

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13794>
 2021-11-18 19:23:13 +00:00
Samuel Pitoiset
341278f069 radv: disable HTILE for D32S8 format and mipmaps on GFX10 
Stencil texturing with HTILE doesn't work with mipmapping on Navi10-14,
it's a hw bug. RadeonSI and PAL have a workaround too.

This fixes 35 piglit failures with Zink on Navi10.

Cc: 21.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13814>
 2021-11-18 14:45:54 +00:00
Tomeu Vizoso
81f25d8f27 virgl/ci: Run each dEQP instance in its own VM 
Currently we run deqp-runner inside a single VM, which makes very poor
use of the available CPUs because Virgl has a bottleneck in the VMM that
serializes everything.

With this change, we can run several Crosvm instances in a runner and
make full use of the CPUs. Getting the same coverage with 3 runners
instead of 6.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12828>
 2021-11-18 13:36:24 +00:00
Tomeu Vizoso
d542e978e9 virgl/ci: Set GALLIVM_PERF=nopt,no_quad_lod 
nopt will disable some shader optimizations that slow down test runs for
no gain.

no_quad_lod will disable some speed hacks that can cause inaccurate
results.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12828>
 2021-11-18 13:36:24 +00:00
Mike Blumenkrantz
e7b9561959 gallium: implement compute pbo download 
this reworks PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER into an
enum as PIPE_CAP_TEXTURE_TRANSFER_MODES, enabling drivers to choose
a (sometimes) faster, compute-based download mechanism based on a new
pipe_screen hook

compute pbo download is implemented using shaders with a prolog to convert
the input format to generic rgb float values, then an epilog to convert
to the output value. the prolog and epilog are determined based on a vec4
of packed ubo data which is dynamically updated based on the API usage

currently, the only known limitations are:
* GL_ARB_texture_cube_map_array is broken somehow (and disabled)
* AMD hardware somehow can't do depth readback?

otherwise it should work for every possible case

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11984>
 2021-11-18 08:00:07 -05:00
Mike Blumenkrantz
ed65b5e839 mesa/st: make some pbo functions public 
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11984>
 2021-11-18 08:00:05 -05:00
Mike Blumenkrantz
f7a51e9469 mesa/st: make sampler_type_for_target public 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11984>
 2021-11-18 07:58:29 -05:00
Mike Blumenkrantz
c9a47c85da gallium: rename PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER 
this is now a bitfield enum for more functionality

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11984>
 2021-11-18 07:58:29 -05:00
Mike Blumenkrantz
0b30a7a243 gallium: add pipe_screen::is_compute_copy_faster hook 
this can be used to query whether a driver expects a given texture
copy to be faster as a compute shader or using cpu/gfx transfers

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11984>
 2021-11-18 07:58:29 -05:00
Dylan Baker
a854cbc7b5 turnip: don't use mesa/macros.h to get utils/rounding.h 
For hopefully obvious reasons.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13853>
 2021-11-18 10:46:51 +00:00
Pierre-Eric Pelloux-Prayer
df8aeb4598 radeonsi/sqtt: increase the default buffer size to 32MB 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13838>
 2021-11-18 10:53:37 +01:00
Pierre-Eric Pelloux-Prayer
56382ec071 radeonsi: unreference framebuffer state after use 
util_copy_framebuffer_state increases refcounts, so we have
to decrement them afterwards.

Fixes: b1b491cdbb ("radeonsi: add a faster clear path for glClearTexImage")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5631
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13838>
 2021-11-18 10:53:34 +01:00
Iago Toral Quiroga
5e536c97a9 broadcom/compiler: fix early fragment tests setup 
When early fragment tests are mandated by the shader, we must use
the Z value produced by the FEP even if there are elements that
would typically require late fragment tests (such as discards,
sample to coverage, etc).

This change means we also need to be a bit more careful when
we promote shaders to use early fragment tests so we don't
promote anything with discards for example.

Fixes:
dEQP-VK.fragment_operations.early_fragment.discard_early_fragment_tests_depth
dEQP-VK.fragment_operations.early_fragment.discard_early_fragment_tests_stencil

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13837>
 2021-11-18 07:39:32 +00:00
Joshua Ashton
68ec867181 radv: Implement VK_EXT_image_view_min_lod 
Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13820>
 2021-11-18 01:05:06 +00:00
Joshua Ashton
d0f217ad80 vulkan: Update the XML and headers to 1.2.199 
Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13820>
 2021-11-18 01:05:06 +00:00
Joshua Ashton
4e76d0cb56 radv: Expose min_lod in *_make_texture_descriptor 
We'll need this going forward for VK_EXT_image_view_min_lod.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13820>
 2021-11-18 01:05:06 +00:00
Joshua Ashton
c6471ef918 radv: Refactor S_FIXED to radv_float_to_{s,u}fixed 
We'll need to use this in radv_image for VK_EXT_image_view_min_lod.

Additionally, creates signed/unsigned variants to avoid sign-extending where we don't need to.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13820>
 2021-11-18 01:05:06 +00:00
Mike Blumenkrantz
35ffadb9e7 zink: clamp to 500 max batch states on nvidia 
I've been advised that leaving this unclamped will use up all the fds
allotted to a process

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13844>
 2021-11-18 00:00:16 +00:00
Mike Blumenkrantz
a3be30665f zink: fail context creation more gracefully 
handle some cases where context creation fails earlier than expected

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13844>
 2021-11-18 00:00:16 +00:00
Mike Blumenkrantz
72a88c77de zink: fix memory availability reporting 
this shouldn't report the budgeted available memory, it should return
the total memory, as that's what this api expects

Fixes: ff4ba3d4a7 ("zink: support PIPE_CAP_QUERY_MEMORY_INFO")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13849>
 2021-11-17 22:59:43 +00:00
Mike Blumenkrantz
5f140a723d zink: use IMMUTABLE for dummy xfb buffer 
this is never getting read back or anything so don't waste BAR allocation

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13849>
 2021-11-17 22:59:43 +00:00
Mike Blumenkrantz
1eb2f0d41e zink: demote BAR allocations to device-local on oom 
ideally this shouldn't happen, but it's better than crashing even if
it may crash later from attempting to map

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13849>
 2021-11-17 22:59:43 +00:00
Mike Blumenkrantz
8f97af050e zink: set zink_resource_object::host_visible based on actual bo placement 
the properties determined before allocation may not be the same as what gets
allocated

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13849>
 2021-11-17 22:59:43 +00:00
Mike Blumenkrantz
74d2e89201 zink: always use slab allocation placement for domains 
this allows the actual bo to have its memory type changed if necessary

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13849>
 2021-11-17 22:59:43 +00:00
Mike Blumenkrantz
4fc216b4ba zink: add error for bo allocation failure 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13849>
 2021-11-17 22:59:43 +00:00
Marek Olšák
83278b5661 glx: add a workaround to glXDestroyWindow for Viewperf2020/Sw 
This fixes:
    X Error of failed request:  GLXBadWindow
      Major opcode of failed request:  152 (GLX)
      Minor opcode of failed request:  32 (X_GLXDestroyWindow)
      Serial number of failed request:  9667
      Current serial number in output stream:  9674

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13611>
 2021-11-17 21:26:54 +00:00
Iván Briano
0388783a03 intel/nir: also allow unknown format for getting the size of a storage image 
Fixes: fa251cf111 ("intel/nir: allow unknown format in lowering of storage images")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13847>
 2021-11-17 21:06:23 +00:00
Ian Romanick
04f5c543de glsl/nir: Don't build soft float64 when it cannot be used 
Fixes: 82d9a37a59 ("glsl/nir: Add a shared helper for building float64 shaders")
Closes: #5556
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13828>
 2021-11-17 12:23:29 -08:00
Mike Blumenkrantz
b1a32d1432 zink: implement multiplanar modifier handling 
it turns out this is trivial as long as dri gives usable resource templates

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13799>
 2021-11-17 19:22:02 +00:00
Mike Blumenkrantz
b1675608c3 dri2: set dimensions on dmabuf import planes 
this is unusable for some drivers without the plane size attached

Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13799>
 2021-11-17 19:22:02 +00:00
Mike Blumenkrantz
943f6a038d zink: always set matching resource export type for dmabuf creation 
both of these need to be set if one is

cc: mesa-stable

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13799>
 2021-11-17 19:22:02 +00:00
Mike Blumenkrantz
11c79a8bd7 zink: stop using VK_IMAGE_LAYOUT_PREINITIALIZED for dmabuf 
this is illegal

cc: mesa-stable

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13799>
 2021-11-17 19:22:02 +00:00
Jason Ekstrand
63baeffc2d vulkan/sync: Rework asserts a bit 
ANV currently smashes off the TIMELINE bit depending on whether or not
the i915 interface supports them, triggering assert(!type->get_value).
Instead of requiring ANV to smash off function pointers, let the extra
function pointers through and then assert on the feature bits before the
function pointers get used.  This should give us roughly the same amount
of assert protection while side-stepping the feature disabling problem.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13839>
 2021-11-17 16:52:29 +00:00
Filip Gawin
0c74f80645 glsl: fix trivial strict aliasing warning 
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13827>
 2021-11-17 16:22:10 +00:00
Omar Akkila
58a0d8d0de llvmpipe: page-align memory allocations 
Allows memory allocated by llvmpipe_allocate_memory_fd to be
mappable to guests in virtualized environments like KVM which
requires page-aligned memory.

llvmpipe_allocate_memory is updated similarly for consistency.

Signed-off-by: Omar Akkila <omar.akkila@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13793>
 2021-11-17 09:25:37 -05:00
Connor Abbott
23a5f1a5ac ir3: Stop inserting nops during scheduling 
Not necessary since nothing uses it anymore. This might have a slight
effect on spilling with multiple blocks, but no shader-db difference
because nothing spills.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13722>
 2021-11-17 13:41:47 +00:00
Connor Abbott
e0eeba6cbb ir3/postsched: Only prefer tex/sfu if they are soft-ready 
Otherwise we schedule an SFU depending on a tex as soon as the tex is
scheduled, which is very much not what we want.

Note that sstall is helped more than nops are hurt, and the shaders with
the largest nop regressions also have sstall helped. However (sy) is
also very much helped.

total nops in shared programs: 345482 -> 345986 (0.15%)
nops in affected programs: 5731 -> 6235 (8.79%)
helped: 15
HURT: 81
helped stats (abs) min: 1 max: 9 x̄: 3.27 x̃: 3
helped stats (rel) min: 0.50% max: 16.00% x̄: 8.55% x̃: 10.26%
HURT stats (abs)   min: 1 max: 72 x̄: 6.83 x̃: 4
HURT stats (rel)   min: 0.57% max: 400.00% x̄: 32.50% x̃: 13.16%
95% mean confidence interval for nops value: 3.34 7.16
95% mean confidence interval for nops %-change: 13.07% 39.10%
Nops are HURT.

total sstall in shared programs: 133804 -> 132381 (-1.06%)
sstall in affected programs: 4743 -> 3320 (-30.00%)
helped: 68
HURT: 24
helped stats (abs) min: 1 max: 153 x̄: 21.88 x̃: 8
helped stats (rel) min: 1.79% max: 100.00% x̄: 33.20% x̃: 28.00%
HURT stats (abs)   min: 1 max: 11 x̄: 2.71 x̃: 2
HURT stats (rel)   min: 1.02% max: 200.00% x̄: 17.73% x̃: 5.59%
95% mean confidence interval for sstall value: -22.05 -8.89
95% mean confidence interval for sstall %-change: -27.60% -12.22%
Sstall are helped.

total (ss) in shared programs: 35471 -> 35481 (0.03%)
(ss) in affected programs: 462 -> 472 (2.16%)
helped: 9
HURT: 15
helped stats (abs) min: 1 max: 2 x̄: 1.11 x̃: 1
helped stats (rel) min: 4.17% max: 33.33% x̄: 14.00% x̃: 7.69%
HURT stats (abs)   min: 1 max: 3 x̄: 1.33 x̃: 1
HURT stats (rel)   min: 1.19% max: 50.00% x̄: 12.27% x̃: 8.33%
95% mean confidence interval for (ss) value: -0.14 0.97
95% mean confidence interval for (ss) %-change: -5.11% 9.94%
Inconclusive result (value mean confidence interval includes 0).

total (sy) in shared programs: 13522 -> 13288 (-1.73%)
(sy) in affected programs: 422 -> 188 (-55.45%)
helped: 22
HURT: 1
helped stats (abs) min: 1 max: 21 x̄: 10.68 x̃: 10
helped stats (rel) min: 8.00% max: 94.44% x̄: 56.58% x̃: 56.94%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 25.00% max: 25.00% x̄: 25.00% x̃: 25.00%
95% mean confidence interval for (sy) value: -13.18 -7.17
95% mean confidence interval for (sy) %-change: -65.48% -40.59%
(sy) are helped.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13722>
 2021-11-17 13:41:47 +00:00
Connor Abbott
6f5c0d209c ir3/postsched: Rewrite delay handling 
Analogous to the pre-RA scheduler. Unfortunately this time it's a bit
more involved because we have to correctly handle (rptN), which is
already relevant for swz. This means we need the index of the
destination register that conflicts with the source register, to handle
swz, and we need to expose that part of ir3_delay. But once that's done,
we can delete ir3_delay_calc_postra.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13722>
 2021-11-17 13:41:47 +00:00
Connor Abbott
140e117f2b ir3/delay: Ignore earlier definitions to the same register 
We have a situation in some skia shaders like:

add.f r0.x, ...
(rpt2)nop
mul.f ..., r0.x
sam (xyzw) r0.x, ...
rcp ..., r0.x

Notice that rcp uses the result of the sam instruction, not the add.f,
but we didn't keep track of which instructions kill the sources in
ir3_delay, so we'd add an extra nop, resulting in a disagreement betwen
ir3_delay and the scheduling graph. Since postsched is correct, fix
ir3_delay. This only results in some very slight shader-db changes but
keeps the next commit from changing things.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13722>
 2021-11-17 13:41:47 +00:00