65e64b6e2d
agx: handle discard with force early tests
...
we need to predicate the store, since we can't do a hardware demote after
running tests. this is similar to what the blob does.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29607 >
2024-06-07 16:57:03 +00:00
1dfb461552
asahi: add AGX_TEXTURE_FLAG_CLAMP_TO_0 flag
...
for border colour emulation
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29607 >
2024-06-07 16:57:03 +00:00
ff032297de
asahi: support bigger buffer textures
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29607 >
2024-06-07 16:57:03 +00:00
b88bcca459
asahi: bounds check eMRT stores
...
this is a hack that fixes faults with eMRT. I do not understand what's going on
here. hopefully we can root cause this at some point :-/
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29607 >
2024-06-07 16:57:03 +00:00
152595057c
asahi: force bindless for eMRT
...
the perf difference is neglible and this simplifies the state management.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29607 >
2024-06-07 16:57:03 +00:00
e5bc9da499
asahi: add missing lowerings
...
not sure how this worked before.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29607 >
2024-06-07 16:57:03 +00:00
a9a6af50a7
agx: rework libagx I/O lowering
...
that would otherwise fight with other driver I/O lowering.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29607 >
2024-06-07 16:57:03 +00:00
5f72234745
asahi: split param structs for GS internal kernel
...
this simplifies state management consdierably
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29607 >
2024-06-07 16:57:03 +00:00
d3291ad001
agx: fix draw param gather for sw vs
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29607 >
2024-06-07 16:57:03 +00:00
3c42d55b15
asahi: be robust against out of sync shader info
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29607 >
2024-06-07 16:57:03 +00:00
e49e8fcfee
libagx: add libagx_copy_xfb_counters helper
...
for hk
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29607 >
2024-06-07 16:57:03 +00:00
70f043d6c1
libagx: drop unused !indexed path
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29607 >
2024-06-07 16:57:03 +00:00
5056ead5d2
libagx: fix triangle fan + prim restart + GS/XFB
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29607 >
2024-06-07 16:57:03 +00:00
3e3fd6877b
libagx: fix static assert
...
../src/asahi/lib/shaders/geometry.h:193:1: warning: redefinition of typedef 'static_assertion___line__' is a C11 feature [-Wtypedef-redefinition]
../src/asahi/lib/shaders/libagx.h:45:17: note: expanded from macro 'AGX_STATIC_ASSERT'
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29607 >
2024-06-07 16:57:03 +00:00
a412bf0127
libagx: rm unused field
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29607 >
2024-06-07 16:57:03 +00:00
18658d8d60
asahi/decode: drop Apple-specific decode check
...
Linux doesn't use a BO list.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29607 >
2024-06-07 16:57:03 +00:00
cea3aeefd0
ci: add farm variable for devices in collabora farm
...
Add farm variable for devices in the collabora farm so that
the LAVA job submitter uses this in structured log files.
Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29583 >
2024-06-07 14:32:49 +00:00
5297896856
aco: use ac_get_hw_cache_flags()
...
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29243 >
2024-06-07 13:22:43 +00:00
167b6cac45
ac: stop using radeon_info for ac_get_hw_cache_flags
...
This makes the function easier to use when radeon_info is not available.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29243 >
2024-06-07 13:22:43 +00:00
00eccf524f
aco: use GFX12 scope/temporal-hint
...
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29243 >
2024-06-07 13:22:42 +00:00
b41f0f6cc1
aco: use ac_hw_cache_flags
...
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29243 >
2024-06-07 13:22:42 +00:00
cdaf269924
aco: inline store_vmem_mubuf/emit_single_mubuf_store
...
Both of these are only used once.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29243 >
2024-06-07 13:22:42 +00:00
185fa04baa
aco/gfx6: set glc for buffer_store_byte/short
...
For the same reason we set it for image stores. GFX6 has a caching bug
which requires this.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29243 >
2024-06-07 13:22:42 +00:00
6f6da58315
intel/compiler: fix shuffle generation on LNL
...
There doesn't seem to be a restriction on the mentioned data types on
LNL anymore. Default to a maximum exec size of SIMD16.
This patch fixes dEQP-VK.subgroups.shuffle.framebuffer.* on LNL
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29504 >
2024-06-07 12:51:30 +00:00
d4ccae739b
radv: fix creating unlinked shaders with ESO when nextStage is 0
...
When nextStage is 0, the driver needs to assume that a stage might be
used with any valid next stages.
Fixes new dEQP-VK.shader_object.binding.*_no_next_stage.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29567 >
2024-06-07 12:21:38 +00:00
cc82f7f8ac
tu: Emit GRAS_LRZ_DEPTH_BUFFER_INFO correctly
...
This register stores the depth format of the underlying depth
buffer, it seemingly doesn't change anything about the LRZ buffer
itself and has no behavioral changes over setting it to 0.
However, it's possible that there's some case where it does matter
so matching the proprietary driver's behavior is safer.
Signed-off-by: Mark Collins <mark@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29453 >
2024-06-07 10:18:10 +00:00
a6f08fd69d
fd/a7xx: Document LRZ_FLIP_BUFFER event
...
I found this while reverse engineering A7XX LRZ, it's going to be
relevant when we implement concurrent binning so I've added the
register definition.
Signed-off-by: Mark Collins <mark@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29453 >
2024-06-07 10:18:10 +00:00
7ad5bacf7a
tu: Enable LRZ fast-clear for A7XX
...
Signed-off-by: Mark Collins <mark@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29453 >
2024-06-07 10:18:10 +00:00
9e936d3fde
tu: Specify LRZ FC depth clear value on A7XX
...
A7XX allows setting the FC depth to an arbitrary F32 value rather
than being limited to 0.0/1.0, we use this to match the depth clear
value.
Signed-off-by: Mark Collins <mark@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29453 >
2024-06-07 10:18:10 +00:00
15b02f4700
tu: Update LRZ FC dirty clear for A7XX
...
Signed-off-by: Mark Collins <mark@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29453 >
2024-06-07 10:18:10 +00:00
db505ea565
tu: Update LRZ FC allocation for A7XX layout
...
The allocation size is now determined based off the LRFC structure
rather than hardcoding in A6XX's layout.
Signed-off-by: Mark Collins <mark@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29453 >
2024-06-07 10:18:10 +00:00
bf5e8fb394
tu/lrz: Add structure for LRZ FC layout
...
The layout of the LRZ FC section has changed substantially between
A6XX and A7XX so the best way to express the layout was determined
to be a templated structure.
Signed-off-by: Mark Collins <mark@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29453 >
2024-06-07 10:18:10 +00:00
c801fd9771
tu: Allow LRZ on A7XX
...
LRZ without FC should work with all the current changes.
Signed-off-by: Mark Collins <mark@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29453 >
2024-06-07 10:18:10 +00:00
e2eda5a9eb
fd/a7xx: Initialize magic register 8008 to 0
...
This can be seen emitted in traces related to FDM on A740, it's set
to zero to ensure there's no side effects from prop writing to it.
Signed-off-by: Mark Collins <mark@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29453 >
2024-06-07 10:18:10 +00:00
c85cd9c0b0
fd/a7xx: Initialize magic register 8C34 to 0
...
This register is set by prop sometimes, functionality is unknown
at the moment.
Signed-off-by: Mark Collins <mark@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29453 >
2024-06-07 10:18:10 +00:00
0068e75fc6
tu/lrz: Use actual CHIP rather than hardcoding A6XX
...
A lot of CHIP template parameters were hardcoded to A6XX rather than
the actual chip which would lead to an incorrect command stream being
generated.
Signed-off-by: Mark Collins <mark@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29453 >
2024-06-07 10:18:10 +00:00
895c091cdd
tu/lrz: Emit GRAS_LRZ_CNTL2 on A7XX
...
The functionality of GRAS_LRZ_CNTL on A6XX was split into GRAS_LRZ_CNTL
and GRAS_LRZ_CNTL2 on A7XX. The only new field is for the Z function to
be specified.
Signed-off-by: Mark Collins <mark@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29453 >
2024-06-07 10:18:10 +00:00
f592483350
tu/shader: Allow LRZ when write pos with explicit early frag test
...
This is an exceptional case where any writes to gl_Depth should be
ignored, it means we can use LRZ in this case and don't need to
disable it.
Signed-off-by: Mark Collins <mark@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29453 >
2024-06-07 10:18:10 +00:00
84b74599cb
v3d,v3dv: document cl_emit_with_prepacked
...
In addition to always being good to have some documentation, it was
added to clarify that if you use the macro to fill up values, it will
not override the values coming from the prepacked buffer, but doing an
OR.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com >
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29570 >
2024-06-07 09:44:13 +02:00
94989b45a5
anv,driconf: Add fake non device local memory WA for Total War: Warhammer 3
...
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8721
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29127 >
2024-06-07 04:14:10 +00:00
df17f2b89a
meson: bump test-timeout
...
This tests usually takes around 15 seconds on CI, according to logs. It
recently timed out under load, causing a job to fail spuriously.
Let's bump the timeout here to 60. That's in line with the glsl compiler
warnings test, which usually takes around the same time.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29547 >
2024-06-07 03:38:59 +00:00
db38a4913e
llvmpipe: query winsys support for dmabuf mapping
...
Fixes #11257 by ensuring winsys mapping functions is only called
if its supported by the winsys, which should prevent llvmpipe from
crashing with kmswast.
If the winsys is kms_swrast then this method will be null, but on
drisw it will be available.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com >
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29546 >
2024-06-07 02:42:20 +00:00
85ff3f525c
util: Rename DETECT_OS_UNIX to DETECT_OS_POSIX
...
Looking at each usage of DETECT_OS_UNIX, it's more about the POSIX API usage, not the
Unix-like OS, so let's rename it
And for POSIX it's a standard to claim which API present, but for UNIX there is no such thing
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com >
Acked-by: Rob Clark <robdclark@chromium.org >
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29555 >
2024-06-07 01:56:28 +00:00
73cc6c6738
venus/ci: add flake that's been blocking MRs
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29590 >
2024-06-07 01:24:26 +00:00
de22e20294
anv: Rely more on ISL_SURF_USAGE_DISABLE_AUX_BIT
...
In order to support CCS, ISL may upgrade a main surface from Tile4 to
Tile64 with miptails disabled. To avoid using this space consuming
layout when not needed, inform ISL as soon as possible that compression
won't be used.
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29094 >
2024-06-07 00:58:41 +00:00
fc57991b66
anv: Support multiple aspects in anv_formats_ccs_e_compatible
...
Prevents the next patch from causing the following assert failure:
Test case 'dEQP-VK.ycbcr.copy.g8_b8_r8_3plane_420_unorm.g8_b8_r8_3plane_444_unorm.linear_linear_disjoint'..
deqp-vk: ../../src/intel/vulkan/anv_private.h:4962: anv_aspect_to_plane: Assertion `!(aspect & ~all_aspects)' failed.
We still disable CCS for multiplane formats elsewhere. I've attempted
enabling CCS for those cases but end up with failures in CI that I
cannot reproduce locally. Hopefully this change gets the next person a
step closer towards enabling this feature.
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29094 >
2024-06-07 00:58:41 +00:00
14a0f7391d
anv,hasvk: Drop anv_get_isl_format_with_usage
...
Since 3beaaa9ae8rohan.garg@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29094 >
2024-06-07 00:58:41 +00:00
3e9dc450a6
anv: Rely on the primary surf usage to disable aux
...
Instead of passing isl_extra_usage_flags to
add_aux_surface_if_supported, use the isl_surf::usage field of the
primary surface to check for ISL_SURF_USAGE_DISABLE_AUX_BIT.
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29094 >
2024-06-07 00:58:41 +00:00
8e96b516ca
intel/isl: Assert alignments of surface addresses
...
In the import paths in iris, there are several cases where surface VMAs
are created without relying on the calculated surface alignment.
Asserting the alignments of surface addresses, should help catch any
cases where we end up with the wrong alignment.
This found a couple issues during development. One which required a
change to existing code is that when creating uncompressed surfaces from
compressed ones, ISL will sometimes increase the image alignment as a
result of the new format supporting CCS. This patch adds the usage flag
to disable that behavior.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29094 >
2024-06-07 00:58:41 +00:00
31560d82ad
iris: Simplify bo import in memobj_create_from_handle
...
Looking at the caller, we only import FDs without modifiers. By
asserting this behavior and dropping the unused cases, we gain some
clarity on the alignment of the imported BO's VMA.
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29094 >
2024-06-07 00:58:41 +00:00
Alyssa Rosenzweig