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Author SHA1 Message Date
José Roberto de Souza 1de5d2ac01 anv: Return earlier in anv_gem_get_tiling() when not supported 
Tiling set and get UAPIs has the same support level.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18251>
 2022-08-25 19:21:49 +00:00
José Roberto de Souza e9cba466ea anv: Nuke dead code 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18251>
 2022-08-25 19:21:49 +00:00
Eric Engestrom c66622de3a meson: replace manual compiler flags with meson arguments 
These would only have worked in GCC and Clang, which so far wasn't an
issue, but let's clean it up anyway.

Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18190>
 2022-08-24 22:13:19 +00:00
Lionel Landwerlin f242c9af76 intel/fs: bump max SIMD size for A64 atomics with LSC 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>.
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
 2022-08-24 17:51:40 +00:00
Lionel Landwerlin 407f2beb97 intel/fs: port block a64/surface messages to use LSC 
v2: Fixup block load/store on surfaces/shared-memory (Rohan)

v3: drop write specific size_written case (Rohan)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
 2022-08-24 17:51:40 +00:00
Lionel Landwerlin 37b3601052 intel/fs: switch register allocation spilling to use LSC on Gfx12.5+ 
v2: drop the hardcoded inst->mlen=1 (Rohan)

v3: Move back to LOAD/STORE messages (limited to SIMD16 for LSC)

v4: Also use 4 GRFs transpose loads for fills (Curro)

v5: Reduce amount of needed register to build per lane offsets (Curro)
    Drop some now useless SIMD32 code
    Unify unspill code

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
 2022-08-24 17:51:40 +00:00
Lionel Landwerlin 3c6fa2703d intel/fs: fixup SEND validation check on overlapping src0/src1 
With the following SEND instruction :

   send(1)         nullUD          nullUD          g0UD            0x4200c504                a0.1<0>UD

This instruction although valid but somewhat nonsensical (SEND message
to write at offset contained in NULL register), triggers an error in
the validator.

The restriction is that we cannot have overlapping sources. The
validator not checking the type of register incorrectly thinks that
the null register (offset 0) is the same as g0.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
 2022-08-24 17:51:40 +00:00
Lionel Landwerlin a81ca32f96 intel/fs: remove unused opcode 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
 2022-08-24 17:51:40 +00:00
Lionel Landwerlin aa65f83203 intel/fs: switch compute push constant loads to LSC 
We're now able to load up to 8 GRFs in one send.

v2: Switch to use transpose + vector of up to 64 (Thanks Curro!)

v3: Increase parallelism by not reusing the same register for push
    constant offset (Curro)

v4: Drop dead ADD() instruction (Curro)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
 2022-08-24 17:51:40 +00:00
Caio Oliveira bee2df64d2 intel/compiler: Use fs_reg helpers for GS icp_handle selection 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18221>
 2022-08-24 01:42:23 +00:00
Caio Oliveira b4aff6ab49 intel/compiler: Use fs_reg helpers for TCS icp_handle selection 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18221>
 2022-08-24 01:42:22 +00:00
Caio Oliveira a1b1fdf70d intel/compiler: Rename 8_PATCH to MULTI_PATCH 
Make it clearer we are dealing with multiple patches,
works better in constrast with SINGLE_PATCH.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18151>
 2022-08-24 00:39:57 +00:00
Caio Oliveira 7cd06249b9 intel/compiler: Remove INTEL_DEBUG=tcs8 
For Gen11 and prior, the dispatch mode for TCS was SINGLE_PATCH, and
this debug setting could be used to change it to 8_PATCH (falling back
to SINGLE_PATCH when shader couldn't be in the multi dispatch mode).
However after talking to Ken, seems this debug setting is not really
worth keeping around, so removing it.

For Gen12+ the only option is 8_PATCH, so it was always using that
dispatch mode as before.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18151>
 2022-08-24 00:39:57 +00:00
Lionel Landwerlin 3c78e94ff3 intel/fs: fixup scratch load/store handling on Gfx12.5+ 
We did not handle the operation with data size < 4. It works fine on
all other messages (global/shared). The initial commit was just too
restrictive.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 1e242785c3 ("intel/fs: Implement load/store_scratch on XeHP")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16964>
 2022-08-23 22:19:16 +00:00
Lionel Landwerlin 46a13404c0 intel/fs: fix load_scratch intrinsic 
The selection of the internal opcode to deal with load_scratch is
incorrect.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c643979228 ("intel/fs: Choose memory message type based on bit size")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16964>
 2022-08-23 22:19:16 +00:00
Caio Oliveira 0a2cfa14dd intel/compiler: Make component() work for FIXED_GRF/ARF 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18157>
 2022-08-23 19:52:38 +00:00
Francisco Jerez 6f33b22495 intel/fs: Fix horiz_offset() to handle FIXED_GRFs with non-trivial 2D regions. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18157>
 2022-08-23 19:52:38 +00:00
Eric Engestrom c535434fd9 anv: convert assert into unreachable to avoid fallthrough error 
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18192>
 2022-08-23 18:37:41 +00:00
Jason Ekstrand 7077b72d60 vulkan,anv,dozen: Use VK_IMAGE_LAYOUT_ATTACHMENT_FEEDBACK_LOOP_OPTIMAL_EXT 
This has basically identical semantics to the pseudo-ext enum we were
using before.  Also, now that it's in the actual Vulkan enum, we can get
rid of all the #pragma garbage to avoid compiler warnings.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18084>
 2022-08-23 16:41:55 +00:00
Yonggang Luo 4bfde7954e intel/compiler: Fixes [-Wdeprecated-declarations] in test_eu_validate.cpp 
Warning message:
../src/intel/compiler/test_eu_validate.cpp:96:1: warning: 'InstantiateTestCase_P_IsDeprecated' is deprecated: INSTANTIATE_TEST_CASE_P is deprecated, please use INSTANTIATE_TEST_SUITE_P [-Wdeprecated-declarations]

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18203>
 2022-08-23 15:19:16 +00:00
Yonggang Luo c48f4b70e2 intel/compiler: Fixes [-Wdeprecated-declarations] in test_eu_compact.cpp 
Warning messages:
../src/intel/compiler/test_eu_compact.cpp:238:1: warning: 'InstantiateTestCase_P_IsDeprecated' is deprecated: INSTANTIATE_TEST_CASE_P is deprecated, please use INSTANTIATE_TEST_SUITE_P [-Wdeprecated-declarations]

../src/intel/compiler/test_eu_compact.cpp:256:1: warning: 'InstantiateTestCase_P_IsDeprecated' is deprecated: INSTANTIATE_TEST_CASE_P is deprecated, please use INSTANTIATE_TEST_SUITE_P [-Wdeprecated-declarations]

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18203>
 2022-08-23 15:19:16 +00:00
Caio Oliveira 9fa48eb4cf intel/compiler: Get URB handle in emit_task/mesh_intrinsic functions 
This will make convenient later to keep track of the urb
handles directly in a Task thread payload struct (to be part of
fs_visitor).

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18188>
 2022-08-23 07:39:18 -07:00
Caio Oliveira ead0cfce54 intel/compiler: Call get_mesh_urb_handle one level up in call-stack 
Call it now from a fs_visitor member functions instead of the static
ones.  This will make convenient later to keep track of the urb
handles directly in a Task thread payload struct (to be part of
fs_visitor).

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18188>
 2022-08-23 07:39:18 -07:00
sjfricke c49e328e4f anv: fix assert to build with shader cache disabled 
When setting -Dshader-cache=disabled the build fails due
no member named 'disk_cache' in 'struct anv_physical_device'

Signed-off-by: sjfricke <spencerfricke@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Fixes: 7f1e8230 ("anv: Switch to the new common pipeline cache")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18181>
 2022-08-23 13:35:46 +00:00
Lionel Landwerlin 9027c5df4c anv: remove the LOCAL_MEM allocation bit 
We always want to use local memory if possible, we'll just add the
system memory heap if the buffer needs to be host visible.

v2: Drop some usages of ANV_BO_ALLOC_LOCAL_MEM_CPU_VISIBLE

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17873>
 2022-08-23 13:19:06 +03:00
Lionel Landwerlin a254aff643 anv: prevent trying to mmap non host visible memory 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17873>
 2022-08-23 13:18:06 +03:00
Lionel Landwerlin b8c472c111 anv: fix assert in memory budget code when extension is not supported 
First we should only support the extension if we can support reporting
on all the heaps.

Second we should not run any query code if the extension is not
supported.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: fae88d8791 ("anv: make use of the new smallbar uAPI")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18153>
 2022-08-23 08:51:56 +00:00
Lionel Landwerlin 4ab38112f3 anv: fixup assertions on lowered storage formats 
With VK_FORMAT_B10G11R11_UFLOAT_PACK32 in particular, we're seeing
applications create image views with swizzle = R,G,B,0

But since the format has no alpha channel, the swizzle value for it
does not matter for the equivalence we're trying to verify.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a9edc268b9 ("anv: validate image view lowered storage formats for storage")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18081>
 2022-08-23 08:29:51 +00:00
Lionel Landwerlin d0e8f21100 anv: fix GetPipelineExecutableStatistics for ray tracing pipelines 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e104555851 ("anv: Compile ray-tracing shaders")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18013>
 2022-08-23 09:56:02 +03:00
Mark Janes 468538509f Revert "anv: Do not copy garbage to batch_bo" 
This reverts commit 87b19c68d8.

Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7109
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18202>
 2022-08-23 02:01:57 +00:00
José Roberto de Souza f986a5207c anv: Group all context operations during device creation 
Move all the setup of context to one function making it easier
to read it.
There is no behavior changes here.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18110>
 2022-08-22 22:04:52 +00:00
José Roberto de Souza dbbf2ff12e anv: Nuke anv_execbuf_init() 
We can do designated initialization to initialize needed values
and set the rest to zero.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18110>
 2022-08-22 22:04:52 +00:00
José Roberto de Souza 87b19c68d8 anv: Do not copy garbage to batch_bo 
batch_size is the aligned value so it is >= than the actual number
of bytes in anv_batch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18110>
 2022-08-22 22:04:52 +00:00
José Roberto de Souza 631794b8a9 anv: Only wait for queue sync if execbuf was properly executed 
In case execbuf failed it would block execution until the maximum
timeout if DEBUG_SYNC is enabled.

While at it also removing the shadowing of result that would cause
the function result to not have its values updated in case
vk_sync_wait() returns a error.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18110>
 2022-08-22 22:04:52 +00:00
Caio Oliveira 631b5742d1 intel/compiler: Print more details when fs_visitor::validate() fails 
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18150>
 2022-08-22 18:58:55 +00:00
Yonggang Luo 201a62cbba meson: Use different STRACEDIR folder for intel_devinfo_override_test 
Fixes
--- stderr ---
strace: Can't fopen 'meson-logs/strace/intel_device_info_override_test_120_/log.10613': No such file or directory

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17928>
 2022-08-22 14:18:53 +00:00
Yonggang Luo 12bb9cba8b anv: Fixes struct anv_device::info is not initialized with struct anv_physical_device 
Refactoring the function anv_device_set_physical out, so that it's can be called in unittests

Fixes: 356a60bd6c ("anv: Do not duplicate intel_device_info memory in each logical device")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7092

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: José Roberto de Souza jose.souza@intel.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17928>
 2022-08-22 14:18:53 +00:00
Sami Kyöstilä b936d638ab intel/ds: Update to Perfetto API v28.0 
Perfetto v28.0 changes the naming scheme of generated enum constants.
Update our code to match and roll the version of Perfetto forward
accordingly.

No functional changes.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18056>
 2022-08-19 18:09:43 +00:00
José Roberto de Souza 356a60bd6c anv: Do not duplicate intel_device_info memory in each logical device 
Each logical device can point to its physical device intel_device_info
saving at least one intel_device_info.

This also allow us to set 'const' to avoid values in intel_device_info
being changed by mistake.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17897>
 2022-08-19 16:29:58 +00:00
Marcin Ślusarz 446eeccb1c intel/compiler: fix mesh urb write regression 
Right now even the simplest mesh test (func.mesh.basic.mesh from crucible) fails like this:
ASSERT: Scalar MESH validation failed!
load_payload(16) vgrf11+0.0:F, vgrf8:D
../../src/intel/compiler/brw_fs_validate.cpp:61: inst->dst.offset / REG_SIZE + regs_written(inst) <= alloc.sizes[inst->dst.nr]
Because we try to load 8 regs with LOAD_PAYLOAD in SIMD16 mode.

Fixes: 349a040f68 ("intel/fs: Make logical URB write instructions more like other logical instructions")

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18075>
 2022-08-18 17:48:41 +00:00
Kenneth Graunke 2cea0d6ef6 intel/compiler: Drop variable group size lowering 
This backend lowering code has been dead since the removal of i965 -
nothing in the current source tree ever sets the flag.

This is handled by iris_setup_uniforms() and crocus_setup_uniforms().
Variable group size does not appear to be a feature in anv.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18055>
 2022-08-18 16:17:03 +00:00
Matt Turner 59dca6f6e1 intel/tools: Also look for 'batch' tag 
This changed in the kernel at some point, but I'm not sure when.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18087>
 2022-08-17 02:24:09 +00:00
José Roberto de Souza c5f03288f0 anv: Free vmas in case device creation fails in pthread_mutex_init(&device->mutex 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17961>
 2022-08-16 18:11:58 +00:00
José Roberto de Souza e5923bbdc0 anv: Remove anv_app_info 
Dead-code not used anywhere.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17961>
 2022-08-16 18:11:58 +00:00
José Roberto de Souza d5e5a1a734 anv: Remove duplicated memset() in physical device creation 
device is allocated with vk_zalloc() that zeroes the allocated memory.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17961>
 2022-08-16 18:11:58 +00:00
José Roberto de Souza f3b15143d2 intel: Simply intel_gem_create_context_engines() 
We can use I915_DEFINE_CONTEXT_PARAM_ENGINES() to simply the filling
of engines_param.

As some compilers might not support VLA, defining struct with 64
engines, the maximum that i915 API supports.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17961>
 2022-08-16 18:11:58 +00:00
Kenneth Graunke bb5d09da6c intel/compiler: Use named NIR intrinsic const index accessors 
In the early days of NIR, you had to prod at inst->const_index[]
directly, but a long while back, we added handy accessor functions
that let you use the actual name of the thing you want instead of
memorizing the exact order of parameters.

Also rewrite a comment I had a hard time parsing.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18067>
 2022-08-16 05:44:30 +00:00
Tomeu Vizoso 477412f303 iris/ci: Set FDO_CI_CONCURRENT for all Chromebook jobs 
For some reason we were missing these and that was causing some CPUs to
remain idle, and some boards to have too high load and some tests timing
out occasionally.

Set FDO_CI_CONCURRENT for the number of cores, plus one to account for
GPU and I/O waits.

Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18028>
 2022-08-15 11:40:16 +02:00
Tomeu Vizoso 1bdcf5c099 iris/ci: Test on Jasper Lake Chromebooks 
8 such boards have been added to Collabora's lab, let's run all tests
from the selected set.

Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18028>
 2022-08-15 11:40:12 +02:00
Yonggang Luo 44a64a34bf intel: Fixes compile error of aubinator_viewer.cpp with gcc 
Remove '-Wno-class-memaccess' from cpp_args because clang don't support this option

aubinator_viewer.cpp:1183:39: error: 'void* memset(void*, int, size_t)' clearing an object of non-trivial type 'struct Context'; use assignment or value-initialization instead [-Werror=class-memaccess]
 1183 |    memset(&context, 0, sizeof(context));

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18024>
 2022-08-12 18:06:36 +00:00