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110527 Commits

Author SHA1 Message Date
Samuel Pitoiset
61d24080bb compiler: add new SYSTEM_VALUE_BARYCENTRIC_* 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
 2020-01-29 09:49:50 +00:00
Samuel Pitoiset
15d53d8294 compiler: add PERSP to the existing barycentric system values 
We need the LINEAR versions for AMD_shader_explicit_vertex_parameter.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
 2020-01-29 09:49:50 +00:00
Samuel Pitoiset
5c053cc6ec spirv: add support for SpvDecorationExplicitInterpAMD 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
 2020-01-29 09:49:50 +00:00
Samuel Pitoiset
746e9e5d66 compiler: add a new explicit interpolation mode 
This introduces one more interpolation mode INTERP_MODE_EXPLICIT,
which is needed for AMD_shader_explicit_vertex_parameter.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
 2020-01-29 09:49:50 +00:00
Eduardo Lima Mitev
e6b531af66 turnip: Fix issues in tu_compute_pipeline_create() that may lead to crash 
The shader object is destroyed even if its creation failed. It is also
not destroyed if its compilation or upload fails, leading to leaks.

Finally, tu_compute_pipeline_create() should set output var
pPipeline to VK_NULL_HANDLE if it fails.

Avoids crash on
dEQP-VK.api.object_management.alloc_callback_fail_multiple.compute_pipeline

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3572>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3572>
 2020-01-29 09:25:20 +00:00
Eduardo Lima Mitev
0e11e8ba89 turnip: Remove failed command buffer from pool 
When an error condition occurs during tu_create_cmd_buffer(), the
cmd buffer has already been added to a pool, so the cleanup code should
remove it.

Fixes a crash (assert in tu_device::tu_bo_finish()) in dEQP tests:

dEQP-VK.api.object_management.max_concurrent.command_buffer_primary
dEQP-VK.api.object_management.max_concurrent.command_buffer_secondary

due to pool attempting to destroy an invalid command buffer.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3572>
 2020-01-29 09:25:20 +00:00
Pierre-Eric Pelloux-Prayer
ab54624d0d radeonsi: stop using the VM_ALWAYS_VALID flag 
Allocation all the bo as ALWAYS_VALID means they must all fit in memory
(vram + gtt) at each command submission.
This causes some trouble when the total allocated memory is greater than
the available memory.

Possible solutions:
- being able to tag/untag a bo as ALWAYS_VALID: would require kernel changes
- disable VM_ALWAYS_VALID when memory usage is more than a percentage of the
  available memory
- disable VM_ALWAYS_VALID entirely

v1 of this patch implemented option 2. v2 (this version) implements option 3.

Related issues:
 - https://gitlab.freedesktop.org/drm/amd/issues/607
 - https://gitlab.freedesktop.org/mesa/mesa/issues/1257

It also helps with some piglit tests (-t maxsize -t "max[_-].*size" -t maxuniformblocksize):
instead of crashing the machine, the tests fail cleanly.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2190
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3430>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3430>
 2020-01-29 09:05:04 +01:00
Samuel Pitoiset
b05ac4b158 radv: enable VK_AMD_shader_fragment_mask on GFX6-GFX7 
Works fine.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3603>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3603>
 2020-01-29 08:08:27 +01:00
Kenneth Graunke
baf9327fa1 loader: Check if the kernel driver is i915 before loading iris 
To prevent it from trying to load on say gma500 hardware.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3595>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3595>
 2020-01-28 15:35:09 -08:00
Jordan Justen
2969012d03 anv: Emit CS Stall before Instruction Cache flush for gen12 WA 
Before flushing the instruction cache with a pipe control, we need to
use a CS Stall pipe control.

Ref: GEN:BUG:1409226450
Rework: Add stall-at-scoreboard (Lionel)
Rework: Merge with other anvil pre-invalidate stalls (Lionel)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457>
 2020-01-28 21:57:17 +00:00
Jordan Justen
da03e07cc2 iris: Emit CS Stall before Instruction Cache flush for gen12 WA 
Before flushing the instruction cache with a pipe control, we need to
use a CS Stall pipe control.

Ref: GEN:BUG:1409226450
Rework: Add stall-at-scoreboard (Lionel)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457>
 2020-01-28 21:57:17 +00:00
Erik Faye-Lund
b175effc72 zink: set compareEnable when setting compareOp 
We need to enable compareEnable for compareOp to be valid, and ANV was
recently updated to respect this. So let's update Zink to match.

This fixes the shadow-variants of several piglit regressions, like these:
spec@arb_shader_texture_lod@execution@tex-miplevel-selection
spec@glsl-1.20@execution@tex-miplevel-selection

Fixes: a19cdf989b ("anv: only use VkSamplerCreateInfo::compareOp if enabled")
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3473>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3473>
 2020-01-28 21:04:26 +00:00
Eric Anholt
527a8c345b mesa/st: Fix compiler warnings from INTEL_shader_integer_functions. 
Fixes: 1d165b0548 ("glsl: Add new expressions for INTEL_shader_integer_functions2")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>
 2020-01-28 12:31:03 -08:00
Eric Anholt
096921c878 iris: Silence warning about AUX_USAGE_MC. 
It was recently introduced and not added to iris yet it looks like.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>
 2020-01-28 12:30:48 -08:00
Eric Anholt
05e3ccd8a1 vulkan/wsi: Fix compiler warning when no WSI platforms are enabled. 
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>
 2020-01-28 12:30:48 -08:00
Jason Ekstrand
997040e4b8 intel/mi_builder: Force write completion on Gen12+ 
Otherwise, we have no guarantee that the write actually lands before we
move on to other things.  Doing this on every SDI is probably a bit
harsh but it's safe.  We should figure out a good way to avoid this when
we can.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>
 2020-01-28 18:15:29 +00:00
Jason Ekstrand
06657e1dda anv: Replace one more aux_surface.isl.size_B check 
This one was missed in 41bffe0913.

Fixes: 41bffe0913 "anv: Replace aux_surface.isl.size_B checks with..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>
 2020-01-28 18:15:29 +00:00
Jason Ekstrand
f229579c0a intel/blorp: Handle bit-casting UNORM and BGRA formats 
In f132e0fddf, I attempted to allow BLORP to do CCS_E copies by using
the UNORM formats instead.  However, the old BLORP bit-cast code could
only handle RGBA formats and asserted on anything other than UINT
formats.  The reason we didn't catch this is because it only comes up on
Gen12 platforms which aren't in our normal CI yet.

Fixes: f132e0fddf "intel/blorp: Add support for CCS_E copies with..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>
 2020-01-28 18:15:29 +00:00
Daniel Schürmann
396be00640 aco: fix combine_salu_not_bitwise() when SCC is used 
Previously, we didn't use the SCC bit, and thus, we didn't care about it.
With 'aco: Transform uniform bitwise instructions to 32-bit if possible.'
that changed, so that we have to handle it.

Fixes: 8a32f57fff ('aco: Transform uniform bitwise instructions to 32-bit if possible.')
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3598>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3598>
 2020-01-28 18:14:02 +01:00
Drew Davenport
0d99ff54cc radeonsi: Clear uninitialized variable 
|view| was not initialized leading to flaky test failures in SkQP
test unitTest_ES2BlendWithNoTexture.

Fixes: 029bfa3d25 "radeonsi: add ability to bind images as image buffers"

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3592>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3592>
 2020-01-28 16:29:48 +00:00
Brian Ho
815a603889 anv: Handle unavailable queries in vkCmdCopyQueryPoolResults 
If VK_QUERY_RESULT_WAIT_BIT is not set, there is currently no
special handling of unavailable queries in vkCmdCopyQueryPoolResults,
and anv will write an invalid value for the query result.

This commit updates vkCmdCopyQueryPoolResults for unavailable
queries to return 0 if the VK_QUERY_RESULT_PARTIAL_BIT flag is set
and if not, skip writing altogether.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3586>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3586>
 2020-01-28 15:17:21 +00:00
Brian Ho
af92ce50a7 anv: Properly fetch partial results in vkGetQueryPoolResults 
Currently, fetching the partial results (VK_QUERY_RESULT_PARTIAL_BIT)
of an unavailable occlusion query via vkGetQueryPoolResults can
return invalid values. anv returns slot.end - slot.begin, but in the
case of unavailable queries, slot.end is still at the initial value
of 0. If slot.begin is non-zero, the occlusion count underflows to
a value that is likely outside the acceptable range of the partial
result.

This commit fixes vkGetQueryPoolResults by always returning 0 if the
query is unavailable and the VK_QUERY_RESULT_PARTIAL_BIT is set.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3586>
 2020-01-28 15:17:21 +00:00
Rhys Perry
7edcf4a59d aco: fix rebase error from GS copy shader support 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: f8f7712666 ('aco: implement GS copy shaders')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3601>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3601>
 2020-01-28 13:50:53 +00:00
Tapani Pälli
dd9bf7d291 anv/android: make format_supported_with_usage static 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3532>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3532>
 2020-01-28 14:46:38 +02:00
Tapani Pälli
104744f4df anv/android: setup gralloc1 usage from gralloc0 usage manually 
This cuts away dependency to libgrallocusage.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3532>
 2020-01-28 14:46:25 +02:00
Rhys Perry
03a0d39366 aco: use MUBUF in some situations instead of splitting vertex fetches 
Fixes most of the regressions from splitting vertex fetches in an earlier
commit.

pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 0 -> 0 (0.00 %)
VGPRS: 0 -> 0 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 0 -> 0 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 0 -> 0 (0.00 %)

pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 562696 -> 558344 (-0.77 %)
VGPRS: 395596 -> 393752 (-0.47 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 11600912 -> 11311804 (-2.49 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 101839 -> 102372 (0.52 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
 2020-01-28 11:44:52 +00:00
Rhys Perry
21d2799cee aco: value-number MUBUF instructions 
We will have to do this when we start creating MUBUF instructions for
load_input because NIR might not be able to tell they are identical since
it doesn't know whether two vertex attributes have the same offset.

No pipeline-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
 2020-01-28 11:40:22 +00:00
Rhys Perry
d39f5519a1 aco: handle unaligned vertex fetch on GFX10 
pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 0 -> 0 (0.00 %)
VGPRS: 0 -> 0 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 0 -> 0 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 0 -> 0 (0.00 %)

pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 795000 -> 802368 (0.93 %)
VGPRS: 579632 -> 581280 (0.28 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 17208408 -> 17583652 (2.18 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 145731 -> 145279 (-0.31 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
 2020-01-28 11:40:10 +00:00
Rhys Perry
d9e357e35b aco: skip unused channels at the start when fetching vertices 
pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 161320 -> 161224 (-0.06 %)
VGPRS: 153968 -> 149408 (-2.96 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 4331496 -> 4331308 (-0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 27814 -> 28594 (2.80 %)

pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 161504 -> 161408 (-0.06 %)
VGPRS: 153836 -> 149440 (-2.86 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 4327572 -> 4327604 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 27837 -> 28618 (2.81 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
 2020-01-28 11:40:01 +00:00
Rhys Perry
525b107347 aco: rework vertex fetching a bit 
This will make it easier to skip unused channels at the start and to split
unaligned loads on GFX10.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
 2020-01-28 11:39:57 +00:00
Rhys Perry
4363a1f75b amd/common,radv: move vertex_format_table to ac_shader_util.{h,c} 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
 2020-01-28 11:39:52 +00:00
Jan Zielinski
ab7ac1ffda gallium/swr: fix tessellation state save/restore 
Tessellation state should be saved with TCS/TES state
when binding new state and restored if old state
is set again.

Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3596>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3596>
 2020-01-28 13:55:47 +01:00
Vasily Khoruzhick
fe5267d322 lima: disable early-z if fragment shader uses discard 
We have to disable early-z if fragment shader uses discard,
otherwise we'll get misrendering.

Reported-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3570>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3570>
 2020-01-27 22:35:43 -08:00
Vasily Khoruzhick
650c680545 lima: ppir: always create move and update ld_tex successors for all blocks 
Always create a mov for ld_tex since we can't rely on
ppir_node_has_single_src_succ() if we have multiple blocks. And since
ld_tex successor can be in a different block we have to update their
ppir_src as well.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3564>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3564>
 2020-01-28 01:45:29 +00:00
Vasily Khoruzhick
4a0f62f1fc lima: ppir: don't delete root ld_tex nodes without successors in current block 
We don't clone ld_tex nodes into each block anymore, so ld_tex may have
successors in another block.

Fixes: c8554f849e ("lima/ppir: don't clone texture loads")
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3564>
 2020-01-28 01:45:29 +00:00
Rob Clark
63af27bc76 freedreno/drm: fix invalid-cmdstream-size with older kernels 
A cmdstream of size zero is invalid.  But this can appear in various
places where we emit a pointer to state.  This doesn't show up with
newer kernels (newer than v5.0) which use "softpin", but on earlier
kernels can result in:

  [drm:msm_ioctl_gem_submit [msm]] *ERROR* invalid cmdstream size: 0

Since the pointer value doesn't matter in these cases, the easy solution
is just to not emit a cmds table entry in this case.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2805>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2805>
 2020-01-28 00:09:34 +00:00
Marek Olšák
0c154d9e2d Revert "winsys/amdgpu: Re-use amdgpu_screen_winsys when possible" 
This reverts commit b60f5cbc15.

This fixes dmesg errors and X freezes:
[   29.543096] amdgpu 0000:0c:00.0: No GEM object associated to handle 0x00000009, can't create framebuffer
[   29.543103] amdgpu 0000:0c:00.0: No GEM object associated to handle 0x00000009, can't create framebuffer
 2020-01-27 17:48:42 -05:00
Marek Olšák
ba06c7620f Revert "winsys/amdgpu: Close KMS handles for other DRM file descriptions" 
This reverts commit 552028c013.

Required by the next reverted commit.
 2020-01-27 17:48:25 -05:00
Jason Ekstrand
993f866d2e anv: Insert holes for non-existant XFB varyings 
Thanks to optimizations, it's possible for varyings to get deleted but
still leave the variable there for nir_gather_xfb_info to find.  If we
get into this case, insert a hole.

Fixes: 36ee2fd61c "anv: Implement the basic form of..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3520>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3520>
 2020-01-27 20:26:23 +00:00
Jason Ekstrand
68b3bfaa42 intel/genxml: Make SO_DECL::"Hole Flag" a Boolean 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3520>
 2020-01-27 20:26:23 +00:00
Sagar Ghuge
a27542c5dd intel/compiler: Clear accumulator register before EOT 
v2: (Francisco Jerez)
- Drop vec4 changes.
- Handle explicit acc0 operand and implicit one.
- Make sure instruction is SIMD16, prediction is off and default mask
  control set to true.

v3: (Francisco Jerez)
- Clear accumulator only when it's written.
- Use BRW_MASK_DISABLE instead of true.
- Use correct width for brw_acc_reg().
- Fix last_inst_offset.

v4: (Francisco Jerez)
- Don't check for last instruction for accummulator write.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3376>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3376>
 2020-01-27 19:48:11 +00:00
Alyssa Rosenzweig
480cf7d9bf pan/midgard: Remove float_bitcast 
Now unused.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3588>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3588>
 2020-01-27 13:37:36 -05:00
Samuel Pitoiset
83e1fa87a7 radv: do not allow sparse resources with multi-planar formats 
It's unsupported.

Fixes some fails or hangs with
dEQP-VK.sparse_resources.image_sparse_binding.*

Cc: 19.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3581>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3581>
 2020-01-27 15:47:49 +00:00
Boris Brezillon
24360966ab panfrost/midgard: Prettify embedded constant prints 
Until now, embedded constants were printed as all 32 bits integer or
floats, but the compiler can pack constant from different types if
severa instructions with different reg_mode and native type refer to
the constant register. Let's implement something smarter so users don't
have to do a manual conversion when looking at a trace.

Note that 8-bit constants are not decoded yet, as we're not sure how
the writemask is encoded in that case.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3536>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3536>
 2020-01-27 15:24:54 +00:00
Boris Brezillon
aa973fc14e panfrost/midgard: Add a condense_writemask() helper 
This way we can convert an 8-bit writemask (Midgard specific
representation) into the more common 1-bit/component representation.

8-bit mode is not supported yet, as we're not sure how the writemask is
encoded for this mode.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3536>
 2020-01-27 15:24:54 +00:00
Rhys Perry
2dc63d39d3 aco: fix literal application with v_cndmask_b32/v_addc_co_u32/etc 
No pipeline-db changes

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 0be7409069 ('aco: rewrite literal combining')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3541>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3541>
 2020-01-27 14:50:37 +00:00
Rhys Perry
827681f921 aco: always add sgprs to sgpr_ids when choosing literals 
Even if it's a literal, we should add this to sgpr_ids.
No pipeline-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 0be7409069 ('aco: rewrite literal combining')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3541>
 2020-01-27 14:50:37 +00:00
Rhys Perry
92970adb4b aco: fix operand to scc when selecting SGPR ufind_msb/ifind_msb 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa78 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3541>
 2020-01-27 14:50:37 +00:00
Rhys Perry
e6c90e4af9 aco: fix WaR check for >64-bit FLAT/GLOBAL instructions 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 5986e0019 ('aco: improve WAR hazard workaround with >64bit stores')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3541>
 2020-01-27 14:50:37 +00:00
Alyssa Rosenzweig
8784062abb pan/midgard: Handle tag 0x4 as texture 
Used for barriers which work as texture ops.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3580>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3580>
 2020-01-27 13:38:41 +00:00