41ee836c9a
intel: Add and use intel_gem_can_render_on_fd()
...
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19425 >
2022-11-07 17:22:14 +00:00
dfd20f002f
intel: Add and use intel_gem_get_param()
...
Again sharing the same function across all Intel drivers.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19425 >
2022-11-07 17:22:14 +00:00
fd14fcb9f9
intel: Add and use intel_gem_get_context_param()
...
Again sharing the same function across all Intel drivers.
There is still two additional DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
calls, one in intel/dev and other in perf.
The first one can't call intel_gem_get_context_param() because of the
build order of libs and the second one because it sets the size
parameter.
Will revisit those calls in future but this is already an improvement.
v2:
- using intel_gem_get_context_param() for the recently added query for
I915_CONTEXT_PARAM_PROTECTED_CONTENT
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18974 >
2022-11-03 21:01:30 +00:00
39486661e9
intel: Add and use intel_gem_set_context_param()
...
Again sharing the same function across all Intel drivers.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18974 >
2022-11-03 21:01:30 +00:00
6ae6921216
intel: Add and use intel_gem_destroy_context()
...
Again sharing the same function across all Intel drivers.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18974 >
2022-11-03 21:01:30 +00:00
f928ead625
intel: Add and use intel_gem_create_context()
...
Add intel_gem_create_context() to common/intel_gem.c/h and use it
on Iris, Crocus, ANV and HASVK.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18974 >
2022-11-03 21:01:30 +00:00
ce4a7e7d40
intel: Refactor intel_gem_create_context_engines()
...
This function was returning a int but there was no meaninfull errno
code being returned, also context_id is a uint32_t what would be
problematic if i915 even returned 2147483648(-1).
So here changing the return type and add context_id pointer parameter.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18974 >
2022-11-03 21:01:30 +00:00
5f7c2b0e16
intel/common: Add and use intel_gem_create_context_ext()
...
v2:
- added flag mask bit to enable context protected and recoverable
v3:
- added enum intel_gem_create_context_flags
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18974 >
2022-11-03 21:01:30 +00:00
aa4ac5ff8b
utils: Merge util/debug.* into util/u_debug.* and remove util/debug.*
...
Rename env_var_as_unsigned() -> debug_get_num_option(), because duplicate
Rename env_var_as_bool() -> debug_get_bool_option(), because duplicate
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7177
Signed-off-by: Illia Abernikhin <illia.abernikhin@globallogic.com >
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com >
Reviewed-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19336 >
2022-11-02 07:25:39 +00:00
2bc82581ad
anv: add support for mesh shading in INTEL_MEASURE
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19344 >
2022-10-27 15:03:28 +00:00
ed7d64962e
intel/common: add detection of protected context support
...
v2: Add anv bits
Fix missing i915 extension chaining helper
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8092 >
2022-10-27 10:53:18 +00:00
86c9aa6bfe
intel: Add and use intel_engines_class_to_string()
...
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18975 >
2022-10-15 20:04:51 +00:00
772dfd60ad
intel: Convert i915 engine type to intel in tools/ common/ and ds/
...
This ones were left to be done after initial conversion.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18975 >
2022-10-15 20:04:51 +00:00
5269d91efc
intel: Convert missing i915 engine types to intel
...
This convertions were missed due to bad rebased in my end, sorry.
Fixes: 03b959286ejose.souza@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18975 >
2022-10-15 20:04:51 +00:00
03b959286e
intel: Make engine related functions and types not i915 dependent
...
There is too much i915_drm.h code spread, this patch start to fix that
by re-organizing engine related code.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18942 >
2022-10-04 18:35:50 +00:00
1e87834980
intel: Share code to read render timestamp
...
Timestamp read is not in any hot path so there is no down-sides in
share the same function between iris, crocus, anv and hasvk.
Also while at it also dropping the functions to read MMIO from kernel,
the only use is read render timestamp so we don't need it.
v2:
- fix compilaton of ds
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18920 >
2022-10-03 06:26:50 -07:00
3beb088490
intel/mi_builder: allow half GP registers for dereferencing
...
Some of the GRL metakernels will generate 64bit value in a register,
then use only half of that as the last operation on that value.
v2: Add comment (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970 >
2022-09-28 05:38:36 +00:00
24a4a3bbbb
intel/mi_builder: Add a helper for incrementing reference counts
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Acked-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970 >
2022-09-28 05:38:36 +00:00
b7296e11ae
intel/mi_builder: add a way to reserve a register
...
Will be useful for GRL metakernels.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Acked-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970 >
2022-09-28 05:38:36 +00:00
f446f7a769
intel/l3: Use L3 full-way allocation setting for gfx12.5 (DG2, MTL)
...
For now we use an empty set of L3 config settings on DG2 & MTL, which
will cause the L3 programming to set L3FullWayAllocationEnable.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18770 >
2022-09-23 12:49:37 -07:00
89d2cdad37
intel/dev: Adjust prefetch_size values for MTL engines
...
MTL has different CS prefetch sizes for each CS type.
So here replacing the cs_prefetch_size in intel_device_info struct
by a function that takes as argument the i915 engine class.
Fixes:
- func.cmd-buffer.small-secondaries.q0
- dEQP-VK.multiview.secondary_cmd_buffer.*
- Several other VK CTS tests that uses secondary_cmd_buffer
v2:
- renamed to intel_device_info_get_engine_prefetch() (Jordan)
v3:
- renamed to intel_device_info_calc_engine_prefetch()
- store each engine class prefetch in intel_device_info
BSpec: 45718
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18597 >
2022-09-22 02:14:47 +00:00
8d66c45290
intel/common: clamp sample location coordinate range
...
Applications may use out-of-range values, driver is responsible for
clamping to implementation-dependent sample location coordinate
range.
Without clamp we hit assert when packing 3DSTATE_SAMPLE_PATTERN if
application attempts to use bigger value than 0.9375.
util_bitpack_ufixed: Assertion `min <= v && v <= max' failed.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18696 >
2022-09-21 04:05:45 +00:00
356a60bd6c
anv: Do not duplicate intel_device_info memory in each logical device
...
Each logical device can point to its physical device intel_device_info
saving at least one intel_device_info.
This also allow us to set 'const' to avoid values in intel_device_info
being changed by mistake.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Acked-by: Jordan Justen <jordan.l.justen@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17897 >
2022-08-19 16:29:58 +00:00
f3b15143d2
intel: Simply intel_gem_create_context_engines()
...
We can use I915_DEFINE_CONTEXT_PARAM_ENGINES() to simply the filling
of engines_param.
As some compilers might not support VLA, defining struct with 64
engines, the maximum that i915 API supports.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17961 >
2022-08-16 18:11:58 +00:00
1aeb11cde1
intel: protect against empty invalidate ranges
...
It's legal for an application to call vkInvalidateMappedMemoryRanges()
/ vkFlushMappedMemoryRanges() with zero sized ranges.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: b91971c240https://gitlab.freedesktop.org/mesa/mesa/-/issues/6852
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17481 >
2022-07-13 01:33:27 +00:00
6787c96039
intel/decoder: Use util_mask_sign_extend()
...
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17214 >
2022-07-06 11:23:18 +00:00
72e9843991
intel/compiler: Introduce a new brw_isa_info structure
...
This structure will contain the opcode mapping tables in the next
commit. For now, this is the mechanical change to plumb it into all
the necessary places, and it continues simply holding devinfo.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309 >
2022-06-30 23:46:35 +00:00
3dc6a98d78
intel/common: allocate space for at least one task urb
...
Fixes: c93cbc77f7lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16196 >
2022-06-27 14:14:41 +00:00
f4386b81e6
intel: fix typos found by codespell
...
Acked-by: David Heidelberg <david.heidelberg@collabora.com >
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17191 >
2022-06-27 10:20:55 +00:00
a1a5f6430a
intel: provide a callback to clean up after intel_measure_gather
...
The caller may have passed ownership of intel_measure_batch structures
to intel_measure until they are ready to be gathered. The caller
needs a notification when rendering is complete and snapshots have
been processed, so it can free the resources that measure the batch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16571 >
2022-06-16 02:58:08 +00:00
c4c096e66e
intel: relax assertion in INTEL_MEASURE
...
It is possible that a secondary command buffer was submitted with no
renders in it. For that case, no timestamp will be collected. Only
verify that timestamps if the index is nonzero.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16571 >
2022-06-16 02:58:08 +00:00
3c53c6b247
intel: parse intel_measure environment without side effects
...
If an application links agaist both iris and anv, they will clash when
parsing the INTEL_MEASURE environment variable.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16571 >
2022-06-16 02:58:08 +00:00
60e29fc7c5
intel/gem: Add support for I915_ENGINE_CLASS_COMPUTE
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395 >
2022-06-15 08:58:20 +00:00
ffb0c97caf
intel: Build mi_builder_test whenever build-tests is set
...
Previously `install-intel-gpu-tests` controlled this, but now
`install-intel-gpu-tests` will only be used to decide if it should be
installed.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16902 >
2022-06-07 18:26:02 +00:00
8381f64251
intel: Fix build of mi_builder_tests by including c99_compat.h
...
We need this so C++ will understand "restrict" which is used in the
genxml output.
Fixes: 9f717b5f23jordan.l.justen@intel.com >
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16899 >
2022-06-07 08:27:19 +00:00
b637f6c3db
intel/decoder: Fix binding table pointer decoding with large offsets
...
XeHP supports a 20:5 pointer format, so the offset can legitimately
be more than UINT16_MAX. Likewise, with 256B binding table mode on
Icelake/Tigerlake, we might have 18:8 pointers that exceed UINT16_MAX.
Thanks to Felix DeGrood for catching this!
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16538 >
2022-05-17 08:52:00 +00:00
b07c215c35
intel: fix URB programming for GT1s
...
We're missing a programming restriction.
Hopefully fixing
dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_1.* on
Gfx9atoms
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6216
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >.
Tested-by: Mark Janes <markjanes@swizzler.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15596 >
2022-04-17 21:24:17 +00:00
1407a4db69
intel/batch-decoder: Fix uninitialized scalar variables
...
CID: 1498516
CID: 1498560
Signed-off-by: Vitalii Lomaka <vitalii.lomaka@globallogic.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15685 >
2022-04-08 18:35:34 +00:00
9bc97e4fc1
intel/decoder: Fix decoder handling of binding table pool alloc on XeHP
...
3DSTATE_BINDING_TABLE_POOL_ALLOC no longer has a "Binding Table Pool
Enable" bit. It is always enabled.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15625 >
2022-03-29 02:35:54 -07:00
3bd9b25060
intel: change INTEL_MEASURE output to microseconds
...
Change time event durations from ns -> us. Microseconds are easier
to work with.
Reviewed-by: Mark Janes <markjanes@swizzler.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15348 >
2022-03-17 22:14:42 +00:00
2e6d14cc7b
intel: increase INTEL_MEASURE batch/buffer sizes
...
Increase default batch_size and buffer_size from 16 -> 64. These
are sized to be big enough to service most games. As games have
become more demanding, larger sizes become necessary.
Reviewed-by: Mark Janes <markjanes@swizzler.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15348 >
2022-03-17 22:14:42 +00:00
12d815bcac
intel/guardband: Take min/max instead of total size
...
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14961 >
2022-03-16 13:13:45 -05:00
dbcdededb2
intel: Add missing dep of gen_*_header.py on utils.py.
...
Reviewed-by: Dylan Baker <dylan@pnwbakers.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14725 >
2022-02-02 11:21:57 -08:00
c93cbc77f7
intel/common: Add helper for URB allocation in Mesh pipeline
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
b01c73fd0a
intel: Add INTEL_URB_DEREF_BLOCK_SIZE_MESH
...
And corresponding value in XML.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
8599ded193
intel: Only reserve space for Compute Engine out of URB in Gfx12LP
...
Reviewed-by: Francisco Jerez <currojerez@riseup.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14756 >
2022-01-28 14:52:17 -08:00
79b199b333
intel: Allow copy engine class in intel_gem_create_context_engines()
...
I want to use I915_ENGINE_CLASS_COPY in iris.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687 >
2022-01-24 23:27:25 +00:00
695ba644ab
intel/gem: Return length from intel_i915_query_alloc
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13866 >
2022-01-19 00:29:35 +00:00
69df00b33b
intel/ds: reuse intel_ioctl()
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Acked-by: Antonio Caggiano <antonio.caggiano@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13996 >
2022-01-14 20:17:44 +00:00
14a4600b62
intel: add swizzle flag into driver uuid
...
Suggested by Lionel Landwerlin, we add has_bit6_swizzle as
another input when computing driver uuid.
Also fix miscalculation of the length of driver tag.
Signed-off-by: Jianxun Zhang <jianxun.zhang@linux.intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13936 >
2022-01-13 03:09:36 +00:00
José Roberto de Souza