Commit Graph

85652 Commits

Author SHA1 Message Date
Chad Versace f7e36f9f66 isl: Move it a standalone directory
The plan all along was to eventualyl move isl out of the Vulkan
directory, because I intended i965 and anvil to share it.

A small problem I encountered when attempting to write unit tests for
isl precipitated the move.  I discovered that it's easier to get isl
unit tests to build if I remove the extra, unneeded dependencies
injected by src/vulkan/Makefile.am. And the easiest way to remove those
unneeded dependencies is to move isl out of src/vulkan. (Unit tests come
in subsequent commits).
2015-12-15 08:45:49 -08:00
Nicolai Hähnle c8d9d289ff radeonsi: fix perfcounter selection for SI_PC_MULTI_BLOCK layouts
The incorrectly computed register count caused lockups.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-12-15 11:23:40 -05:00
Nicolai Hähnle 149d049676 gallium/radeon: remove unnecessary test in r600_pc_query_add_result
This test is a left-over of the initial development. It is unneeded and
misleading, so let's get rid of it.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-12-15 11:23:40 -05:00
Nicolai Hähnle 819543adb4 mesa/main: use BITSET_FOREACH_SET in perf_monitor_result_size
This should make the code both faster and slightly clearer.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2015-12-15 11:23:40 -05:00
Emil Velikov 9c0773958e docs: add news item and link release notes for 11.1.0
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2015-12-15 15:07:03 +00:00
Emil Velikov b8394ef3df docs: add sha256 checksums for 11.0.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 525f3c2c28cd083b37e1f6a27f503af1c4781141)
2015-12-15 15:07:02 +00:00
Emil Velikov 5497e119a5 docs: Update 11.1.0 release notes
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 5a616125acf0ac043d2d44b7a8e804739d55014e)
2015-12-15 15:07:02 +00:00
Rob Clark e677b3047b freedreno/a4xx: fix fragcoord.z + fragdepth
It seems like disabling earlyz on a4xx also, by defaults, disables
fragcoord.z to the FS.  For frag shaders that both read fragcoord(.z)
and write fragdepth, we need to set some extra bits to prevent a
lockup.

This lets us get rid of the hack of disabling fragcoord.z (which
prevented 0ad from lockups, but resulted in rendering corruption).  Also
fixes fbo-depth-sample-compare.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-12-15 09:40:54 -05:00
Rob Clark cad0920d11 freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-12-15 09:39:10 -05:00
Rob Clark 249b2be3bc freedreno/ir3/cmdline: don't dump nir by default
By default we only want the disasm dumped, which we get anyways.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-12-15 09:39:10 -05:00
Christian König 10b7a7c344 st/va: remove nonesense HEVC picture id handling
The picture id in this case is a VA-API surface handle, checking
for a certain value can't be correct.

Signed-off-by: Christian König <christian.koenig@amd.com>
2015-12-15 11:25:02 +01:00
Chris Forbes af5ca43f26 i965: Allocate URB space for HS and DS stages when required.
v2: (by Ken, incorporating feedback from Matt Turner):
- Rewrite the push constant allocation code to be clearer.
- Only apply the minimum VS entries workaround on Gen 8.

v3: (by Ken)
- Fix a bug in v2 where we failed to allocate the full push constant
  space when the number of enabled stages didn't divide the available
  push constant space evenly.  (Any left over space is now allocated
  to the PS, as it was in v1.)
- Fix an off-by-one error in v2's number of enabled stages calculation.
- Use DIV_ROUND_UP for nicer formatting.
- Line wrapping fixes.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-12-15 02:16:14 -08:00
Jason Ekstrand 8224571ef8 vec4/generator: Actually pass the sampler into generate_tex
This is an artifact of the way the separate samplers/textures series ended
up getting sent out and rebased.  This should fix a number of CTS tests
involving geometry shaders.
2015-12-14 21:13:52 -08:00
Jordan Justen 7edcc59a7b anv: Rename gs_vec4 to gs_kernel
The code generated may be vec4 or simd8 depending on how we start the
compiler.

To run the GS in SIMD8, set the INTEL_SCALAR_GS environment variable.
This was added in:

    commit 36fd653817
    Author: Kenneth Graunke <kenneth@whitecape.org>
    Date:   Wed Mar 11 23:14:31 2015 -0700

        i965: Add scalar geometry shader support.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-14 18:23:14 -08:00
Jordan Justen a3c5c339a8 nir/spirv_to_nir: Use a minimum of 1 for GS invocations
glslang is giving us 0, which causes the SIMD8 GS compile to hit an
assert.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-14 18:23:14 -08:00
Timothy Arceri 8c0963f9d3 docs: mark input/output block locations as DONE
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-12-15 13:10:51 +11:00
Timothy Arceri 0aeb9b3e5e glsl: add support for explicit locations inside interface blocks
This change also adds explicit location support for structs and interfaces which
is currently missing in Mesa but is allowed with SSO and GLSL 1.50+.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-12-15 13:10:44 +11:00
Timothy Arceri 183c606066 glsl: simplify interface matching
This makes the code easier to follow, should be more efficient
and will makes it easier to add matching via explicit locations
in the following patch.

This patch also replaces the hash table with the newer
resizable hash table this should be more suitable as the table
is likely to only contain a small number of entries.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-12-15 13:10:39 +11:00
Roland Scheidegger 8e264765a4 draw: remove clip_vertex from vertex header
vertex header had both clip_pos and clip_vertex.
We only really need one (clip_pos) because the draw llvm shader would
overwrite the position output from the vs with the viewport transformed.
However, we don't really need the second one, which was only really used
for gl_ClipVertex - if the shader didn't have that the values were just
duplicated to both clip_pos and clip_vertex. So, just use this from the vs
output instead when we actually need it.
Also change clip debug to output both the data from clip_pos and the
clipVertex output (if available).
Makes some things more complex, some things less complex, but seems more
easy to understand what clipping actually does (and what values it uses
to do its magic).

Reviewed-by: Brian Paul <brianp@vmware.com
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-12-15 02:03:40 +01:00
Roland Scheidegger 1775400a20 draw: use clip_pos, not clip_vertex for the fake guardband xy point clipping
Seems obvious now this should use the data from position and not clip_vertex
(albeit might not really make a difference).

Reviewed-by: Brian Paul <brianp@vmware.com
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-12-15 02:03:40 +01:00
Roland Scheidegger 8575ddb644 draw: rename vertex header members
clip -> clip_vertex and pre_clip_pos -> clip_pos.
Looks more obvious to me what these values actually represent (so use
something resembling the vs output names).

Reviewed-by: Brian Paul <brianp@vmware.com
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-12-15 02:03:40 +01:00
Roland Scheidegger 1b22815af6 draw: don't pretend have_clipdist is per-vertex
This is just for code cleanup, conceptually the have_clipdist really
isn't per-vertex state, so don't put it there (just dependent on the
shader). Even though there wasn't really any overhead associated with
this, we shouldn't store random shader information in the vertex header.

Reviewed-by: Brian Paul <brianp@vmware.com
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-12-15 02:03:40 +01:00
Roland Scheidegger 9e3f2af3c3 draw: use position not clipVertex output for xyz view volume clipping
I'm pretty sure this should use position (i.e. pre_clip_pos) and not
the output from clipVertex. Albeit piglit doesn't care. It is what we
use in the clip test, and it is what every other driver does (as they
don't even have clipVertex output and lower the additional planes to
clip distances).

Reviewed-by: Brian Paul <brianp@vmware.com
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-12-15 02:03:40 +01:00
Jason Ekstrand f46544dea1 anv: Fix CUBE storage images 2015-12-14 16:59:59 -08:00
Jason Ekstrand 783a21192c anv: Add support for storage texel buffers 2015-12-14 16:51:12 -08:00
Jason Ekstrand 1f98bf8da0 anv: Pass an isl_format into fill_buffer_surface_state 2015-12-14 16:14:20 -08:00
Jason Ekstrand 091b6156dd i965/fs: Push small uniform arrays
Unfortunately, this also means that we need to use a slightly different
algorithm for assign_constant_locations.  The old algorithm worked based on
the assumption that each read of a uniform value read exactly one float.
If it encountered a MOV_INDIRECT, it would immediately bail and push the
whole thing.  Since we can now read ranges using MOV_INDIRECT, we need to
be able to push a series of floats without breaking them up.  To do this,
we use an algorithm similar to the on in split_virtual_grfs.
2015-12-14 15:58:10 -08:00
Jason Ekstrand 63c313de84 i965/fs: Rename demote_pull_constants to lower_constant_loads 2015-12-14 15:58:10 -08:00
Jason Ekstrand 75f33a6420 i965/vec4: Get rid of the uniform_size array 2015-12-14 15:58:09 -08:00
Jason Ekstrand eb76f226cf i965/fs: Use UD type for offsets in VARYING_PULL_CONSTANT_LOAD 2015-12-14 15:58:09 -08:00
Jason Ekstrand a487f0284f i965/vec4: Use MOV_INDIRECT instead of reladdr for indirect push constants
This commit moves us to an instruction based model rather than a
register-based model for indirects.  This is more accurate anyway as we
have to emit instructions to resolve the reladdr.  It's also a lot simpler
because it gets rid of the recursive reladdr problem by design.

One side-effect of this is that we need a whole new algorithm in
move_uniform_array_access_to_pull_constants.  This new algorithm is much
more straightforward than the old one and is fairly similar to what we're
already doing in the FS backend.
2015-12-14 15:58:09 -08:00
Jason Ekstrand 46f5396846 i965/vec4: Inline get_pull_constant_offset
It's not really doing enough anymore to justify a helper function.
2015-12-14 15:58:09 -08:00
Jason Ekstrand 9c36c40845 i965/fs: Get rid of the param_size array 2015-12-14 15:58:09 -08:00
Jason Ekstrand 9024353db3 i965/fs: Stop relying on param_size in assign_constant_locations
Now that we have MOV_INDIRECT opcodes, we have all of the size information
we need directly in the opcode.  With a little restructuring of the
algorithm used in assign_constant_locations we don't need param_size
anymore.  The big thing to watch out for now, however, is that you can have
two ranges overlap where neither contains the other.  In order to deal with
this, we make the first pass just flag what needs pulling and handle
assigning pull constant locations until later.
2015-12-14 15:58:09 -08:00
Jason Ekstrand 9f46af9e41 i965/fs: Get rid of reladdr
We aren't using it anymore.
2015-12-14 15:58:09 -08:00
Jason Ekstrand a3cd95a884 i965/fs: Use MOV_INDIRECT for all indirect uniform loads
Instead of using reladdr, this commit changes the FS backend to emit a
MOV_INDIRECT whenever we need an indirect uniform load.  We also have to
rework some of the other bits of the backend to handle this new form of
uniform load.  The obvious change is that demote_pull_constants now acts
more like a lowering pass when it hits a MOV_INDIRECT.
2015-12-14 15:58:09 -08:00
Jordan Justen c4219bc6ff anv/cmd_buffer: Gen 8 requires 64 byte alignment for push constant data
See MEDIA_CURBE_LOAD, CURBE Data Start Address & CURBE Total Data Length

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-14 15:39:07 -08:00
Jason Ekstrand f0313a5569 anv: Add initial support for cube maps
This fixes 486 cubemap CTS tests.
2015-12-14 15:36:30 -08:00
Kenneth Graunke 77cc2666b1 i965: Use DIV_ROUND_UP() in gen7_urb.c code.
This is a newer convention, which we prefer over ALIGN(x, n) / n.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-12-14 14:56:14 -08:00
Kenneth Graunke 9f0944d15b i965: Make TES inputs match TCS outputs.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-14 14:48:29 -08:00
Kenneth Graunke 4fac950010 i965: Force VS -> TCS varyings to use the SSO VUE map layout.
The compact VUE map only works when varying packing is in use.
Unfortunately, varying packing is disabled for TCS inputs.

This is needed to fix Piglit's tcs-input-read-array-interface test.

v2: Make lines fit in 80 columns (caught by Jordan Justen).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-14 14:48:18 -08:00
Kenneth Graunke bee42cc1f7 i965: Handle TCS outputs and TES inputs.
TCS outputs and TES inputs both refer to a common "patch URB entry"
shared across all invocations.  First, there are some number of
per-patch entries.  Then, there are per-vertex entries accessed via
an offset for the variable and a stride times the vertex index.

Because these calculations need to be done in both the vec4 and scalar
backends, it's simpler to just compute the offset calculations in NIR.
It doesn't necessarily make much sense to use per-vertex intrinsics
afterwards, but that at least means we don't lose the per-patch vs.
per-vertex information.

v2: Use is_input/is_output helpers (suggested by Jordan Justen).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-14 14:48:13 -08:00
Kenneth Graunke 31140d097a i965: Handle TCS inputs and TES outputs.
TES outputs work exactly like VS outputs, so we can simply add a case
statement for those.

TCS inputs are very similar to geometry shaders - they're arrays of
per-vertex data.  We use the same method I used for the scalar GS
backend.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-14 14:48:07 -08:00
Kenneth Graunke 1f46163acb i965: Add tessellation shader VUE map code.
Based on a patch by Chris Forbes, but largely rewritten by Ken.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-14 14:48:01 -08:00
Kenneth Graunke 9f3917bf37 i965: Fix partial variable access for geometry shaders in SSO mode.
Without varying packing, if a VS writes a compound variable, and the GS
only reads part of it, the base location of the variable may not
actually be in the VUE map.

To cope with this, we do lowering in terms of varying slots, add any
constant offsets to the base, and then do the VUE map remapping.  This
ensures we only look up VUE map entries for slots which actually exist.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-12-14 14:39:38 -08:00
Kenneth Graunke 8c4deb10df i965: Separate base offset/constant offset combining from remapping.
My tessellation branch has two additional remap functions.  I don't want
to replicate this logic there.

v2: Handle inputs/outputs separately (suggested by Jason Ekstrand).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-12-14 14:39:34 -08:00
Jason Ekstrand 7ba70b1b51 nir: Add another index to load_uniform to specify the range read 2015-12-14 14:28:31 -08:00
Jason Ekstrand 4115648a6b i965/vec4: Add support for SHADER_OPCODE_MOV_INDIRECT 2015-12-14 14:28:31 -08:00
Jason Ekstrand 2f1455dbb0 i965/fs: Add support for MOV_INDIRECT on pre-Broadwell hardware
While we're at it, we also add support for the possibility that the
indirect is, in fact, a constant.  This shouldn't happen in the common case
(if it does, that means NIR failed to constant-fold something), but it's
possible so we should handle it.
2015-12-14 14:28:31 -08:00
Jason Ekstrand 4be9a1c7bb i965/fs: Fix regs_read() for MOV_INDIRECT with a non-zero subnr
The subnr field is in bytes so we don't need to multiply by type_sz.
2015-12-14 14:28:31 -08:00