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Author SHA1 Message Date
Benjamin Lee
588cfcaec7 nak: Legalize a bunch of instructions for SM50 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26114>
 2023-12-07 00:36:35 +00:00
Faith Ekstrand
bbd2de34c5 nak: Rework the SM50 encoding of isetp 
Drop the ALU stuff and hand-encode it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26114>
 2023-12-07 00:36:35 +00:00
Faith Ekstrand
e404877a02 nak: Use OpLop2 and OpPSetP pre-SM70 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26114>
 2023-12-07 00:36:35 +00:00
Faith Ekstrand
36e80caac9 nak: Rename LogicOp to LogicOp3 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26114>
 2023-12-07 00:36:35 +00:00
Faith Ekstrand
93b6c43725 nak: Rewrite SM50 encode_fadd to not use encode_alu 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26114>
 2023-12-07 00:36:35 +00:00
Faith Ekstrand
4ab2d5c4ff nak: Rework set_src_imm20 in nak_encode_sm50 
Rename it to set_src_i20 and fix the assert to allow negative signed
values.  Also, add a new set_src_f20 helper with the correct semantics
for float immediates.  Finally, get rid of some bogus shifting in the
ALU code.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26114>
 2023-12-07 00:36:35 +00:00
Faith Ekstrand
a80ce982d4 nak: Initial WIP SM50 backend 
Only encode some instructions.

some TODO:
- SM50 specific legalizer
- Cleaner ALU encoding (there is multiple form of encoding depending of
  the instruction)

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26114>
 2023-12-07 00:36:35 +00:00
Benjamin Lee
9af7639e4b nak: make sm available in builders 
This is needed for the 'sel' builder method, which should emit different
instrs on SM50 versus SM75.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26114>
 2023-12-07 00:36:35 +00:00
Faith Ekstrand
40127e881f nak: Split legalize into per-SM functions 
We still have common code to handle the multiple vector source case
because that's required for RA correctness but everything else is
pretty much per-SM.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26114>
 2023-12-07 00:36:35 +00:00
Jesse Natalie
d157cd7442 microsoft/clc: One more image lowering fix 
Bindings are not necessarily globally unique, and even the location
where we were trying to read the binding value out of is a union, so
we could be trying to compare binding values against data for other
arg types.

Instead, use the arg metadata offset, which is globally unique and
outside of the union.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26555>
 2023-12-06 23:46:42 +00:00
Faith Ekstrand
03ae261183 nvk: Advertise KHR_shader_integer_dot_product 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26533>
 2023-12-06 23:15:33 +00:00
Faith Ekstrand
eb633b4978 nak: Wire up DP4 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26533>
 2023-12-06 23:15:33 +00:00
Faith Ekstrand
fcf31d9c25 nak: Rework printing of int/float types and rounding modes 
Make the . part of the enum's print like for other things.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26533>
 2023-12-06 23:15:33 +00:00
Faith Ekstrand
adafcacf15 microsoft: Stop claiming dot_4x8_sat support 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26533>
 2023-12-06 23:15:33 +00:00
Faith Ekstrand
d2ffcb6092 nir: Lower [su]dot_4x8_[ui]add_sat to [su]dot_4x8_[ui]add 
Since nir_opt_algebraic runs on its own results, if the driver doesn't
have [su]dot_4x8_[ui]add then the [su]dot_4x8_[ui]add lowering rules
will kick in and lower that to what we had originally.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26533>
 2023-12-06 23:15:33 +00:00
Faith Ekstrand
09fc5e1c4d nir: Split has_[su]dot_4x8 bits into regular and _sat versions 
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26533>
 2023-12-06 23:15:33 +00:00
Faith Ekstrand
03f1b99f50 nak: Restructure for better module separation 
With this commit, NAK now takes on a more Cargo-like structure with
things split better into crates:

 - bitview/
    - lib.rs // Formerly bitview.rs
 - nak/
    - lib.rs // Only pulls stuff into the module
    - api.rs // Formerly nak.rs
    - ...
 - nvfuzz/
    - main.rs // Formerly nvfuzz.rs

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26546>
 2023-12-06 22:41:47 +00:00
Faith Ekstrand
97cd55d065 nak: rustfmt 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26546>
 2023-12-06 22:41:47 +00:00
José Roberto de Souza
5560835fbe anv: Avoid unnecessary intel_flush calls 
Batch bos are always allocated with ANV_BO_ALLOC_HOST_CACHED_COHERENT
so there is no need to do cflush calls.
But if we ever decide to change that anv_bo_needs_host_cache_flush()
will make sure cflush is called.

Outside of batch bos, this patch is also removing the
intel_flush_range() call from anv_QueuePresentKHR because
device->debug_frame_desc is offset of workaround_bo that is also
allocated as ANV_BO_ALLOC_HOST_COHERENT.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26457>
 2023-12-06 22:18:26 +00:00
José Roberto de Souza
9aea879342 anv: Promote bos to host_cached+host_coherent in platforms with LLC 
In platforms with LLC we can promote all bos to cached+coherent
without any performance penality.
On the up side CPU reads can hit cache this way.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26457>
 2023-12-06 22:18:26 +00:00
José Roberto de Souza
a65e982b44 anv: Split ANV_BO_ALLOC_HOST_CACHED_COHERENT into two actual flags 
As suggested by Lionel, here adding ANV_BO_ALLOC_HOST_COHERENT
and with that ANV_BO_ALLOC_HOST_CACHED_COHERENT is now defined by
(ANV_BO_ALLOC_HOST_COHERENT | ANV_BO_ALLOC_HOST_CACHED).

In some callers of anv_device_alloc_bo() was necessary to add
ANV_BO_ALLOC_HOST_COHERENT as no other flag was set and that
was the default behavior up to now.

A change that could look not related is the removal of the
intel_flush_range() in anv_device_init_trivial_batch(), that was done
because trivial_batch_bo is HOST_COHERENT so no flush is necessary.
And it did not made sense to make it ANV_BO_ALLOC_HOST_CACHED_COHERENT
as it was never read in CPU.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26457>
 2023-12-06 22:18:26 +00:00
José Roberto de Souza
0eac6298f2 anv: Fix handling of host_cached_coherent bos in gen9 lp in older kernels 
Kernel versions without DRM_I915_QUERY_MEMORY_REGIONS support will
take a different code path in i915_gem_create() that lacks the
i915_gem_set_caching() call to make cached bos in gen9 lp 1 way
coherent.

Fixes: fc0acf6d90 ("anv: Move i915 specific gem_set_caching to backend")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26457>
 2023-12-06 22:18:26 +00:00
Samuel Pitoiset
e126e82c79 zink/ci: stop running zink-radv-navi31-valve sequentially 
Skipping the tests that OOM seems to fix this.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26544>
 2023-12-06 20:31:24 +00:00
Samuel Pitoiset
bec2928cc2 zink/ci: update list of failures for NAVI31 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26544>
 2023-12-06 20:31:24 +00:00
Samuel Pitoiset
f6dc3429e6 zink/ci: skip more tests that run OOM on NAVI31 
These have been skipped recently, but not for NAVI31 for some reasons.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26544>
 2023-12-06 20:31:24 +00:00
José Roberto de Souza
969af605fe intel/isl: Set mocs.blitter_dst/src for MTL 
This fields are required to be set because those are used by
XY_FAST_COLOR_BLT instruction.
Right now it is not set causing applications to abort because
DestinationMOCS is required to be non-zero.

This fixes at least piglit@ext_external_objects-vk-image-display on MTL.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26502>
 2023-12-06 20:09:04 +00:00
Lionel Landwerlin
4ff1b0f751 anv/video: only report matching memory types for protected sessions 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 794b0496e9 ("anv: enable protected memory")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26519>
 2023-12-06 19:17:17 +00:00
Lionel Landwerlin
e8a96e6ba0 vulkan/runtime: retain video session creation flags 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26519>
 2023-12-06 19:17:17 +00:00
Faith Ekstrand
22c60ea384 nir: Respect variable alignments in lower_vars_to_explicit_types 
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26522>
 2023-12-06 18:37:36 +00:00
Faith Ekstrand
629af540ca spirv: Plumb variable alignments through to NIR 
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26522>
 2023-12-06 18:37:36 +00:00
Juan A. Suarez Romero
47b825c6c5 v3d: include the revision in the device name 
To match what the Vulkan driver does.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26520>
 2023-12-06 18:19:08 +00:00
José Roberto de Souza
1f0a9f853c intel: Sync xe_drm.h take 2 part 3 
Sync xe_drm.h with commit ac7b89571d80 ("drm/xe/uapi: Kill exec_queue_set_property").

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26360>
 2023-12-06 17:35:23 +00:00
Rohan Garg
d1109f67bb iris: Emit EXECUTE_INDIRECT_DRAW when available 
On newer platforms (Arrowlake and above) we can issue a
EXECUTE_INDIRECT_DRAW that allows us to:
  * Skip issuing mi load/store instructions for indirect parameters
  * Skip doing the indirect draw unroll on the CPU side when the
    appropriate stride is passed

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26178>
 2023-12-06 17:09:58 +00:00
Faith Ekstrand
e5b7e16f3b nvk: Implement VK_EXT_texel_buffer_alignment 
These values are taken from the blob.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9618
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26545>
 2023-12-06 16:54:57 +00:00
Samuel Pitoiset
47f666b64b radv: enable extendedDynamicState3AlphaToCoverageEnable on GFX11 
This is now supported and this allows Zink to enable full ds3 mode for
even less stuttering. DXVK also uses dynamic alpha to coverage
sometimes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26250>
 2023-12-06 16:36:16 +00:00
Samuel Pitoiset
bca4ebc3c4 radv: export MRTZ via PS epilogs when alpha to coverage is dynamic on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26250>
 2023-12-06 16:36:16 +00:00
Rhys Perry
0cbe0d2968 nir/loop_analyze: support loops with min/max and non-add incrementation 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26225>
 2023-12-06 15:58:36 +00:00
Rhys Perry
fc1ebc67b1 nir/loop_analyze: support umin and {u,i,f}max 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26225>
 2023-12-06 15:58:36 +00:00
Rhys Perry
9591c36666 nir/loop_analyze: check min compatibility with comparison 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26225>
 2023-12-06 15:58:36 +00:00
Rhys Perry
b6c2a5d48d nir/loop_analyze: fix vector basis/limit/comparison 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26225>
 2023-12-06 15:58:36 +00:00
Rhys Perry
2f46773819 nir/loop_analyze: scalarize try_eval_const_alu 
This is simpler, and users of this function expected scalar anyway.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26225>
 2023-12-06 15:58:36 +00:00
Rhys Perry
7960588413 nir/loop_analyze: skip if basis/limit/comparison is vector 
Replacement in try_eval_const_alu() doesn't work because the replacements
are always scalar. The callers also always give a scalar dest.

This is encountered when compiling a Redout shader under ASan.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Fixes: bc170e895f ("nir/loop_analyze: Use try_eval_const_alu and induction variable basis info")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26225>
 2023-12-06 15:58:36 +00:00
Samuel Pitoiset
13e9e73974 zink/ci: remove skipped tests from the list of expected failures for NAVI31 
These are skipped.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26539>
 2023-12-06 12:28:17 +00:00
Samuel Pitoiset
79cf2b6824 radv: determine and emit SPI_SHADER_Z_FORMAT for PS epilogs 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
 2023-12-06 11:49:31 +00:00
Samuel Pitoiset
4248d0b03a radv,aco: declare PS epilog VGPR arguments for depth/stencil/samplemask 
Depth/stencil/samplemask inputs are first to match
create_fs_jump_to_epilog().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
 2023-12-06 11:49:31 +00:00
Samuel Pitoiset
8b87c985b0 radv: prepare the PS epilog key for exporting MRTZ on RDNA3 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
 2023-12-06 11:49:31 +00:00
Samuel Pitoiset
5b01285cfb radv: determine if MRTZ needs to be exported via PS epilogs 
For GFX11 only.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
 2023-12-06 11:49:31 +00:00
Samuel Pitoiset
b2a37b4304 ac/nir: add an option to skip MRTZ exports in ac_nir_lower_ps() 
On RDNA3, alpha to coverage needs to be exported through MRTZ when
depth, stencil or samplemask are also exported. This option will allow
us to export MRTZ from PS epilogs instead of the main FS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
 2023-12-06 11:49:31 +00:00
Samuel Pitoiset
81eeb157f8 aco: export depth/stencil/samplemask in create_fs_jump_to_epilog() 
This currently has no effects because the store_output instructions
are removed earlier (in ac_nir_lower_ps). Though, this will be needed
for exporting MRTZ from PS epilogs for alpha to coverage on RDNA3.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
 2023-12-06 11:49:31 +00:00
Eric Engestrom
90a77f55de ci: drop containers, builds, and tests from post-merge pipeline 
All these jobs are redundant and a waste of resources:
- the containers have already been built & pushed in the merge pipeline
- the mesa build variants have already all passed
- the driver tests have already all passed

None of these jobs are doing anything useful in this pipeline, but it
costs a factor of 2x to our infrastructure, so let's remove them.

In other words, the only job left in the post-merge pipeline is the
`pages` job that deploys the update to the website.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26451>
 2023-12-06 08:26:04 +00:00