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Lionel Landwerlin 93924ab091 intel/perf: report whether the platform supported 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin fe8e8e5099 intel/perf: add counter category to generated code 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin c36933e081 intel/perf: add helper to compute metrics from counters 
The produced array tells use what metric to enable for a given pass.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin a7890f559b intel/perf: emit counter units in generated code 
We'll use this coming extension.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin d15369332f intel/perf: compute number of passes for a set of counters 
We want to compute the number of passes required to gather performance
data about a set of counters.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin 3f0c4c2afe intel/perf: create a unique list of counters 
For a future extension we want to be able to list the counters. Our
existing sets counters might contain the same counters multiple times.
This is a side effect of the fixed OA counters in the HW. We track
thoses with a mask so that we know when a counter is available from
multiple metrics.

v2: Use BITFIELD64_BIT() (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin 65d242ff5e intel/perf: update generated code to ralloc all data 
Previously counter descriptions as well register values were written
in global static variables. This isn't really thread safe so instead
ralloc all the data back under the gen_perf_config object.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin a683e7f3dc intel/perf: store the appropriate OA formats in queries 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin 8b8eaa84a3 intel/perf: make pipeline statistic query loading optional 
On Vulkan most of those are already covered by standard queries so
add the ability to skip them.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin cc13bfbd05 intel/genxml: add PIPE_CONTROL command cache invalidate bit 
This new bit invalidates the cache/prefetch of commands in the command
streamer. This will be useful for self modifying batches.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin 34a0ce58c7 anv: add a new execution mode for secondary command buffers 
This change adds a call/return execution mode for secondary command
buffer rather than the existing copy into the primary batch mode.

v2: Rework convention to avoid burning an ALU register (Jason)

v3: Use anv_address_add() (Jason)

v4: Move command emissions to anv_batch_chain.c (Jason)

v5: Also move last MI_BBS emission in secondary command buffer to
    anv_batch_chain.c (Jason)

v6: Fix end secondary command buffer end (Jason)

v7: Refactor anv_batch_address() to remove additional emit functions

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin a96d92a689 anv: don't reserve a particular register for draw count 
By using the same mi_builder throughout the draw call, we can just
allocate a register from the mi_builder and unref it when we're done.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin 796fccce63 intel/mi-builder: add framework for self modifying batches 
v2: Use Jason's idea to store addresses to modify

v3: Add ALU flushes (Jason)

v4: Remove ALU flush from gen_mi_self_mod_barrier() (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v2)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:27 +03:00
Lionel Landwerlin 570bd760d3 intel/genxml: fix bits generation for MI_LOAD_REGISTER_IMM 
This instruction has a group with the same name than another field above :

  <field name="Data DWord" start="64" end="95" type="uint"/>
  <group count="0" start="96" size="64">
    <field name="Register Offset" start="2" end="22" type="offset"/>
    <field name="Data DWord" start="32" end="63" type="uint"/>
  </group>

The script was replacing the offset of the field first with the second
one in the group.

This change ignore anything a group within an instruction.

v2: Drop unused variable (Rafael)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
 2020-05-20 14:02:26 +03:00
Denys ee9b17fc26 gitlab: Ask about reproduction rate in the issue template 
Reviewed-by: <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5055>
 2020-05-20 10:20:00 +00:00
Jason Ekstrand 989619c05b nir: Add const to nir_intrinsic_src_components 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5108>
 2020-05-19 20:45:55 +00:00
Alyssa Rosenzweig 29afa88941 pan/mdg: Apply outmods 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
 2020-05-19 20:21:28 +00:00
Alyssa Rosenzweig db7b0eb911 pan/mdg: Use helpers for branch/discard inversion 
Doesn't come up on glmark but would covered by the old passes.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
 2020-05-19 20:21:28 +00:00
Alyssa Rosenzweig 5500b1f280 pan/mdg: Remove invert optimizations 
Unused since last commit.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
 2020-05-19 20:21:28 +00:00
Alyssa Rosenzweig 449e5ded93 pan/mdg: Treat inot as a modifier 
With this, we may remove all invert passes and simply look at the src
modifier on NIR->MIR and fixup at pack time. No shader-db changes.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
 2020-05-19 20:21:28 +00:00
Alyssa Rosenzweig b124f5315c pan/mdg: Apply abs/neg modifiers 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
 2020-05-19 20:21:27 +00:00
Alyssa Rosenzweig 24e2e24dc0 pan/mdg: Ingest fsat_signed/fclamp_pos 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
 2020-05-19 20:21:27 +00:00
Alyssa Rosenzweig 22bb5a9acb pan/mdg: Prepare for modifier helpers 
We have to restructure to ensure NIR->MIR does not mutate the NIR and to
allow passing around dest/outmods for the new helpers. If NIR->MIR were
better designed this would be easier. Sigh.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
 2020-05-19 20:21:27 +00:00
Alyssa Rosenzweig f0455de6fc pan/mdg: Drop nir_lower_to_source_mods 
shader-db regressions fixed shortly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
 2020-05-19 20:21:27 +00:00
Alyssa Rosenzweig acc5afb0af pan/mdg: Remove .pos propagation pass 
Will be replaced later in the series. shader-db regressions but those
fixed momentarily.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
 2020-05-19 20:21:27 +00:00
Alyssa Rosenzweig aeb55180ff panfrost: Add modifier detection helpers 
With the goal of removing modifiers from NIR, these helpers let us
detect modifier patterns without mutating the underlying NIR. These were
intended for upstream, but due to various issues are being (temporarily)
vendored.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
 2020-05-19 20:21:27 +00:00
Alyssa Rosenzweig c2b0f3c17d nir: Add fclamp_pos opcode 
Corresponds to the .pos modifier on all Mali GPUs (lima and panfrost).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
 2020-05-19 20:21:27 +00:00
Alyssa Rosenzweig 0aedce417a nir: Add fsat_signed opcode 
Exists on later Mali. Equivalent to clamp(x, -1.0, 1.0)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5102>
 2020-05-19 20:21:27 +00:00
Connor Abbott 518909290b tu: Support VK_FORMAT_FEATURE_BLIT_SRC_BIT for texture-only formats 
It turns out this is required for compressed formats, and we might as
well enable it for the one other texture-only format too.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5098>
 2020-05-19 19:55:11 +00:00
Connor Abbott 74f1c304e8 tu: Fix buffer compressed pitch calculation with unaligned sizes 
We can just set the extent and not bufferRowLength/bufferImageHeight,
and the extent may not be a multiple of the block size if it covers the
entire image. In this case we have to first divide to get the
width/height in terms of blocks, and then multiply by the block size to
get the buffer's pitch and layer size. Multiplying and dividing instead
won't get the correct result when the extent covers the entire image and
isn't a multiple of the block size. This also makes the code easier to
follow because we don't calculate a pitch in non-sensical units (bytes
times the block width) as an intermediate step.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5098>
 2020-05-19 19:55:11 +00:00
Connor Abbott da68c72715 tu: Fall back to 3d blit path for BC1_RGB_* formats 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5098>
 2020-05-19 19:55:11 +00:00
Connor Abbott 3d5cc5ff22 tu: Always initialize image_view fields for blit sources 
Previously we only supported BLIT_SRC_BIT and BLIT_DEST_BIT together, so
we didn't have to worry about initializing blit-related fields for
texture-only formats, but it turns out that 2d blits work out just fine
with these formats and we'll need to enable BLIT_SRC_BIT for
texture-only formats due to a Vulkan requirement on compressed formats.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5098>
 2020-05-19 19:55:11 +00:00
Jason Ekstrand cc4a02d0ed nir: Add a store_reg helper and use the builder in phis_to_regs 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5094>
 2020-05-19 19:31:26 +00:00
Jason Ekstrand 3fdbeb70e1 nir: Add a new helper for iterating phi sources leaving a block 
This takes the same callback as nir_foreach_src except it walks all phi
sources which leave a given block.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5094>
 2020-05-19 19:31:26 +00:00
Jason Ekstrand 2c8c5cc87d nir/clone: Re-use clone_alu for nir_alu_instr_clone 
All it takes are a couple small tweaks to the clone infrastructure to
allow us to use it without any remap table at all.  This reduces code
duplication and the chances for bugs that come with it.  In particular,
the hand-rolled nir_alu_instr_clone didn't preserve no_[un]signed_wrap,
or source/destination modifiers.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5094>
 2020-05-19 19:31:26 +00:00
Bas Nieuwenhuizen 4c62dbb145 radv/winsys: Finish mapping for sparse residency. 
This adds the part that disables pagefaults when unbacked sparse
textures get accessed.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5079>
 2020-05-19 19:17:35 +00:00
Ian Romanick fec36c0668 intel/drm-shim: Return correct values for I915_PARAM_HAS_ALIASING_PPGTT 
It sure looks like it should be a Boolean value, but it's not.  The
values that we really want for later platforms are either 2 or 3.  The
old intel_stub.c in shader-db just always returns 3
(I915_GEM_PPGTT_FULL).  This returns the same set of values per platform
that kernel 5.6.13 would.

When using the shim for ICL with i965 driver, this fixes:

    i965 requires softpin (Kernel 4.5) on Gen10+.

Fixes: 0f4f1d70bf ("intel: add stub_gpu tool")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5061>
 2020-05-19 18:55:29 +00:00
Ian Romanick c8635b6fd3 intel/drm-shim: Add noop ioctl handler for set_tiling 
When using the shim for HSW and earlier, this fixes:

    DRM_SHIM: unhandled driver DRM ioctl 33 (0xc0106461)

Fixes: 0f4f1d70bf ("intel: add stub_gpu tool")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5061>
 2020-05-19 18:55:29 +00:00
Bas Nieuwenhuizen f8314291b3 radv: Expose VK_EXT_pipeline_creation_cache_control. 
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2972
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5072>
 2020-05-19 18:40:04 +00:00
Bas Nieuwenhuizen 32e9283145 radv: Support VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT_EXT. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5072>
 2020-05-19 18:40:04 +00:00
Bas Nieuwenhuizen e11f077bb2 radv: Support VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5072>
 2020-05-19 18:40:04 +00:00
Bas Nieuwenhuizen dde998685e radv: Support VK_PIPELINE_COMPILE_REQUIRED_EXT. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5072>
 2020-05-19 18:40:04 +00:00
Alyssa Rosenzweig 46624f277e panfrost: Enable AFBC for Z24X8 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5069>
 2020-05-19 18:09:26 +00:00
Alyssa Rosenzweig 82792ef19f panfrost: Fix Z24 vs Z32 mixup 
We don't actually support Z32_UNORM; the format we've been using as such
is in fact Z24X8 / Z24S8. Fix that and drop Z32_UNORM.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5069>
 2020-05-19 18:09:26 +00:00
Alyssa Rosenzweig 861e7dcae6 panfrost: Switch formats to table 
Rather than heuristically guessing what PIPE formats correspond to what
in the hardware, hardcode a table. This is more verbose, but a lot more
obvious -- the previous format support code was a source of endless
silent bugs.

v2: Don't report RGB233 (icecream95). Allow RGB5 for texturing
(icecream95).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5069>
 2020-05-19 18:09:26 +00:00
Alyssa Rosenzweig 6be9e09473 pan/mfbd: Add format codes for PIPE_FORMAT_B5G5R5A1_UNORM 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5069>
 2020-05-19 18:09:26 +00:00
Rhys Perry aca15d5cba nir/opt_if: use nir_src_as_bool in opt_peel_loop_initial_if helper 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4757>
 2020-05-19 17:46:38 +00:00
Rhys Perry 50bead32b1 nir/opt_if: run opt_peel_loop_initial_if after all other optimizations 
Fixes dEQP-VK.graphicsfuzz.loops-ifs-continues-call with RADV.

opt_if_loop_terminator can cause this optimization or
opt_if_simplification to be run on the non-SSA code.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes: 52c8bc0130 ('nir: make opt_if_loop_terminator() less strict')
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2943
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4757>
 2020-05-19 17:46:38 +00:00
Jason Ekstrand d221f70299 nir: Add documentation for each jump instruction type 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5101>
 2020-05-19 17:21:23 +00:00
Jason Ekstrand d011fbde5c nir: Use a switch statement in nir_handle_add_jump 
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5101>
 2020-05-19 17:21:23 +00:00