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30028 Commits

Author SHA1 Message Date
Boris Brezillon 5d5f7552a5 panfrost: XML-ify the multi-target framebuffer descriptors 
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6797>
 2020-09-21 07:35:45 -04:00
Boris Brezillon efce73d99d panfrost: XML-ify the bifrost tiler descriptors 
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6797>
 2020-09-21 07:35:45 -04:00
Boris Brezillon 95eb7d9a34 panfrost: XML-ify the single target framebuffer descriptor 
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6797>
 2020-09-21 07:35:45 -04:00
Boris Brezillon e855698ddd panfrost: XML-ify the midgard tiler descriptor 
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6797>
 2020-09-21 07:35:45 -04:00
Boris Brezillon 76096c723a panfrost: Clarify what TILED mode is 
We have 2 tile modes: tiled linear and tiled U-interleaved. Let's rename
the existing value to clarify that.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6797>
 2020-09-21 07:35:45 -04:00
Boris Brezillon 3a06fc3d34 panfrost: XML-ify the local storage descriptor 
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6797>
 2020-09-21 07:35:45 -04:00
Icecream95 2aa5838730 Revert "panfrost: Drop implicit blend pooling" 
This reverts commit dc7fbe114b.

Fixes INSTR_INVALID_PC faults with the SuperTuxKart advanced rendering
pipeline, which occurred when blend shader BOs were allocated far apart.

Fixes: dc7fbe114b ("panfrost: Drop implicit blend pooling")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6785>
 2020-09-21 11:13:36 +00:00
Bas Nieuwenhuizen d78df70c2a radv,radeonsi: Disable compression on interop depth images 
If we want to use HTILE correctly we need to communicate extra stuff
like clear colors. (Unlike DCC there is no HTILE FCE)

CC: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6617>
 2020-09-20 23:51:58 +00:00
Icecream95 7acf364131 panfrost: Set modifier_constant to true for exported resources 
Not actually seen in the wild but could theoretically be a problem for
applications that explicitly import/export resources.

v2: Set it on exporting as well as importing (Daniel Stone)

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6717>
 2020-09-20 01:28:50 +00:00
Erico Nunes 95ee0ba41f lima: fix vertex shader uniform buffer size 
In some cases when switching shader programs, mesa does not switch the
currently set pipe_constant_buffer, which keeps pointing to the one
previously set.
If the two shader programs have a different number of uniforms, the size
of the constant buffer may be different and this needs to be considered
while generating the next draw command.
This patch fixes the uniform buffer creation in the lima vertex shader
command to avoid an out of bounds memcpy due to a previously set
pipe_constant_buffer.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6701>
 2020-09-19 11:53:28 +02:00
Erico Nunes 6a1926035b lima: allocate new bo for stream draw 
In stream draws, the resource bo might be in use in a previous draw.
Allocate a new one for the resource to avoid overwriting data in use.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6503>
 2020-09-19 09:41:33 +00:00
Bas Nieuwenhuizen 017ca86b22 radeonsi: Move display dcc dirty tracking to framebuffer emission. 
To improve performance.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6783>
 2020-09-19 03:15:28 -04:00
Bas Nieuwenhuizen c6c1fa9a26 radeonsi: Put retile map in separate buffers. 
The retile maps are a software mechanism and hence very suceptible
to change. As such I'd like to avoid making it part of the cross
driver ABI.

Ideally we'd just use the cached tile info + a shader to avoid these
buffers altogether.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6783>
 2020-09-19 03:15:25 -04:00
Christian Gmeiner 77af1ca690 etnaviv: add disk cache 
Adds a shader disk-cache for shader variants.  Note that builds with
`-Dshader-cache=false` have no-op stubs with `disk_cache_create()` that
returns NULL.

This shader disk-cache gets used when using NIR only. Helps to save
about 1-2 minutes for a deqp run on gc2000.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6669>
 2020-09-18 07:45:11 +00:00
Christian Gmeiner 6a0d7f6316 etnaviv: shuffle some variant fields 
Just to group together the parts that will get serialized when we have
shader disk-cache.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6669>
 2020-09-18 07:45:11 +00:00
Michel Zou 12b8ad8f21 swr: fix _BitScanForward64 on unix 
it must apply to 64 bits types, and use the ctzll intrinsic instead of ctz

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6705>
 2020-09-18 06:24:00 +00:00
Michel Zou 82c49a66c0 swr: missing _BitScanForward64 on 32 bits win 
the code does not compile on 32 bits systems
for mingw we can use gcc intrinsics like the unix side
for msvc a generic implementation is provided

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6705>
 2020-09-18 06:24:00 +00:00
Vinson Lee ffbdbd631a panfrost: Delete debug allocated syncobj. 
Fix defect reported by Coverity Scan.

Logically dead code (DEADCODE)
dead_error_line: Execution cannot reach this statement: drmSyncobjDestroy(dev->fd, ...

Fixes: 64d6f56ad2 ("panfrost: Allocate syncobjs in panfrost_flush")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6720>
 2020-09-17 23:12:14 +00:00
Vinson Lee fcc506e520 radesonsi: Remove unsigned comparison to zero. 
cbuf was changed to unsigned in commit 3fec2f67c3 ("radeonsi:
compact MRTs to save PS export memory space").

Fix defect reported by Coverity Scan.

Macro compares unsigned to 0 (NO_EFFECT)
unsigned_compare: This greater-than-or-equal-to-zero comparison of
an unsigned value is always true. cbuf >= 0U.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6739>
 2020-09-17 22:59:57 +00:00
Gert Wollny 18e9781714 r600/sfn: Use load_ubo_vec4 lowering pass 
This replaces the lowering pass to align UBO loads at 16 byte
boundaries.

v2: use nir functions to query constants in ubo_vec4 (Eric)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6743>
 2020-09-17 10:11:11 +00:00
Gert Wollny 98eb00face r600: enable lowering uniforms to UBO 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6743>
 2020-09-17 10:11:11 +00:00
Gert Wollny feb463da63 llvmpipe: set lower_uniform_to_ubo compiler flag 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6316>
 2020-09-16 10:07:42 +00:00
Gert Wollny b155b6869c radeonsi: set compiler flag lower_uniforms_to_ubo 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6316>
 2020-09-16 10:07:42 +00:00
Erik Faye-Lund 9ba2365c6f vc4: remove unused header 
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6651>
 2020-09-16 08:37:13 +00:00
Erik Faye-Lund 9992797e1b v3d: remove unused header 
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6651>
 2020-09-16 08:37:13 +00:00
Gert Wollny 39e7bc23dd r600/sfn: Fix comparison with different signedness 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6706>
 2020-09-16 08:30:41 +00:00
Gert Wollny 2d6316cca4 r600/sfn: more fixing of vec4 fetching 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6706>
 2020-09-16 08:30:41 +00:00
Gert Wollny f46e04a1c4 r600/sfn: Fix source swizzle for gradient queries 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6706>
 2020-09-16 08:30:41 +00:00
Gert Wollny 02581acd07 r600/sfn: Fix bitfield ops and 2x16 split_y 
Don't reuse the dest register to make instruction dependency tracking
easier.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6706>
 2020-09-16 08:30:41 +00:00
Gert Wollny dfa45e26e2 r600/sfn: Fix split_alu_modifiers 
Don't reuse the dest register so we can better track instruction
dependencies later.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6706>
 2020-09-16 08:30:41 +00:00
Gert Wollny e85c0bdda5 r600/sfn: Lower *sign opcodes in nir 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6706>
 2020-09-16 08:30:41 +00:00
Gert Wollny c22e0fb02d r600/sfn: avoid some copies 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6706>
 2020-09-16 08:30:41 +00:00
Gert Wollny f2280e03e2 r600/sfn: Fix ordering of tex param moves 
Both moves should happen in the same instuction group, otherwise the
lod/bias value will be overwritten by the shadow compare value.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6706>
 2020-09-16 08:30:41 +00:00
Gert Wollny daaa71924a r600/sfn: clone shader before lowering to registers and src/dest modifiers 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6706>
 2020-09-16 08:30:41 +00:00
Gert Wollny 09558ad84e r600/sfn: Fix loading vertex attributes 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6706>
 2020-09-16 08:30:41 +00:00
Gert Wollny e46b2ad127 r600/sfn: correct ring op patching 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6706>
 2020-09-16 08:30:41 +00:00
Gert Wollny 688680decc r600/nir: fetch sources and split uniforms before emittting alu instructions 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6706>
 2020-09-16 08:30:41 +00:00
Gert Wollny 85f39cab8b r600: revert disabling llvm draw 
Now that llvm supports NIR and lowers uniforms to UBO in draw
calls when this hasn't be done before this can be used again.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6706>
 2020-09-16 08:30:41 +00:00
Pierre-Eric Pelloux-Prayer f1730bed8f radeonsi: fix guardband handling for large values 
When minx = -32768 (ViewportBounds.Min) we'll hit the "left <= -1, ..."
assert because 'left' is computed as:

   (-65535 / 2 - translate_x) / (minx - translate_x)

This commit fixes the problem by using the full max_viewport_size => [-32768, 32767]
instead of [-32767, 32767] for SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3502
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6685>
 2020-09-16 09:54:11 +02:00
Pierre-Eric Pelloux-Prayer c493bb9a57 radeonsi: fix quant_mode selection for large negative values 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6685>
 2020-09-16 09:54:09 +02:00
Pierre-Eric Pelloux-Prayer 7d853966df radeon/vcn: set dec->bs_ptr = NULL on unmap 
To avoid using a dangling pointer.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/1308
Cc: mesa-stable
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6556>
 2020-09-16 08:45:00 +02:00
Pierre-Eric Pelloux-Prayer eb60849ea2 r600/uvd: set dec->bs_ptr = NULL on unmap 
To avoid using a dangling pointer.
See https://gitlab.freedesktop.org/mesa/mesa/-/issues/1308

Cc: mesa-stable
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6556>
 2020-09-16 08:44:24 +02:00
Marek Olšák 4790811d78 Revert "radeonsi: move L2_CACHE_CONTROL registers into si_emit_framebuffer_state" 
This reverts commit 7edf15ad47.

The register value is immutable now.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6722>
 2020-09-16 02:54:01 +00:00
Marek Olšák b23013db0a Revert "radeonsi: set BIG_PAGE fields on gfx10.3" 
This reverts commit 430d384c31.

BIT_PAGE can't be set for GTT and we don't know if a buffer has been
evicted to GTT.

Fixes: 430d384c31

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6722>
 2020-09-16 02:54:01 +00:00
Marek Olšák 758ab39d25 radeonsi: clean up ffma handling 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6596>
 2020-09-16 02:39:02 +00:00
Marek Olšák 57bf4c2028 nir,radeonsi: move ffma fusing to late optimizations for better codegen 
The freedreno trace changes were suggested by Rob Clark.

ALU performance is higher, because ffma is used more often, but so is
register usage, because trinary opcodes (such as ffma) usually need
at least 3 live registers.

54793 shaders in 33659 tests
Totals:
SGPRS: 2639746 -> 2642938 (0.12 %)
VGPRS: 1534120 -> 1536392 (0.15 %)
Spilled SGPRs: 3541 -> 3618 (2.17 %)
Spilled VGPRs: 33 -> 44 (33.33 %)
Scratch size: 292 -> 312 (6.85 %) dwords per thread
Code Size: 55639836 -> 55620116 (-0.04 %) bytes
Max Waves: 964785 -> 963977 (-0.08 %)

Totals from affected shaders:
SGPRS: 1105800 -> 1108992 (0.29 %)
VGPRS: 635292 -> 637564 (0.36 %)
Spilled SGPRs: 3193 -> 3270 (2.41 %)
Spilled VGPRs: 33 -> 44 (33.33 %)
Scratch size: 36 -> 56 (55.56 %) dwords per thread
Code Size: 31568708 -> 31548988 (-0.06 %) bytes
Max Waves: 319991 -> 319183 (-0.25 %)

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6596>
 2020-09-16 02:39:02 +00:00
Tapani Pälli 51a6261d38 iris: remove additional pipe control done before hiz for older gens 
The restriction found in removed comment is not found on new specs.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6593>
 2020-09-15 11:44:30 +03:00
Vinson Lee c7719b8cfc nv50/ir: Initialize Converter members. 
Fix defects reported by Coverity Scan.

Uninitialized pointer field (UNINIT_CTOR)
Non-static class member exit is not initialized in this
constructor nor in any functions that it calls
Non-static class member immInsertPos is not initialized in this
constructor nor in any functions that it calls.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6695>
 2020-09-14 22:44:39 +00:00
Christian Gmeiner f3150abe5e etnaviv: call nir_opt_shrink_vectors(..) in opt loop 
total instructions in shared programs: 105044 -> 103312 (-1.65%)
instructions in affected programs: 27328 -> 25596 (-6.34%)
helped: 55
HURT: 0
helped stats (abs) min: 4 max: 96 x̄: 31.49 x̃: 24
helped stats (rel) min: 1.18% max: 23.08% x̄: 8.26% x̃: 6.88%
95% mean confidence interval for instructions value: -37.81 -25.18
95% mean confidence interval for instructions %-change: -9.66% -6.85%
Instructions are helped.

total temps in shared programs: 2960 -> 2917 (-1.45%)
temps in affected programs: 425 -> 382 (-10.12%)
helped: 41
HURT: 6
helped stats (abs) min: 1 max: 3 x̄: 1.20 x̃: 1
helped stats (rel) min: 7.14% max: 25.00% x̄: 13.79% x̃: 12.50%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 12.50% max: 25.00% x̄: 17.52% x̃: 16.67%
95% mean confidence interval for temps value: -1.17 -0.66
95% mean confidence interval for temps %-change: -13.30% -6.29%
Temps are helped.

total immediates in shared programs: 16772 -> 16468 (-1.81%)
immediates in affected programs: 4304 -> 4000 (-7.06%)
helped: 59
HURT: 0
helped stats (abs) min: 4 max: 16 x̄: 5.15 x̃: 4
helped stats (rel) min: 2.22% max: 33.33% x̄: 9.31% x̃: 7.14%
95% mean confidence interval for immediates value: -5.88 -4.43
95% mean confidence interval for immediates %-change: -11.14% -7.49%
Immediates are helped.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6572>
 2020-09-14 18:49:26 +00:00
Erico Nunes 4868ce1451 lima: dont split vec3 unaligned load inputs 
It seems that the mali400 pp is unable to load vec3 unaligned varyings.
This can happen in the current state with mesa if a varying float is put
into the first component of a vec4 and a vec3 is packed right after it.
This would be fine as by default nir would create a vec4 load followed
by a mov with swizzle to realign the components into a vec3.
In lima_nir_split_load_input, this becomes a separate vec3 load
expecting the unaligned load.
Since this can't happen, skip the load input splitting for this special
case.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6507>
 2020-09-13 10:09:29 +00:00