Commit Graph

30028 Commits

Author SHA1 Message Date
Kenneth Graunke 39f06e2848 iris: Implement pipe->texture_subdata directly
Chris Wilson noted that u_default_texture_subdata's transfer path
sometimes results in wasteful double copies.  This patch is based
on an earlier path he wrote, but updated now that we have staging
blits for busy or compressed textures.

Consider the case of idle, non-CCS-compressed, tiled images:

The transfer-based CPU path has to return a "linear" mapping, so upon
map, it mallocs a temporary buffer.  u_default_texture_subdata then
copies the client memory to this malloc'd buffer, and transfer unmap
performs a tiled_memcpy to copy it back into the texture.  By writing
a direct texture_subdata() implementation, we're able to directly do
a tiled_memcpy from the client memory into the destination texture,
resulting in only one copy.

For linear buffers, there is no advantage to doing things directly, so
we simply fall back to u_default_texture_subdata()'s transfer path to
avoid replicating those cases.

We still may want to use GPU staging buffers for busy destinations
(to avoid stalls) or CCS-compressed images (to compress the data),
at which point we also fall back to the existing path.  We thought
to try and use a tiled temporary, but this didn't appear to help.

Improves performance in x11perf -shmput500 by 1.96x on my Icelake.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2500
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3818>
2020-06-26 21:20:41 +00:00
Rob Clark f97acb4bb4 freedreno/ir3: disk-cache support
Adds a shader disk-cache for ir3 shader variants.  Note that builds with
`-Dshader-cache=false` have no-op stubs with `disk_cache_create()` that
returns NULL.

Binning pass variants are serialized together with their draw-pass
counterparts, due to shared const-state.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
2020-06-26 08:55:19 -07:00
Rob Clark 6aadb00e60 freedreno/ir3: build binning variant at same time as draw variant
For shader-cache, we are going to want to serialize them together.
Which is awkward if the two related variants are not compiled together.

This also decouples allocation and compile, which will simplify adding
shader-cache (which still needs to allocate, but can skip compile).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
2020-06-26 08:53:02 -07:00
Rob Clark 83b97bf161 freedreno/a6xx+ir3: stop generating pointless binning shaders
Currently we always do sysmem if there is tess.  And for GS, the binning
pass VS ends up identical to the draw pass VS, so no point in compiling
it twice.  (For GS what we should do someday is generate a binning pass
GS, and possibly if we can do cross-stage linking opts, an optimized
binning pass VS, but the required outputs would somehow have to end up
in the shader variant key.)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
2020-06-26 08:53:00 -07:00
Rob Clark c0f22c3d94 freedreno/ir3: add ir3_compiler_destroy()
Use ir3_compiler_destroy() rather than open-coding ralloc_free().  This
will give us a place to add more compiler related cleanup code in the
following patches.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
2020-06-26 08:43:23 -07:00
Rob Clark f1ab57359c freedreno/ir3: move finalize_nir to pscreen hook
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
2020-06-26 08:43:22 -07:00
Rob Clark d3ae559378 freedreno/ir3: add ir3_finalize_nir()
The next step is to hook this into pscreen->finalize_nir() so it can
come before the state tracker's shader-caching.

Unfortunately we still need to do lower_io after mesa/st, so that is
split out into a post-finalize pass.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
2020-06-26 08:43:22 -07:00
Mike Blumenkrantz e35b8971a7 zink: use OpFUnordNotEqual for nir_op_fne
we want to detect NaNs here, and OpFUnordNotEqual is the variant which does this

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>
2020-06-26 14:07:35 +00:00
Mike Blumenkrantz 765de33d3c zink: set lower_mul_high and lower_rotate in ntv compiler options
we don't implement these

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>
2020-06-26 14:07:35 +00:00
Mike Blumenkrantz 49c13fccf7 zink: handle isign alu in ntv
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>
2020-06-26 14:07:35 +00:00
Mike Blumenkrantz 21fe5b0ffd zink: handle ixor in ntv
fixes spec@glsl-1.30@execution@built-in-functions@fs-op-assign-bitxor tests

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>
2020-06-26 14:07:35 +00:00
Mike Blumenkrantz 651d093298 zink: lower byte/word extract ops in nir
we don't implement these, and pre-optimizing them breaks things in ntv->vtn

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>
2020-06-26 14:07:35 +00:00
Mike Blumenkrantz 90d3455848 zink: add bitfield_reverse handling to ntv
fixes several piglit tests

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>
2020-06-26 14:07:35 +00:00
Mike Blumenkrantz 957d8e2658 zink: add ult handling for ntv
fixes shaders@glsl-vs-absolutedifference-uint piglit test

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>
2020-06-26 14:07:35 +00:00
Mike Blumenkrantz 2159aa0c49 zink: handle signed and unsigned min/max ops in ntv
fixes a number of piglit amd_shader_trinary_minmax tests

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>
2020-06-26 14:07:35 +00:00
Icecream95 6b886fbc0b panfrost: Add PAN_MESA_DEBUG=gl3 flag
This flag allows forcing GL 3.3 without having to use
MESA_GL_VERSION_OVERRIDE etc.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5584>
2020-06-26 10:30:03 +00:00
Connor Abbott 1288613f1c freedreno/a6xx: use firstIndex field
Analogous to the turnip change.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>
2020-06-26 10:05:24 +00:00
Connor Abbott a32fb2f9d0 freedreno: On a5xx+ INDX_SIZE is MAX_INDICES
This was already done correctly for the indirect variants, and turnip
was setting the correct value, but it seems freedreno missed the change
in the non-indirect variant. Also, fix a misspelling of "indices" and
add a type to INDX_SIZE.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>
2020-06-26 10:05:24 +00:00
Connor Abbott 1dd24bf27b freedreno: Share constlen between different stages properly
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
2020-06-26 09:34:33 +00:00
Connor Abbott d9dd989d2a freedreno: Refactor ir3_cache shader compilation
Use an array, which makes it more like turnip and makes implementing the
const limits easier.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
2020-06-26 09:34:33 +00:00
Connor Abbott 2841bb1fac ir3, freedreno: Round up constlen earlier
Prevents problems when calculating whether we overflow the shared limit.
Note that on a6xx, the macros handle the assert for us.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
2020-06-26 09:34:33 +00:00
Marek Olšák 71794567f9 radeonsi: remove tabs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
2020-06-26 07:02:57 +00:00
Marek Olšák 0cdec11d95 radeonsi: clear per-context buffers at the end of si_create_context
We don't want any packets before CONTEXT_CONTROL.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
2020-06-26 07:02:57 +00:00
Marek Olšák da78d50bc8 radeonsi: make si_pm4_cmd_begin/end static and simplify all usages
There is no longer the confusing trailing si_pm4_cmd_end call.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
2020-06-26 07:02:57 +00:00
Marek Olšák 7b2a0f880b radeonsi: disallow adding BOs into si_pm4_state except 1 shader BO per state
The si_shader pointer is already there, so use it and remove the array
of BOs.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
2020-06-26 07:02:57 +00:00
Marek Olšák 3b1e42d2c2 radeonsi: make wait_mem_scratch unmappable
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
2020-06-26 07:02:57 +00:00
Marek Olšák 428360662f radeonsi: don't add the tess ring buffers into the cs_preamble state
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
2020-06-26 07:02:57 +00:00
Marek Olšák 1c1d34a67a radeonsi: rename init_config states to cs_preamble states
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
2020-06-26 07:02:57 +00:00
Marek Olšák bbc0a2d51d radeonsi: don't add the border color buffer into the init_config state
We might have to replace init_config for preemption.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
2020-06-26 07:02:57 +00:00
Icecream95 be5d06106f panfrost: Only copy resources when they are in a pending batch
Fixes a performance regression in alacritty, and rendering is still
fine in GLQuake ports.

Fixes: 361fb38662 ("panfrost: Copy resources when mapping to avoid waiting for readers")
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5642>
2020-06-26 06:32:34 +00:00
Rafael Antognolli 293221ddda iris: Align last_seqnos to 64 bits.
last_seqnos is used in atomic operations. Specially on 32 bit platorms,
it tends to be slower if it's not aligned to 64 bits (see
cdc331c6f9). This fixes a small regression
on Bioshock.

Fixes: aba3aed96e ("iris: fix export of GEM handles")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5637>
2020-06-25 22:11:08 -07:00
Eric Anholt 50e20cb036 freedreno/a6xx: Add support for polygon fill mode (as long as front==back).
Unlike a4xx, we don't seem to have separate back vs front fields any more.
Still, this improves desktop GL conformance (and one of the traces in
traces-db).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5650>
2020-06-25 13:46:30 -07:00
Eric Anholt daee177ca0 freedreno/a6xx: Define the register fields for polygon fill mode.
Produced by comparing the traces of:
dEQP-VK.rasterization.culling.front_triangles
dEQP-VK.rasterization.culling.front_triangles_point
dEQP-VK.rasterization.culling.front_triangles_line

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5650>
2020-06-25 13:46:28 -07:00
Mike Blumenkrantz 37e7a5e746 zink: unify code for setting resource barriers
no functional changes, this code was just duplicated

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5615>
2020-06-25 12:50:21 +00:00
Danylo Piliaiev 82b4666783 iris: Honor scanout requirement from DRI
Translate PIPE_BIND_SCANOUT as ISL_SURF_USAGE_DISPLAY_BIT,
instead of PIPE_BIND_DISPLAY_TARGET.

PIPE_BIND_DISPLAY_TARGET isn't used for dri images and seem to
be set only for fake winsys buffers (which aren't displayed).
The trouble is that a fake buffer could be multisampled and we
cannot have multisampled surface with display bit.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2313
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4784>
2020-06-25 11:50:10 +00:00
Rob Clark 7c008c293d freedreno: handle batch flush in resource tracking
In rare cases, we can get into situations where the tracking of read/
written resources triggers a flush of the current batch.

To handle that, (1) take a reference to the current batch, so it doesn't
disappear under us, and (2) check after resource tracking whether the
current batch was flushed.  If it is, we have to re-do the resource
tracking, but since we have a fresh batch, it should not get flushed the
second time around.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3160
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5634>
2020-06-25 00:55:24 +00:00
Rob Clark 16b4da3ba3 freedreno: split out batch clear tracking helper
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5634>
2020-06-25 00:55:24 +00:00
Rob Clark ad136945e6 freedreno: split out batch draw tracking helper
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5634>
2020-06-25 00:55:24 +00:00
Rob Clark d74554b167 freedreno: make foreach_bit() declare it's cursor
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5634>
2020-06-25 00:55:24 +00:00
Rob Clark 3065c4bf92 freedreno/ir3: switch PIPE_CAP_TGSI_TEXCOORD
We don't really need the varying remapping, and it seems to somehow
happen twice when shader-cache comes into the picture.  But we can
just choose not to have this problem.

Now that everything is using the ir3_point_sprite() helper, we can
flip this pipe cap without it being a massive flag-day.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
2020-06-24 22:29:28 +00:00
Rob Clark e6d650353a freedreno: convert builtin blit VS prog to ureg builder
The correct varying semantic to use depends on PIPE_CAP_TGSI_TEXCOORD.
To handle this transition switch it over to ureg builder, and query the
pipe-cap to choose the appropriate semantic.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
2020-06-24 22:29:28 +00:00
Rob Clark b5574c5165 freedreno/a3xx: use point-coord helper
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
2020-06-24 22:29:28 +00:00
Rob Clark ba6e1514f5 freedreno/a4xx: use point-coord helper
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
2020-06-24 22:29:28 +00:00
Rob Clark 3e8c6312c7 freedreno/a5xx: use point-coord helper
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
2020-06-24 22:29:28 +00:00
Rob Clark a474d48e17 freedreno/a6xx: use point-coord helper
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
2020-06-24 22:29:28 +00:00
Rob Clark 68d6aa3dd0 freedreno/a6xx: de-duplicate vinterp/vpsrepl state building
When we flip the texcoord patch, we'll setup PNTC input slot in the
pre-built interp stateobj, rather than this being a draw-time (slow-
path) built stateobj.  But rather than duplicate more of the slow-
path logic, refactor it out into a helper that is reused in both
cases.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
2020-06-24 22:29:28 +00:00
Rob Clark 022c363cfb freedreno/ir3: add helper to determine point-coord inputs
This will simplify a bit the logic for setting up vinterp/vprepl in the
driver backend, and also avoid it being a flag-day when we switch the
texcoord pipe cap.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
2020-06-24 22:29:28 +00:00
Jonathan Marek a9d866910c freedreno/registers: a6xx depth bounds test registers
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5628>
2020-06-24 20:55:15 +00:00
Mauro Rossi 1be67d610f android: freedreno/ir3: simplify generated sources rules
Simplification and alignment with meson's sources generation rules

Changelog:
- move rules from src/gallium/drivers/freedreno/Android.gen.mk to Android.ir3.mk
- simplify LOCAL_GENERATED_SOURCES based on $(ir3_GENERATED_FILES)
- remove includes of src/gallium/drivers/freedreno/Android.gen.mk
- remove src/gallium/drivers/freedreno/Android.gen.mk

Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Rob Clark <robdclark@gmail.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5580>
2020-06-24 10:00:14 +00:00
Mauro Rossi 41683157e7 android: freedreno/ir3: add missing generated sources and rules
Changelog:
- Makefile.sources: add ir3_lexer.c and ir3_parser.{c,h} generated sources
- Android.ir3.mk: add the necessary generated sources rules
- Android.ir3.mk: add the necessary include paths
- src/gallium/drivers/freedreno/Android.gen.mk: generate only ir3_nir_{imul,trig}.c for the moment

Fixes the following building error:

target  C: libfreedreno_ir3 <= external/mesa/src/freedreno/ir3/ir3_assembler.c
FAILED: out/target/product/x86_64/obj/STATIC_LIBRARIES/libfreedreno_ir3_intermediates/ir3/ir3_assembler.o
...
external/mesa/src/freedreno/ir3/ir3_assembler.c:28:10: fatal error: 'ir3_parser.h' file not found
         ^~~~~~~~~~~~~~
1 error generated.

Fixes: 1e8808a4a0 ("freedreno/ir3: refactor out helper to compile shader from asm")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Rob Clark <robdclark@gmail.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5580>
2020-06-24 10:00:14 +00:00