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196309 Commits

Author SHA1 Message Date
Sil Vilerino 4b203d361e mediafoundation: Implement d3d12_context_queue_priority_manager and related ICodecAPI 
Reviewed-by: Pohsiang (John) Hsu <pohhsu@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37376>
 2025-09-15 20:41:12 +00:00
Sil Vilerino 11db73820f d3d12: Implement d3d12_context_queue_priority_manager 
Reviewed-by: Pohsiang (John) Hsu <pohhsu@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37376>
 2025-09-15 20:41:12 +00:00
Sil Vilerino 304e3ab552 d3d12: Fix double video encode resource barrier for DPB/recon pic resources 
Reviewed-by: Pohsiang (John) Hsu <pohhsu@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37376>
 2025-09-15 20:41:12 +00:00
Rohit Athavale 4ea424cc4f d3d12: Make delta QP min and max to be bit-depth dependent for HEVC 
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37376>
 2025-09-15 20:41:11 +00:00
Danylo Piliaiev 1c57f88908 tu: Reset BIN_FOVEAT regs for tiling with and without HW binning 
We didn't reset the regs when HW binning was disabled.

Fixes: b34b089ca1 ("tu: Use GRAS bin offset registers")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37373>
 2025-09-15 20:11:21 +00:00
Samuel Pitoiset 0bc0ead674 radv: set DRLR mapping info from inheritance info when present 
These two structs are allowed to be in pNext and they should match
the primary command buffer info.

Found while implementing a new extension.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37278>
 2025-09-15 19:29:34 +00:00
Samuel Pitoiset 5907dbfc09 radv: remove redundant RADV_DYNAMIC_RASTERIZATION_SAMPLES 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36988>
 2025-09-15 19:10:42 +00:00
Samuel Pitoiset 2084cb59f2 radv: remove redundant RADV_DYNAMIC_POLYGON_MODE 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36988>
 2025-09-15 19:10:42 +00:00
Samuel Pitoiset c1a1aed665 radv: remove redundant RADV_DYNAMIC_LINE_RASTERIZATION_MODE 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36988>
 2025-09-15 19:10:41 +00:00
Samuel Pitoiset d8bc573ee9 radv: remove redundant RADV_DYNAMIC_PRIMITIVE_TOPOLOGY 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36988>
 2025-09-15 19:10:40 +00:00
Samuel Pitoiset 43d7795274 radv: pre-compute vgt_outprim_type 
This will allow us to optimize the number of states to emit.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36988>
 2025-09-15 19:10:39 +00:00
Samuel Pitoiset c8245173a0 radv: pre-compute the line rasterization mode 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36988>
 2025-09-15 19:10:39 +00:00
Samuel Pitoiset 469350328c radv: pre-compute the number of rasterization samples 
The number of rasterization samples depend on many various states.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36988>
 2025-09-15 19:10:38 +00:00
Samuel Pitoiset 8d991c2572 radv/meta: remove useless assertion when choosing resolve method 
The destination image layout is used for depth/stencil resolves and
asserting isn't very useful.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37300>
 2025-09-15 18:52:55 +00:00
Samuel Pitoiset c8f6b27964 radv/meta: simplify calling depth/stencil resolve helpers 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37300>
 2025-09-15 18:52:55 +00:00
Samuel Pitoiset 39725fc935 radv/meta: simplify barriers for resolves 
This is equivalent.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37300>
 2025-09-15 18:52:54 +00:00
Samuel Pitoiset e673ccfcb5 radv/meta: remove useless VK_ACCESS_2_SHADER_WRITE_BIT for subpass resolves 
This doesn't do anything.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37300>
 2025-09-15 18:52:54 +00:00
Samuel Pitoiset 704fbbb108 radv/meta: rework depth/stencil resolves using graphics 
This adds a new helper that doesn't depend on the rendering info.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37300>
 2025-09-15 18:52:53 +00:00
Samuel Pitoiset 141beaee4e radv/meta: rework depth/stencil resolves using compute 
This adds a new helper that doesn't depend on the rendering info.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37300>
 2025-09-15 18:52:53 +00:00
Samuel Pitoiset 2207d1e732 radv/meta: fix saving push constants for depth/stensil resolves on compute 
Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37300>
 2025-09-15 18:52:52 +00:00
Mike Blumenkrantz 818826fcf1 zink: imagelessFramebuffer is no longer required/used 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37338>
 2025-09-15 18:06:32 +00:00
Nanley Chery 7c8e38ac67 anv: Rework locking for sparse binding with TR-TT 
When sparse binding functions submit batches, they may modify the
exec_obj_index field of anv_bo structs. This field is used to ensure a
unique list of buffers is sent to the kernel (i915). Add a lock in these
functions to prevent multiple threads from modifying this field during
the batch submission process. To avoid creating a deadlock, also rework
the locking done in anv_queue_submit().

When playing the Monster Hunter Wilds Benchmark on a mesa build which
enables slab allocation of batch buffers (6f7a32ec92), this avoids a
sporadic assert failure:

nsterHunterWilds.exe:
   ../../src/intel/vulkan/i915/anv_batch_chain.c:489:
      setup_execbuf_for_cmd_buffers:
         Assertion `execbuf->bos[idx] == first_batch_bo_real' failed.

This issue was seemingly first introduced in 04bfe828db
("anv/sparse: allow sparse resouces to use TR-TT as its backend")

Backport-to: 25.2
Ref: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12582
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37307>
 2025-09-15 17:45:15 +00:00
Nanley Chery 27167fdcb5 anv,hasvk: Take trace submission ID out of lock 
The Vulkan spec requires that access to the queue parameter be
externally synchronized for vkQueueSubmit(). So, each submit call to a
specific queue will have a unique ID.

Backport-to: 25.2
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37307>
 2025-09-15 17:45:15 +00:00
Natalie Vock e3460f15fa aco/opt: Work around GCC compiler issue 
No functional change. Random code churn that, apparently, makes a
GCC miscompile disappear.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34531>
 2025-09-15 17:16:21 +00:00
Natalie Vock a06f38e5ae aco/vn: Don't combine expressions across calls 
This increases live state across calls, which in turn increases spilling
and makes for slower shaders overall.

On top of RT function calls:
Totals from 7 (0.01% of 81072) affected shaders:

Instrs: 8980 -> 8955 (-0.28%); split: -0.88%, +0.60%
CodeSize: 51976 -> 51684 (-0.56%); split: -1.02%, +0.46%
SpillSGPRs: 248 -> 244 (-1.61%); split: -3.63%, +2.02%
SpillVGPRs: 367 -> 365 (-0.54%); split: -1.09%, +0.54%
Scratch: 32768 -> 31744 (-3.12%)
Latency: 135669 -> 128720 (-5.12%); split: -5.13%, +0.01%
InvThroughput: 35301 -> 34783 (-1.47%); split: -1.51%, +0.05%
VClause: 241 -> 242 (+0.41%)
SClause: 117 -> 120 (+2.56%)
Copies: 1311 -> 1338 (+2.06%); split: -0.69%, +2.75%
PreSGPRs: 899 -> 895 (-0.44%); split: -1.56%, +1.11%
PreVGPRs: 1103 -> 1099 (-0.36%)
VALU: 6143 -> 6098 (-0.73%); split: -1.22%, +0.49%
SALU: 913 -> 933 (+2.19%); split: -0.11%, +2.30%
VMEM: 989 -> 967 (-2.22%)
SMEM: 201 -> 214 (+6.47%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34531>
 2025-09-15 17:16:21 +00:00
Natalie Vock 575d3adbf5 aco/validate: Validate call instructions 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34531>
 2025-09-15 17:16:21 +00:00
Natalie Vock 28dc185966 aco/sched: Handle calls 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34531>
 2025-09-15 17:16:20 +00:00
Natalie Vock 2be37a91fa aco/live_var_analysis: Handle calls 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34531>
 2025-09-15 17:16:20 +00:00
Natalie Vock 9c8a17e172 aco/lower_to_hw_instr: Lower calls 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34531>
 2025-09-15 17:16:20 +00:00
Natalie Vock 3667a7b687 aco: Add call info 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34531>
 2025-09-15 17:16:20 +00:00
Natalie Vock af812862b7 aco: Add call-related program/block properties 
Indicates various properties about calls: Whether a program is an
indirect callee, whether a program or block contains function calls, and
whether registers used by a caller need to be preserved.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34531>
 2025-09-15 17:16:20 +00:00
Natalie Vock 917a98b722 aco: Add ABI and Pseudo CALL format 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34531>
 2025-09-15 17:16:20 +00:00
Natalie Vock e850650f92 aco: Add function call attributes 
ACO needs RADV to set certain attributes on NIR functions to help with
compilation of function calls.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34531>
 2025-09-15 17:16:20 +00:00
Natalie Vock d18b438832 aco: Add RegisterDemand::operator!= 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34531>
 2025-09-15 17:16:20 +00:00
Karol Herbst cbc838b7d1 rusticl: reference resource in sampler and image view wrappers 
Since b3133e250e ("gallium: add pipe_context::resource_release to
eliminate buffer refcounting") we need to take a reference for every bound
buffer object.

As we create image views on buffers, and kinda take partly reference
already just do it properly for now so we don't end up with
use-after-frees in drivers.

Fixes: dee9600a ("zink: eliminate buffer refcounting to improve performance")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37350>
 2025-09-15 16:56:22 +00:00
Job Noorman 563b0b347a ir3: don't create merge sets for subreg moves 
There are multiple places where RA assumes merge sets are either
all-full or all-half registers. Creating merge sets for subreg moves
mixes full and half registers which may lead to RA failures.

Fix this by not creating merge sets for subreg moves anymore. Instead,
we manually try to allocate  a subreg move's src for its dst when
selecting a register during RA, similar to how ALU/SFU instructions try
to reuse their srcs.

Totals:
Instrs: 363174291 -> 363175216 (+0.00%); split: -0.00%, +0.00%
CodeSize: 922975364 -> 922977230 (+0.00%); split: -0.00%, +0.00%
NOPs: 47652421 -> 47652444 (+0.00%); split: -0.00%, +0.00%
MOVs: 15652959 -> 15653065 (+0.00%); split: -0.00%, +0.00%
COVs: 4097203 -> 4097052 (-0.00%); split: -0.01%, +0.00%
(ss): 7806025 -> 7806183 (+0.00%); split: -0.00%, +0.00%
(sy): 3981862 -> 3981855 (-0.00%); split: -0.00%, +0.00%
(ss)-stall: 26612057 -> 26612789 (+0.00%); split: -0.00%, +0.00%
(sy)-stall: 111568786 -> 111568721 (-0.00%); split: -0.00%, +0.00%
STPs: 345796 -> 345792 (-0.00%)
LDPs: 191118 -> 191111 (-0.00%)
Preamble Instrs: 160491915 -> 160492355 (+0.00%); split: -0.00%, +0.00%
Last helper: 116587870 -> 116588273 (+0.00%); split: -0.00%, +0.00%
Cat0: 53288367 -> 53288384 (+0.00%); split: -0.00%, +0.00%
Cat1: 20954383 -> 20954336 (-0.00%); split: -0.00%, +0.00%
Cat2: 155294307 -> 155295252 (+0.00%); split: -0.00%, +0.00%
Cat6: 4623070 -> 4623059 (-0.00%)
Cat7: 9302363 -> 9302384 (+0.00%); split: -0.00%, +0.00%

Totals from 979 (0.07% of 1352016) affected shaders:
Instrs: 1324850 -> 1325775 (+0.07%); split: -0.07%, +0.14%
CodeSize: 2596114 -> 2597980 (+0.07%); split: -0.04%, +0.11%
NOPs: 330197 -> 330220 (+0.01%); split: -0.23%, +0.24%
MOVs: 62592 -> 62698 (+0.17%); split: -0.35%, +0.52%
COVs: 49011 -> 48860 (-0.31%); split: -0.62%, +0.31%
(ss): 35671 -> 35829 (+0.44%); split: -0.28%, +0.73%
(sy): 18936 -> 18929 (-0.04%); split: -0.13%, +0.09%
(ss)-stall: 157929 -> 158661 (+0.46%); split: -0.36%, +0.82%
(sy)-stall: 543371 -> 543306 (-0.01%); split: -0.20%, +0.19%
STPs: 2741 -> 2737 (-0.15%)
LDPs: 3022 -> 3015 (-0.23%)
Preamble Instrs: 322588 -> 323028 (+0.14%); split: -0.01%, +0.14%
Last helper: 298996 -> 299399 (+0.13%); split: -0.05%, +0.19%
Cat0: 361575 -> 361592 (+0.00%); split: -0.21%, +0.22%
Cat1: 111733 -> 111686 (-0.04%); split: -0.45%, +0.41%
Cat2: 487366 -> 488311 (+0.19%); split: -0.04%, +0.23%
Cat6: 21239 -> 21228 (-0.05%)
Cat7: 37170 -> 37191 (+0.06%); split: -0.06%, +0.12%

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: c757b22c5f ("ir3: add subreg move optimization")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37368>
 2025-09-15 15:07:47 +00:00
Julian Orth efc2bb64ce kms-swrast: export dmabufs with DRM_RDWR 
This is required for the dmabufs to be usable with llvmpipe.

Fixes #13609

Signed-off-by: Julian Orth <ju.orth@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37088>
 2025-09-15 14:50:00 +00:00
Mike Blumenkrantz dfcdae378a zink: don't use screen ralloc context for screen::pipeline_libs 
set_rehash will realloc this memory, which triggers a UAF on screen destroy

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37370>
 2025-09-15 14:29:38 +00:00
Mike Blumenkrantz f7480771c6 zink: stop unsetting zink_gfx_pipeline::modules on shader unbind 
this conflicts with the optimal_key

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37370>
 2025-09-15 14:29:38 +00:00
David Rosca e1ea3f8bbf radv/video: Always use OBU_FRAME in AV1 encode 
Saves couple bytes per frame.

Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37176>
 2025-09-15 14:12:17 +00:00
Patrick Lerda 06da0e7310 r600: fix emit_ssbo_atomic_op when ssbo_image_offset is non-zero 
The value read was incorrect.

This change was tested on palm, barts and cayman, it fixes all the variants
of the advanced-sso-simple test:
khr-gl4[56]/es_31_compatibility/shader_image_load_store/advanced-sso-simple: fail pass
khr-gles31/core/shader_image_load_store/advanced-sso-simple: fail pass

Cc: mesa-stable
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37225>
 2025-09-15 13:57:34 +00:00
Erik Faye-Lund 1a9dc3de1f panfrost: add per-gpu GLES2 extension lists 
This allows us to avoid accidental feature regressions, by verifying
that the reality matches the expectations in CI.

This is inspired by a similar change in r300.

Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37363>
 2025-09-15 12:56:15 +00:00
Quentin Schulz e1765a2914 nvk: remove unused relative_dir variable 
In commit f35172b6a4 ("meson: make CL args common"), the
fmacro-prefix-map using relative_dir variable was moved from child
meson.build files to the main meson.build file. However, the
relative_dir variable assignment from src/nouveau/vulkan/meson.build
wasn't removed, while src/asahi/libagx's and src/panfrost/libpan's were.
This seems to be an oversight, so let's remove this seemingly now unused
relative_dir meson variable from nvk's meson.build.

This also allows us to remove the use of discouraged global_build_root()
[1] and global_source_root()[2].

[1] https://mesonbuild.com/Reference-manual_builtin_meson.html#mesonglobal_build_root
[2] https://mesonbuild.com/Reference-manual_builtin_meson.html#mesonglobal_source_root

Fixes: f35172b6a4 ("meson: make CL args common")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36927>
 2025-09-15 12:18:37 +00:00
Sergi Blanch Torne b886ca33b8 ci: fix gc2000 fails duplication 
From !37273 in commit db3501ec4f, the transition Fail to Crash on two tests
produced a duplication in the fails file. The pre-merge didn't catch it, but
in the nightlies and in the ci-uprev attempts to uprev Piglit the jobs report
the duplication error.

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37364>
 2025-09-15 11:25:55 +00:00
Boris Brezillon a620f33b7c panvk: Add planar Z24S8 support 
It allows us to use AFBC even if separateDepthStencilLayouts=true.
Unfortunately, AFBC(S8) is only supported on v9+, so we keep using
interleaved Z24S8 on earlier gens.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37158>
 2025-09-15 10:59:04 +00:00
Boris Brezillon 741df48085 panvk: Stop using panvk_image_can_use_afbc() in panvk_image_can_use_mod() 
panvk_image_can_use_afbc() doesn't know about depth/stencil format
lowering, and does the AFBC format check on the wrong format if planar
depth/stencil is enabled. Inline what we need from this helper in
panvk_image_can_use_mod(). Ultimately we should make it so that
panvk_image_can_use_afbc() uses panvk_image_can_use_mod() and not the
other way around.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37158>
 2025-09-15 10:59:04 +00:00
Boris Brezillon 2cd851a55f panvk: Pass an image to panvk_plane_count() 
We're going to support Z24S8 planar images, but only on v9+. Let's
pass an image to panvk_plane_index() so we can extract the stencil
plane index from the number of planes instead of basing it only on the
format.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37158>
 2025-09-15 10:59:04 +00:00
Boris Brezillon 7ac76d4e91 panvk: Initialize panvk_image::plane_count early 
We are about to use it at initialization time, so let's make sure it's
initialized as early as possible. We defer the initialization to a helper
because we will extend it to support planar Z24S8.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37158>
 2025-09-15 10:59:04 +00:00
Boris Brezillon 9c2c43c5e4 pan/lib: Hook-up Z24_UNORM_PACKED support 
Only works on Valhall for now.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37158>
 2025-09-15 10:59:04 +00:00
Boris Brezillon 18f352090d util/format: Add a Z24_UNORM_PACKED format 
Mali GPUs support Z24_UNORM stored on three bytes instead of four. Add
a new format for this case.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37158>
 2025-09-15 10:59:04 +00:00