Commit Graph

3058 Commits

Author SHA1 Message Date
Jesse Natalie 3c8bcdc863 nir: Add a new opcode for [un]packing doubles
HLSL doesn't support bitcasting a 64bit integer to a double. DXIL
doesn't have generic pack/unpack instructions, so we lower those to
integer bitwise ops. As a result, NIR generic double pack/unpack would
require our backend to emit a bitcast to get a double, but we want
to match HLSL semantics and emit MakeDouble/SplitDouble.

Adding a dedicated opcode for double pack/unpack allows us to add a
pass to emit that instead, which lets our backend emit the right
instruction to pack and unpack doubles.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10063>
2021-04-09 01:54:33 +00:00
Rhys Perry 5f62083c26 nir/gather_info: fix partial masking of compact I/O with location_frac!=0
nir_lower_clip_cull_distance_arrays() can create compact variables with
location_frac!=0.

Fixes: cc7a187411 ("nir/gather_info: implement partial masking of struct and compact I/O")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4554
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10002>
2021-04-08 16:39:48 +00:00
Bas Nieuwenhuizen edb89e7c4d nir: Do not reset shared_size in nir_lower_io.
I'd like to use raw shared intrinsics already for some raytracing
stuff before this pass gets called and this was a real pitfall.

This mirrors scratch_size and constant_data_size.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10094>
2021-04-08 14:39:28 +00:00
Bas Nieuwenhuizen 4ca4de50f7 nir: Remove nir_shader->shared_size.
The same info is in shader_info. Dedupe.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10094>
2021-04-08 14:39:28 +00:00
Bas Nieuwenhuizen 580f1ac473 nir: Extract shader_info->cs.shared_size out of union.
It is valid for all stages, just 0 for most of them. In particular
mesh/task shaders might be using it.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10094>
2021-04-08 14:39:28 +00:00
Bas Nieuwenhuizen 84e0f6dbd8 nir: Fix shader calls with nir_opt_dead_write_vars.
Fixes: 5a28893279 ("spirv,nir: Add ray-tracing intrinsics")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10096>
2021-04-08 11:10:52 +00:00
Alyssa Rosenzweig 1286e73c2c nir/lower_idiv: Add 8-bit and 16-bit lowering path
Roundtrip to a larger float and divide there. The extra details for
mod/rem are handled directly in integer space to simplify verification
of rounding details. The one issue is that the mantissa might be
rounded down which will cause issues; adding 1 unconditionally (proposed
by Jonathan Marek) fixes this. The lowerings here were tested
exhaustively on all pairs of 16-bit integers.

v2: Update idiv lowering per Rhys Perry's comment.

v3: Rewrite lowerings.

v4: Remove useless ftrunc, fix 8-bit issue, simplify code.

v5: Remove useless ffloor

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Tested-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8339>
2021-04-07 15:48:15 +00:00
Alyssa Rosenzweig e91dec1327 nir/lower_idiv: Factor out numer/denom load
No need to duplicate across paths.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8339>
2021-04-07 15:48:15 +00:00
Alyssa Rosenzweig 7b0eb4aa00 nir/lower_idiv: Convert to lower_instructions
Helps deduplicate some code between the two lowering paths. In
particular, it ports the missing 32-bit? check to the precise pass. This
does not change anything immediately: drivers depending on this to lower
16-bit did not work before due to type mismatches and will not work now
since it'll refuse to lower. But that means sub-32-bit idiv can be
lowered more efficiently in an algebraic pass.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8339>
2021-04-07 15:48:15 +00:00
Alyssa Rosenzweig e4da24bd24 nir: Add {i2f, u2f, f2i, f2u} helpers
Convenient for bitsize independent lowerings, will be used in the idiv
lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8339>
2021-04-07 15:48:15 +00:00
Alyssa Rosenzweig 6b19711645 nir: Add nir_type_convert
Generalizes nir_convert_to_bit_size, which we implement as a
special-case.

v2: Take a sized dest type but allow unsized or sized source to address
Jason's feedback. Shorten name.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8339>
2021-04-07 15:48:15 +00:00
Rhys Perry 292ac71a4a nir/lower_tex: handle deref casts
A RDR2 shader has a undef->texture cast which is eventually optimized out.
Without handling NULL from nir_deref_instr_get_variable(), compiling this
shader will result in a crash.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Fixes: bc438c91d9 ("nir/lower_tex: ignore texture_index if tex_instr has deref src")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10038>
2021-04-06 08:35:39 +00:00
Pierre-Eric Pelloux-Prayer bc438c91d9 nir/lower_tex: ignore texture_index if tex_instr has deref src
texture_index is meaningless when a tex_instr has deref src.
Use var->data.binding instead.

This fixes the incorrect lowering on radeonsi where the same
lowering steps was applied to all tex_instr based on the needs
of the first one (since texture_index is always 0).

CC: mesa-stable
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9931>
2021-04-05 10:14:07 +02:00
Rhys Perry cc7a187411 nir/gather_info: implement partial masking of struct and compact I/O
fossil-db (Sienna):
Totals from 138 (0.10% of 138791) affected shaders:
CodeSize: 504060 -> 482136 (-4.35%)
Instrs: 97318 -> 94518 (-2.88%)
Cycles: 389272 -> 378072 (-2.88%)
VMEM: 14397 -> 14614 (+1.51%); split: +1.76%, -0.25%
SMEM: 9088 -> 9024 (-0.70%)
VClause: 2915 -> 2430 (-16.64%)
SClause: 1790 -> 1791 (+0.06%)
PreVGPRs: 5013 -> 4998 (-0.30%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8364>
2021-04-01 10:15:44 +00:00
Alyssa Rosenzweig 8578adeaa6 nir: Unify memory atomics
Avoids some copypaste and makes it easier to see how the different types
relate.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8847>
2021-03-30 00:11:01 +00:00
Eric Anholt 683d3972a6 nir: Update clip_distance_array_size in clip lowering.
If we've added the array, then we should update the info.  This is the
value that gallium drivers setting !PIPE_CAP_CLIP_PLANES have to use in
place of rasterizer->clip_planes_enabled.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9815>
2021-03-26 20:51:18 +00:00
Danylo Piliaiev 2bff8fd53b nir: add nir_shader_as_str function
It would be later used by Turnip in implementation of
VK_KHR_pipeline_executable_properties.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8877>
2021-03-25 13:53:33 +00:00
Mike Blumenkrantz 6900498faa nir: add nir_lower_indirect_builtin_uniform_derefs()
this is a special version of indirect deref lowering which is used by
mesa/st to remove dynamic indexing from builtin uniforms for the lowering
pass in non-packed uniform case

Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9741>
2021-03-23 14:44:48 +00:00
Gert Wollny 318701b803 nir: Add r600 specific sin and cos variants
r600 expect the input values to be normalited by divinding by 2 *PI, so
add an opcode to be able to lower this in nir.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9452>
2021-03-22 15:19:46 +01:00
Gert Wollny 0f5b3c37c5 nir: Add opcodes for fused comp + csel and optimizations
Some backends, like r600 support a fused version of int and float compare
against zero and and csel. Adding these opcodes here makes it possible to
optimize this in nir.

v2: Add rules for float compare + csel

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9452>
2021-03-22 15:19:46 +01:00
Gert Wollny a5747f8ab3 nir: add opcodes for *find_msb_rev and lowering
Some hardware supports a version of find_msb where the bits are counted
starting at the high bit, and this needs some lowering to obtain the
value that is expected by *find_msb

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9452>
2021-03-22 15:19:46 +01:00
Dave Airlie 48080e5bdf nir: lower 64-bit floats to 32-bit first.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9643>
2021-03-22 12:17:14 +10:00
Dave Airlie 01dfd65a2d nir: port fp16 casting code from dxil
This moves the dxil pass to common code and makes dxil
use the new code.

Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9643>
2021-03-22 12:16:59 +10:00
Jesse Natalie 55d153b9f5 nir: Temporarily disable optimizations for MSVC ARM64
There's currently an MSVC optimizer bug which causes a stack overflow
in the compiler if it attempts to optimize fsat.

Acked-by: Rob Clark <robdclark@chromium.org>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9700>
2021-03-21 21:41:41 +00:00
Jason Ekstrand 1ba9c262fd nir: Add image atomic_fmin/fmax intrinsics
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8750>
2021-03-18 00:13:40 +00:00
Caio Marcelo de Oliveira Filho 302183d635 nir: Handle deref_atomic_fadd in a couple of passes
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8750>
2021-03-18 00:13:40 +00:00
Jason Ekstrand 4079279051 anv/apply_pipeline_layout: Add support for A64 descriptor access
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
2021-03-17 17:49:59 +00:00
Jason Ekstrand c8748771bb nir/lower_io: Support global addresses for UBOs in nir_lower_explicit_io
For nir_address_format_64bit_global_32bit_offset and
nir_address_format_64bit_bounded_global, we use a new intrinsics which
take the base address and offset as separate parameters.  For bounds-
checked access, the bound is also included in the intrinsic.  This gives
the drive more control over the bounds checking so that UBOs don't
suddenly become massively more expensive.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
2021-03-17 17:49:59 +00:00
Jason Ekstrand 93a3f18719 nir: Add a new 64+32-bit address format
This is a global address format where you have a 64-bit base pointer and
a 32-bit offset.  It's intentionally identical to 64bit_bounded_global
except nir_lower_explicit_io does no bounds checking with it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
2021-03-17 17:49:59 +00:00
Jason Ekstrand 1ce3660a5a intel/fs,rt: Add a predicate to load_global_const_block
This allows us to do bounds checked A64 block load without the it being
counted as control-flow by NIR.  This means that NIR optimizations like
CSE will be able to work on these the same as a regular load.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
2021-03-17 17:49:58 +00:00
Timur Kristóf 4c5c610f1d nir: Add AMD-specific Geometry Shader related intrinsics.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9201>
2021-03-17 12:42:23 +00:00
Timur Kristóf 38df949f98 nir: Add tessellation related AMD-specific intrinsics.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9201>
2021-03-17 12:42:23 +00:00
Timur Kristóf 744dc74078 nir: Add nir_opt_offsets to fold const adds into load/store offsets.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9201>
2021-03-17 12:42:23 +00:00
Timur Kristóf eee3435757 nir: Add AMD-specific buffer load/store intrinsics.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9201>
2021-03-17 12:42:23 +00:00
Timur Kristóf c2a81ebe19 nir: Add default unsigned upper bound configuration.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9201>
2021-03-17 12:42:23 +00:00
Timur Kristóf 8ebb8d31af nir: Add unsigned upper bound for TCS load_invocation_id.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9201>
2021-03-17 12:42:23 +00:00
Timur Kristóf 9fbfafb57a nir: Shrink vectors for load_shared.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9201>
2021-03-17 12:42:23 +00:00
Timur Kristóf 084863bb5d nir: Fix unsigned upper bound of local_invocation_index for non-CS stages.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9201>
2021-03-17 12:42:23 +00:00
Timur Kristóf 132171dc4e nir: Add a few more algebraic optimizations to help address calculation.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9201>
2021-03-17 12:42:23 +00:00
Timur Kristóf 9f9b0f583b nir: Add nir_builder helper for I/O address offset calculations.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9201>
2021-03-17 12:42:23 +00:00
Timur Kristóf f6f68d5cf1 nir: Add new nir_builder helpers for iadd with no_unsigned_wrap.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9201>
2021-03-17 12:42:23 +00:00
Rhys Perry 5bc42ce579 nir: Don't update base in vectorize_loads()
The offset is already updated with consideration to the base above under
"/* update the offset */".

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9201>
2021-03-17 12:42:23 +00:00
Iago Toral Quiroga f29de817eb compiler/glsl: call util_cpu_detect from glsl_type_singleton_init_or_ref
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Closes: #4393
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9457>
2021-03-17 08:15:36 +01:00
Hyunjun Ko d82b58c03e nir: Set access at lower_ubo_vec4
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>

Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9125>
2021-03-17 01:09:30 +00:00
Ian Romanick da7389eced nir/range_analysis: Simplify analysis of bcsel
union_ranges was previously guarded by 'ifndef NDEBUG'.  After removing
that, I noticed that the two tables were identical.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9108>
2021-03-11 22:00:30 +00:00
Ian Romanick 7019cd84c0 nir/search: Use range analysis for is_finite
There are only a couple patterns that use is_finite, so the changes
aren't huge.  Mostly shaders from Batman Arkham City and a few shaders
from Shadow of the Tomb Raider were affected.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

Tiger Lake
Instructions in all programs: 160902591 -> 160902489 (-0.0%)
SENDs in all programs: 6812270 -> 6812270 (+0.0%)
Loops in all programs: 38225 -> 38225 (+0.0%)
Cycles in all programs: 7429003266 -> 7428992369 (-0.0%)
Spills in all programs: 192582 -> 192582 (+0.0%)
Fills in all programs: 304539 -> 304539 (+0.0%)

Ice Lake
Instructions in all programs: 145301634 -> 145301460 (-0.0%)
SENDs in all programs: 6863890 -> 6863890 (+0.0%)
Loops in all programs: 38219 -> 38219 (+0.0%)
Cycles in all programs: 8798589772 -> 8798575869 (-0.0%)
Spills in all programs: 216880 -> 216880 (+0.0%)
Fills in all programs: 334250 -> 334250 (+0.0%)

Skylake
Instructions in all programs: 135892010 -> 135891836 (-0.0%)
SENDs in all programs: 6802916 -> 6802916 (+0.0%)
Loops in all programs: 38216 -> 38216 (+0.0%)
Cycles in all programs: 8442597324 -> 8442583202 (-0.0%)
Spills in all programs: 194839 -> 194839 (+0.0%)
Fills in all programs: 301116 -> 301116 (+0.0%)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9108>
2021-03-11 22:00:30 +00:00
Ian Romanick f4a7dbc58f nir/range_analysis: Fix analysis of fmin, fmax, or fsat with NaN source
Recall that when either value is NaN, fmax will pick the other value.
This means the result range of the fmax will either be the "ideal"
result range (calculated above) or the range of the non-NaN value.

Previously, something like fmax({gt_zero}, {lt_zero, is_a_number}) would
return a range of gt_zero.  However, if the "gt_zero" parameter is NaN,
the actual result will be the "lt_zero" parameter.

This analysis depends on the is_a_number analysis also added in this MR.
Assuming this doesn't cause any unforeseen problems, I believe we should
wait a bit, then nominate a subset of the series for the stable
branches.

This fixes the piglit tests

    tests/spec/glsl-1.30/execution/range_analysis_fmax_of_nan.shader_test
    tests/spec/glsl-1.30/execution/range_analysis_fmin_of_nan.shader_test

from https://gitlab.freedesktop.org/mesa/piglit/-/merge_requests/463.

Even with the added fsat fixes, range_analysis_fsat_of_nan.shader_test
still fails.  There are some other issues there that will be addressed
in later commits (in another MR).

v2: Add fsat fixes.  Suggested by Rhys.

Fixes: 405de7ccb6 ("nir/range-analysis: Rudimentary value range analysis pass")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

Shader-db results:

All Intel platforms had similar results. (Tiger Lake shown)
total instructions in shared programs: 21049290 -> 21049314 (<.01%)
instructions in affected programs: 3175 -> 3199 (0.76%)
helped: 0
HURT: 17
HURT stats (abs)   min: 1 max: 3 x̄: 1.41 x̃: 1
HURT stats (rel)   min: 0.20% max: 1.89% x̄: 0.97% x̃: 0.92%
95% mean confidence interval for instructions value: 1.09 1.73
95% mean confidence interval for instructions %-change: 0.75% 1.19%
Instructions are HURT.

total cycles in shared programs: 855136176 -> 855136406 (<.01%)
cycles in affected programs: 37579 -> 37809 (0.61%)
helped: 0
HURT: 17
HURT stats (abs)   min: 12 max: 20 x̄: 13.53 x̃: 14
HURT stats (rel)   min: 0.17% max: 1.13% x̄: 0.79% x̃: 0.91%
95% mean confidence interval for cycles value: 12.53 14.53
95% mean confidence interval for cycles %-change: 0.63% 0.94%
Cycles are HURT.

Fossil-db results:

Tiger Lake
Instructions in all programs: 160901033 -> 160902591 (+0.0%)
SENDs in all programs: 6812270 -> 6812270 (+0.0%)
Loops in all programs: 38225 -> 38225 (+0.0%)
Cycles in all programs: 7430016795 -> 7429003266 (-0.0%)
Spills in all programs: 192582 -> 192582 (+0.0%)
Fills in all programs: 304539 -> 304539 (+0.0%)

Ice Lake
Instructions in all programs: 145299102 -> 145301634 (+0.0%)
SENDs in all programs: 6863890 -> 6863890 (+0.0%)
Loops in all programs: 38219 -> 38219 (+0.0%)
Cycles in all programs: 8798390846 -> 8798589772 (+0.0%)
Spills in all programs: 216880 -> 216880 (+0.0%)
Fills in all programs: 334250 -> 334250 (+0.0%)

Skylake
Instructions in all programs: 135889478 -> 135892010 (+0.0%)
SENDs in all programs: 6802916 -> 6802916 (+0.0%)
Loops in all programs: 38216 -> 38216 (+0.0%)
Cycles in all programs: 8442624166 -> 8442597324 (-0.0%)
Spills in all programs: 194839 -> 194839 (+0.0%)
Fills in all programs: 301116 -> 301116 (+0.0%)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9108>
2021-03-11 22:00:30 +00:00
Ian Romanick aa5d38decd nir/range_analysis: Add "is a number" range analysis tracking
This commit is necessary to support "nir/range_analysis: Fix analysis of
fmin and fmax with NaN".

No shader-db or fossil-db changes on any Intel platform.

v2: Pack and unpack is_a_number.

v3: Don't set is_a_number of integer constants.  The bit pattern might
be NaN.

v4: Update handling of b2i32.  intBitsToFloat(int(true)) is
1.401298464324817e-45.  Return a value consistent with that.

Fixes: 405de7ccb6 ("nir/range-analysis: Rudimentary value range analysis pass")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9108>
2021-03-11 22:00:30 +00:00
Ian Romanick d4f21b53f2 nir/range_analysis: Add "is finite" range analysis tracking
The obvious changes to nir_search_helpers.h are in a separate commit to
limit the scope of this change.  These additions are really only needed
to support the next commit "nir/range_analysis: Add "is a number" range
analysis tracking".  This reduction in scope is intended to increase the
suitability for stable branches.

No shader-db or fossil-db changes on any Intel platform.

v2: Pack and unpack is_finite.

v3: Split nir_search_helpers.h changes into a separate commit.

v4: Remove assertion intended for the next commit.  Update is_finite
comment for fsign.  Both noticed by Rhys.  Fix is_finite handling for
load_const vectors.  If any element is not finite, set the flag to
false.  This is the same way is_integral is already handled.

v5: Update handling of b2i32.  intBitsToFloat(int(true)) is
1.401298464324817e-45.  Return a value consistent with that.

Fixes: 405de7ccb6 ("nir/range-analysis: Rudimentary value range analysis pass")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9108>
2021-03-11 22:00:30 +00:00
Ian Romanick 86fb53b1be nir/range_analysis: Refactor fsat handling
This will greatly simplify a later commit.  The assert(r.is_integral) in
the eq_zero case is dropped because I don't think it's useful anymore.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9108>
2021-03-11 22:00:30 +00:00