Commit Graph

7187 Commits

Author SHA1 Message Date
Vinson Lee 9eb010ee1e anv: Fix assertion.
Fix defect reported by Coverity Scan.

Assign instead of compare (PW.ASSIGN_WHERE_COMPARE_MEANT)
assign_where_compare_meant: use of "=" where "==" may have been intended

Fixes: 35315c68a5 ("anv: Use the common wrapper for GetPhysicalDeviceFormatProperties")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13395>
2021-10-18 09:04:47 +00:00
Jason Ekstrand 3ace6b968b compiler/types: Add a texture type
This is separate from images and samplers.  It's a texture (not a
storage image) without a sampler.  We also add C-visible helpers to
convert between sampler and image types.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13389>
2021-10-16 05:49:34 +00:00
Jason Ekstrand 956199e870 nir: s/nir_var_mem_image/nir_var_image/g
We typically use nir_var_mem_* for stuff that has an explicit byte-based
memory layout.  Images are opaque.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13386>
2021-10-16 03:47:10 +00:00
Dylan Baker e73096bd6d meson: use gtest protocol for gtest based tests when possible
With the `gtest` protocol meson will add some extra arguments to the
test to generate better junit results, which may be useful. This
protocol is only available in meson 0.55.0+, so keep using the default
`exitcode` protocol for meson older than that.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8484>
2021-10-16 03:22:24 +00:00
Marcin Ślusarz d05f7b4a2c intel: fix INTEL_DEBUG environment variable on 32-bit systems
INTEL_DEBUG is defined (since 4015e1876a) as:

 #define INTEL_DEBUG __builtin_expect(intel_debug, 0)

which unfortunately chops off upper 32 bits from intel_debug
on platforms where sizeof(long) != sizeof(uint64_t) because
__builtin_expect is defined only for the long type.

Fix this by changing the definition of INTEL_DEBUG to be function-like
macro with "flags" argument. New definition returns 0 or 1 when
any of the flags match.

Most of the changes in this commit were generated using:
for c in `git grep INTEL_DEBUG | grep "&" | grep -v i915 | awk -F: '{print $1}' | sort | uniq`; do
    perl -pi -e "s/INTEL_DEBUG & ([A-Z0-9a-z_]+)/INTEL_DBG(\1)/" $c
    perl -pi -e "s/INTEL_DEBUG & (\([A-Z0-9_ |]+\))/INTEL_DBG\1/" $c
done
but it didn't handle all cases and required minor cleanups (like removal
of round brackets which were not needed anymore).

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13334>
2021-10-15 19:55:14 +00:00
Caio Marcelo de Oliveira Filho 29177c7cee intel/compiler: Build all tests in a single binary
With gtest is possible to filter execution and run only a specific
test suite or individual test, so there's no particular reason here to
generate multiple binaries for the tests of a single module.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13303>
2021-10-15 10:06:51 -07:00
Caio Marcelo de Oliveira Filho 35b6990706 intel/compiler: Rename vec4 test fixtures
Include vec4 in their names to avoid same names as the fs
counterparts.  This will allow compiling all the tests together in the
future.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13303>
2021-10-15 10:06:51 -07:00
Jason Ekstrand e6cce80976 intel/fs: Stop emitting TGM fences for nir_var_mem_ssbo
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>
2021-10-15 14:58:56 +00:00
Caio Marcelo de Oliveira Filho 26582db077 anv: Use nir_foreach_image_variable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>
2021-10-15 14:58:55 +00:00
Caio Marcelo de Oliveira Filho 2d7065ef04 intel/fs: Consider nir_var_mem_image for TGM fences
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>
2021-10-15 14:58:55 +00:00
Clayton Craft b2ef7e6d6b anv: don't advertise vk conformance on GPUs that aren't conformant
This sets the conformance version to 0.0.0.0 for GPUs that have
incomplete support for vulkan, so that it's easier to check if vulkan is
fully supported by a GPU at runtime for applications/libraries.

    $ vulkaninfo|grep conf
    MESA-INTEL: warning: Ivy Bridge Vulkan support is incomplete
        conformanceVersion = 0.0.0.0

Signed-off-by: Clayton Craft <clayton@craftyguy.net>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13275>
2021-10-14 22:16:30 +00:00
Dave Airlie c4323dc846 brw/nir: remove unused function prototypes.
These got moved into common code a good while ago.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13328>
2021-10-13 22:52:59 +00:00
Anuj Phogat a98ece61e9 anv: Enable tessellation redistribution
This patch adds Tessellation Distribution on top of Geometry
Distribution. Using recommended values based on performance studies
across a range of workloads.

Rework:
- Add comment for new packet bits (Sagar)

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12091>
2021-10-13 22:36:54 +00:00
Anuj Phogat 867e2e0716 anv: Enable geometry distribution
Using recommended values based on performance studies across a range
of workloads.

Rework:
 * Always enable geometry distribution
 * Set ListCutIndexEnable if primitive restart is enabled
 * Set distribution mode based on TEEnable
 * Add comment explaining the 3DSTATE_VFG bits (Sagar)

v2:
- Emit 3DSTATE_VFG dynamically based on primitive restart (Ken)

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12091>
2021-10-13 22:36:54 +00:00
Anuj Phogat 1d224e7f14 genxml/gen125: Update 3DSTATE_TE fields
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12091>
2021-10-13 22:36:54 +00:00
Jordan Justen 9a7e54b87f intel/genxml: Update genxml to support tessellation/geometry distribution
Rework:
- Fix 3DSTATE_VFG opcode (Lionel)
- Fix distribution mode values (Sagar)
- Update 3DSTATE_VFG fields (Anuj)

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12091>
2021-10-13 22:36:54 +00:00
Caio Marcelo de Oliveira Filho 94e07058ee intel/compiler: Remove unused ret declaration
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13340>
2021-10-13 17:24:29 +00:00
Caio Marcelo de Oliveira Filho bd2cc4b916 intel/compiler: Convert test_eu_compact to use gtest
Be consistent with the other test suites in intel/compiler.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13340>
2021-10-13 17:24:29 +00:00
Lionel Landwerlin 9fb2c84768 isl: only bump the min row pitch for display when not specified
If the ISL caller didn't specify a row_pitch_B, let's use the
NVIDIA/AMD requirements. Otherwise keep using the Intel requirement,
as the caller is likely trying to import a buffer and if we can deal
with that row_pitch_B, we should accept it.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a3a4517f41 ("isl: Work around NVIDIA and AMD display pitch requirements")
Reported-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13024>
2021-10-13 14:46:49 +00:00
Lionel Landwerlin 47ff6767ea anv: fill correct surface state for lowered storage image
Small typo/copy-paste.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c0093c4668 ("anv: Flip around the way we reason about storage image lowering")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13332>
2021-10-13 14:33:14 +00:00
Tapani Pälli d729038c07 anv: use vk_object_zalloc for wsi fences created
Otherwise we hit assert in vk_object_base_assert_valid when attemping to
create handle from anv_fence with unknown base type.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13330>
2021-10-13 11:59:17 +00:00
Tapani Pälli 840c79fc9b anv/android: fix parameters given for vk_common_QueueSubmit
Common queue submit expects pWaitDstStageMask to be set per each
semaphore (as per Vulkan spec) and crashes if these are not given
properly.

This fixes crashes seen when running vulkan apps on Android.

v2: change the VkPipelineStageFlags given (Lionel)

Fixes: b996fa8efa ("anv: implement VK_KHR_synchronization2")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13305>
2021-10-13 06:00:56 +00:00
Felix DeGrood 5bf6987873 anv: dirty only state impacted by blorp_exec
Instead of dirtying all state after blorp operations,
avoid dirtying state that blorp never touches.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5077
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12567>
2021-10-13 04:31:34 +00:00
Jason Ekstrand a64d90026b anv: Use the common WSI wrappers
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
2021-10-13 00:06:15 +00:00
Jason Ekstrand 916c9335b4 meson: Add and use an idep for Vulkan WSI
Acked-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
2021-10-13 00:06:15 +00:00
Nanley Chery 10be870c72 anv: Tile cache flush for depth before fast clear
Instead of doing a tile cache flush after slow clears, resolves, and
ambiguates, do it before fast clears of HIZ_CCS_WT surfaces. This agrees
with the Bspec.

Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11539>
2021-10-12 18:05:46 +00:00
Nanley Chery 81e9c25c1b anv: Allow HIZ_CCS_WT with subpass self-dependencies
This unblocks later commits that aim to align the driver with the tile
cache flushing requirements in the Bspec.

Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11539>
2021-10-12 18:05:46 +00:00
Lionel Landwerlin ce3dd1375f anv: implement VK_KHR_format_feature_flags2
v2: fix SAMPLED_IMAGE_DEPTH_COMPARISON_BIT_KHR (Ivan)

v3: Fixup VK_FORMAT_FEATURE_2_STORAGE_IMAGE_BIT_KHR setting (Ivan)
    Add missing drm-modifiers/android bits (Lionel)

v4: Avoid duplicating get_ahw_buffer_format_properties() (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>
2021-10-11 10:29:12 -05:00
Lionel Landwerlin 01d1ec292a anv: start computing KHR_format_features2 flags for storage images
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>
2021-10-11 10:29:12 -05:00
Jason Ekstrand c0093c4668 anv: Flip around the way we reason about storage image lowering
There are roughly two cases when it comes to storage images.  In the
easy case, we have full hardware support and we can just emit a typed
read/write message in the shader and we're done.  In the more complex
cases, we may need to fall back to a typed read with a different format
or even to a raw (SSBO) read.

The hardware has always had basically full support for typed writes all
the way back to Ivy Bridge but typed reads have been harder to come by.
Starting with Skylake, we finally have enough that we at least have a
format of the right bit size but not necessarily the right format so we
can use a typed read but may still have to do an int->unorm or similar
cast in the shader.

Previously, in ANV, we treated lowered images as the default and write-
only as a special case that we can optimize.  This flips everything
around and treats the cases where we don't need to do any lowering as
the default "vanilla" case and treats the lowered case as special.
Importantly, this means that read-write access to surfaces where the
native format handles typed writes now use the same surface state as
write-only access and the only thing that uses the lowered surface state
is access read-write access with a format that doesn't support typed
reads.  This has the added benefit that now, if someone does a read
without specifying a format, we can default to the vanilla surface and
it will work as long as it's a format that supports typed reads.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>
2021-10-11 10:29:09 -05:00
Lionel Landwerlin fa251cf111 intel/nir: allow unknown format in lowering of storage images
We're about to allow unknown format for specific formats in Anv.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>
2021-10-11 10:29:09 -05:00
Lionel Landwerlin 0f8efc2b08 anv: switch to use VkFormatFeatureFlags2KHR internally
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>
2021-10-11 10:29:09 -05:00
Jason Ekstrand 35315c68a5 anv: Use the common wrapper for GetPhysicalDeviceFormatProperties
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>
2021-10-11 10:29:07 -05:00
Marcin Ślusarz 3b9b6db031 anv: fix potential integer overflow
Description by Coverity:
"Unintentional integer overflow (OVERFLOW_BEFORE_WIDEN)
overflow_before_widen: Potentially overflowing expression 1 << b with type int
(32 bits, signed) is evaluated using 32-bit arithmetic, and then used in
a context that expects an expression of type VkAccessFlags2KHR (64 bits,
unsigned)"

CID: 1492745
CID: 1492748

Fixes: b996fa8efa ("anv: implement VK_KHR_synchronization2")
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13284>
2021-10-11 10:30:48 +00:00
Yiwei Zhang 8ebf0d1105 radv/anv android: rename buffer usage camera mask
AHARDWAREBUFFER_USAGE_CAMERA_MASK enum is defined later and gets
included in the stub headers.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13255>
2021-10-09 00:42:32 +00:00
Sagar Ghuge 35fd101ad2 isl: Use software programmable render compression format encoding
Instead of relying on hardcoded (legacy) encoding format, use software
programmable encoding for render compression format.

v2: (Nanley)
- Fix param mismatch
- Set RenderCompressionFormat unconditionally
- Fix commit message

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12686>
2021-10-08 18:56:14 +00:00
Sagar Ghuge dd54e9125a isl: Add helper to return render compression format encoding
v2:
- Fix typo (Marcin)
- Fix comment (Nanley)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12686>
2021-10-08 18:56:14 +00:00
Sagar Ghuge e5265c023d intel/genxml: Add new bit fields Render Compression Format
Add RenderCompressionFormat bit field in 3DSTATE_DEPTH/STENCIL_BUFFER
and RENDER_SURFACE_STATE packet to use compression format encoding for
Unified Losless Compression.

v2: (Nanley)
- Drop default value.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12686>
2021-10-08 18:56:14 +00:00
Tapani Pälli 70f193ffcf intel/isl: FXT1 support was removed on Gfx12.5
v2: cleanup (Jordan Justen)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13241>
2021-10-08 15:45:21 +00:00
Jordan Justen 8e735dc72c intel/isl: Add mocs settings for DG2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12712>
2021-10-08 00:48:10 +00:00
Chia-I Wu 8cce6281e6 util/vector: make util_vector_init harder to misuse
Make u_vector_init a wrapper to u_vector_init_pot.  Let both take
(element_count, element_size) as parameters.

Motivated by eed0fc4caf ("vulkan/wsi/wayland: fix an invalid
u_vector_init call")

v2: rename u_vector_init_pot to u_vector_init_pow2

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13201>
2021-10-08 00:15:11 +00:00
Jason Ekstrand 5b42f1a374 vulkan/device: Use vk_error
Tested-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13045>
2021-10-07 20:51:36 +00:00
Jason Ekstrand 88a8b937b5 anv: Use the common vk_error and vk_errorf helpers
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13045>
2021-10-07 20:51:36 +00:00
Jason Ekstrand f6d52768d6 anv/queue: Plumb the queue through all the queue_submit calls
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13045>
2021-10-07 20:51:36 +00:00
Jason Ekstrand ab36efcb4c anv: Drop unused logging helpers
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13045>
2021-10-07 20:51:36 +00:00
Jason Ekstrand ad27b27389 anv: s/vk_error/anv_error/g
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13045>
2021-10-07 20:51:36 +00:00
Jason Ekstrand aa94220d7d anv: Stop printing descriptor pool allocation failures
The VK_ERROR_FRAGMENTED_POOL and VK_ERROR_OUT_OF_POOL_MEMORY errors are
not as exceptional cases as most.  These are expected to be hit by
applications in the normal course of doing their thing.  Probably best
not to spam stderr and the debug logs with them.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13045>
2021-10-07 20:51:35 +00:00
Jason Ekstrand 31148ee88e anv: drop a misplaced and wrong comment
We do actually use vk_error in the one place we check that limit.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13045>
2021-10-07 20:51:35 +00:00
Boris Brezillon b47090c5b3 spirv: Always declare FragCoord as a sysval
Now that all spirv_to_nir() users take care of converting sysvals to
varyings, we can unconditionally declare FragCoord as a sysval.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13017>
2021-10-07 19:45:35 +00:00
Boris Brezillon 4b62e90e71 spirv: Let spirv_to_nir() users turn sysvals into input varyings
This is an attempt at simplifying the spirv_to_nir() backend when it
comes to choosing between system values and input varyings. Let's patch
drivers to do the sysval to input varying conversion on their own so we
can get rid of the frag_coord_is_varying field in spirv_to_nir_options
and unconditionally create create sysvals for FragCoord, FrontFacing and
PointCoord inputs instead of adding new xxx_is_{sysval,varying} flags.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13017>
2021-10-07 19:45:35 +00:00