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293 Commits

Author SHA1 Message Date
Mark Janes
acb2a7d2ec intel/dev: report stepping for TGL systems 
Workaround 14010672564 requires a check for the TGL B0 stepping.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22458>
 2023-04-26 02:00:17 +00:00
Mark Janes
47ac056d0f intel/dev: update mesa_defs.json from defect database 
These modifications represent:

 * changes to defects made since Feb 16, 2023
 * changes to automated processing of defect state

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22458>
 2023-04-26 02:00:17 +00:00
Lionel Landwerlin
c61101f151 intel/dev: set a default valid kmd_type 
src/intel/perf/intel_perf_query_layout.c needs a valid kmd type to
look at the metrics

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 757e2dd692 ("intel/perf: Disable it for Xe KMD")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22257>
 2023-04-03 23:34:17 +00:00
Mark Janes
8eceff48cd intel/dev: use GFX_VERx10 to detect genX compilation 
Depending on the ordering of includes, GFX_VER may not defined for
intel_device_info.h.  The failure mode of this case is silent:
BITSET_TEST will be called when it could be compiled out.

GFX_VERx10 should be used in place of GFX_VER.  GFX_VERx10 is defined
by a compiler flag, and is always present for genX compilation units.

Fixes: 3c9a8f7a6d ("intel/dev: generate helpers to identify platform workarounds")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21908>
 2023-03-23 23:23:52 +00:00
Mark Janes
8c78dd6320 intel/dev: fix macro naming convention in gen_wa_helpers.py 
intel_device_info.h tests macros in the form `INTEL_WA_{id}_GFX_VER`.
gen_wa_helpers.py produced macros in the form `INTEL_GFX_VER_WA_{id}`

Change the generated code to follow intel_device_info.h

Fixes: 3c9a8f7a6d ("intel/dev: generate helpers to identify platform workarounds")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21908>
 2023-03-23 23:23:52 +00:00
Mark Janes
52c71cf959 intel/dev: fix macro string concatenation for INTEL_WA_{id}_GFX_VER 
`INTEL_WA_##id_GFX_VER` evaluates to `INTEL_WA_id_GFX_VER`
instead of numbered identifiers like `INTEL_WA_220579888_GFX_VER`.

Fixes: 3c9a8f7a6d ("intel/dev: generate helpers to identify platform workarounds")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21908>
 2023-03-23 23:23:52 +00:00
Lionel Landwerlin
7941db652e intel/dev: fold Gfx12 URB entries in Gfx12 HW info 
Also add a non-zero URB size for intel_stub_gpu

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21949>
 2023-03-23 08:08:49 +00:00
Lionel Landwerlin
25cb4805f5 intel/devinfo: initialize pci_device_id with from_pci_id() 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21949>
 2023-03-23 08:08:49 +00:00
Lionel Landwerlin
19c9391a2c intel/devinfo: dedicated entries for XeHP 
Also fixing the max URB entries for VS stage.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reported-by: Chuansheng Liu <chuansheng.liu@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21949>
 2023-03-23 08:08:49 +00:00
Lionel Landwerlin
de5ee891f0 intel/dev: use generated WA helpers for Wa_22012575642 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21949>
 2023-03-23 08:08:49 +00:00
Lionel Landwerlin
9b1660c727 intel/devinfo: printout URB entries 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21949>
 2023-03-23 08:08:49 +00:00
Lionel Landwerlin
a42a5bf87e intel/devinfo: add an option to pick platform to print 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21949>
 2023-03-23 08:08:49 +00:00
José Roberto de Souza
491887c9f2 intel: Add TODO about removal of 2Mb alignment in i915 
Xe kmd don't suffer this yet because it still lacks MTL support.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21972>
 2023-03-20 17:18:04 +00:00
José Roberto de Souza
7dc8474c3b intel: Set mem_alignment in Xe kmd 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21972>
 2023-03-20 17:18:04 +00:00
José Roberto de Souza
2ab3d5f436 intel: Move memory aligment information to intel_device_info 
This same information is also used in ANV, so intel_device_info is
a better place to have it.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21972>
 2023-03-20 17:18:03 +00:00
Jordan Justen
48ff68820e intel/dev: Enable MTL PCI ids 
Ref: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/drm/i915_pciids.h?h=v6.0-rc4#n736
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18481>
 2023-03-13 10:17:51 +00:00
Sagar Ghuge
9a34b2ab0e intel/compiler: Add swsb_stall debug option 
When enabled, on gfx12 plus, we will add the sync nop instruction after
each instruction to make sure that current instruction depends on the
previous instruction explicitly.

This option will help us to get a hint if something is missing or broken
in software scoreboard pass.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21797>
 2023-03-10 06:55:39 +00:00
Lionel Landwerlin
8dd960e056 anv/iris: report counter symbols with debug option 
v2: rename to INTEL_DEBUG=perf-symbol-names

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17672>
 2023-03-08 12:45:43 +00:00
José Roberto de Souza
a24d93aa89 intel/dev: Query and compute hardware topology for Xe 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21368>
 2023-03-03 05:25:35 +00:00
José Roberto de Souza
4b81a80f55 intel/dev: Implement Xe functions to handle hwconfig 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21368>
 2023-03-03 05:25:35 +00:00
José Roberto de Souza
bc24091c52 intel/dev: Implement Xe functions to fill intel_device_info 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21368>
 2023-03-03 05:25:35 +00:00
José Roberto de Souza
545d7e07ca intel/dev: Add INTEL_KMD_TYPE_XE 
As mentioned in the previous patch, if intel-xe-kmd is disabled
it will fail to detected in run time but it will still compile all
Xe files.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21368>
 2023-03-03 05:25:35 +00:00
Mark Janes
276f4a9d8c intel/dev: Print required workarounds with intel_dev_info 
With the addition of workarounds, the output from this tool is more
verbose than some users will want.  Provide optional parameters for
enabling hwconfig and workaround details.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21639>
 2023-03-03 04:55:08 +00:00
Mark Janes
3c9a8f7a6d intel/dev: generate helpers to identify platform workarounds 
Workarounds for defects in Intel silicon have been manually
implemented:

 - consult defect database for the current platform

 - add workaround code behind platform ifdef or devinfo->ver checks

Some bugs have occurred due to the manual process.  Typical failure
modes:

 - defect database is updated after a platform is enabled

 - version checks are overly broad (eg gfx11+) for defects that were
   fixed (eg in gfx12)

 - version checks are too narrow for defects that were extended to
   subsequent platforms.

 - missed workarounds

This commit automates workaround handling:

 - Internal automation queries the defect database to collate and
   summarize defect documentation in json.

 - mesa_defs.json describes all public defects and impacted platforms.
   Defects which are extended to subsequent platforms are listed under
   the original defect.

 - gen_wa_helpers.py generates workaround helpers to be called
   in place of version checks:

   - NEEDS_WORKAROUND_{ID} provides a compile time check suitable for
     use in genX routines.

   - intel_device_info_needs_wa() provides a more precise runtime
     check, differentiating platforms within a generation and
     platform steppings.

Internal automation will generate new mesa_defs.json as needed.
Workarounds enabled with these helpers will apply correctly based on
updated information in Intel's defect database.

Reviewed-by: Dylan Baker <dylan@pnwbakers>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20825>
 2023-03-02 00:01:27 +00:00
Dylan Baker
a0fa31bcdd intel/dev: create a helper dependency for libintel_dev 
This ensures that users of libintel_dev.a won't be compiled until
include files are generated, and that they are recompiled when the
header changes.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20825>
 2023-03-02 00:01:27 +00:00
Marcin Ślusarz
e74a3284f5 anv: halve the push constants space in mesh pipelines 
It's only used by fragment shaders, so halving it matches the size
used in the most optimal primitive pipeline (VS + FS).

This change frees some URB space for mesh and task shaders and as
a result improves vk_meshlet_cadscene performance by up to 2%,
depending on the model.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21559>
 2023-02-28 20:18:01 +00:00
Caio Oliveira
ea0ec8c562 intel: Add extra zeros at the end of debug identifiers 
Add at least a full aligned uint64_t of zero padding at the end
to make the identifiers easier to spot.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21479>
 2023-02-24 04:57:40 +00:00
José Roberto de Souza
a364f23a6c intel: Make gen12 URB space reservation dependent on compute engine presence 
Tigerlake PRM: Volume 2c: Command Reference: Registers Part 2 - Registers M through Z
RCU_MODE :: Compute Engine Enable

   This bit indicates if Compute Engine (a.k.a Dual Context or Multi
   Context) is enabled or not. This bit must be treated as global
   control for enabling and disabling of compute engine. Hardware
   allocates required resources for the compute engine based on this
   bit.
   ....
   HW reserves 4KB of URB space...

Right now no gen12 platform has Dual Context enabled in kernel side,
exposing a compute engine but that can change, so here adding
has_compute_engine to intel_device_info and only reserving URB space
if compute engine is available.

While at it also fixing the error path when pb_slabs_init() fails.

Bspec: 46034
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21031>
 2023-02-23 14:27:30 +00:00
Lionel Landwerlin
295dd6f515 intel/dev: add a default urb value for intel_stub_gpu on dg2 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21249>
 2023-02-13 09:38:06 +00:00
José Roberto de Souza
c8626a20bb anv: Start to move anv_gem_stubs.c to kmd backend 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20948>
 2023-02-09 02:57:32 +00:00
José Roberto de Souza
9fc224631c intel: Add intel_memory_class_instance 
This is a KMD independent struct to hold memory class and instance
values.

drm_i915_gem_memory_class_instance usage will be gradually replaced.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20948>
 2023-02-09 02:57:32 +00:00
Jonathan Gray
a23e04b673 intel/dev: remove invalid EHL pci id 
removed in linux
0e8e272f1368 ("drm/i915/ehl: Remove invalid PCI ID")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21129>
 2023-02-06 16:48:39 +00:00
Marcin Ślusarz
432e263284 intel/compiler: fine-grained control of dispatch widths 
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> [v2]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20854>
 2023-01-27 11:00:41 +00:00
José Roberto de Souza
2c42641994 intel/dev: Detect what is the kernel mode driver loaded 
Intel GPUs will have a new kernel mode driver, support for some
platforms will overlap so we will need to detect in runtime what is
the kernel mode driver loaded for each device.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20773>
 2023-01-25 09:16:55 -08:00
José Roberto de Souza
c1d99283e6 intel/dev: Split hwconfig i915 specific code 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20437>
 2023-01-20 17:26:08 +00:00
José Roberto de Souza
b3b769894e intel/dev: Move i915 code to i915/intel_device_info.c 
No behavior changes here.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20437>
 2023-01-20 17:26:08 +00:00
José Roberto de Souza
1332702cf4 intel/dev: Export functions that will be used by different kernel drivers 
No behavior changes here.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20437>
 2023-01-20 17:26:08 +00:00
Nico Cortes
29adbb132f Revert "intel/compiler: fine-grained control of dispatch widths" 
This reverts commit bed18ab3e2.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8063
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20654>
 2023-01-12 00:33:25 +00:00
Marcin Ślusarz
bed18ab3e2 intel/compiler: fine-grained control of dispatch widths 
Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20535>
 2023-01-11 08:17:12 +00:00
Tapani Pälli
7db1b94e07 intel/dev: setup 1024 GS urb entries for ADL-N 
v2: apply only for devices with less than 32 EUs (Lionel)

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7942
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20414>
 2022-12-23 09:51:01 +00:00
Jianxun Zhang
6e33423a6f intel/dev: Enable AUX map on MTL 
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20322>
 2022-12-15 11:43:00 -08:00
Paulo Zanoni
a099d6ae4d intel: add devinfo->has_64bit_float_via_math_pipe 
Unusual hardware features that require special hanlding usually get a
devinfo field, so do this for MTL's unordered DF types. This will
guarantee that any platform based on MTL (thus inheriting from
MTL_FEATURES) will automatically be handled in these special cases.

v2: s/has_unordered_64bit_float/has_64bit_float_via_math_pipe/ (Curro).

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20072>
 2022-12-10 03:59:19 +00:00
Nanley Chery
822687f4c0 intel/dev: Add a has_illegal_ccs_values flag 
Whether or not CCS can be used without initialization depends on the
platform:

- On gfx7-8, each CCS element is 1-bit and encodes "fast-cleared" or
  "pass-through". So, those platforms have no illegal values.

- On gfx9-11, each CCS element is 2-bits and some bit combinations
  are invalid.

- On gfx12+, each CCS element is 4-bits but they have no truly illegal
  values. Unused encodings are interpreted as "pass-through".

Refer to the "MCS/CCS Buffers for Render Target(s)" sections of the
PRMs for more info.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20118>
 2022-12-06 00:49:17 +00:00
Jordan Justen
686ada78cd intel/dev: Add (disabled) device info for MTL 
Reworks:
 * Jordan: INTEL_PLATFORM_MTL_M/INTEL_PLATFORM_MTL_P
 * Lionel: .has_coarse_pixel_primitive_and_cb
 * Jordan: .has_mesh_shading & .has_ray_tracing
 * Paulo: .has_64bit_float
 * José: .has_integer_dword_mul (BSpec: 47431)
 * Jordan: Comment pci device ids for now similar to DG2:
   * 70a4e64685 ("intel: Add *disabled* device ids for DG2")
   * ad565f6b70 ("intel/dev: Enable first set of DG2 PCI IDs")

Ref: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/drm/i915_pciids.h?h=v6.0-rc4#n736
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19658>
 2022-12-01 16:22:47 +00:00
Jianxun Zhang
93baad8047 intel/dev: Set 'has_flat_ccs' flag for DG2 
The code paths of flat ccs should be working on DG2 because
they are routed by other conditions like GFXVer so far. But
using this flag is the intended way, and we need to have
this change prior to updating these conditions with the flag.

Ref: 5262475242 ("intel/dev: Add a has_flat_ccs flag")

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20043>
 2022-11-29 02:47:44 +00:00
Jordan Justen
ed84f163ff intel/dev: Add devinfo::has_caching_uapi (and disable for dg1 and dg2+) 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19911>
 2022-11-28 21:54:20 +00:00
José Roberto de Souza
29550bc50a intel: Add has_context_isolation to intel_device_info 
Iris, hasvk and anv were fetching the same information, better do it
on one place.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19425>
 2022-11-07 17:22:14 +00:00
José Roberto de Souza
d5d1331381 intel: Add has_userptr_probe to intel_device_info 
Iris, hasvk and anv were fetching the same information, better do it
on one place.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19425>
 2022-11-07 17:22:14 +00:00
José Roberto de Souza
e9eceb1106 intel: Add has_mmap_offset to intel_device_info 
All 4 drivers were fetching the same information, better do it on one
place.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19425>
 2022-11-07 17:22:14 +00:00
Jordan Justen
d911eb17d8 intel/dev: Set has_lsc in XEHP_FEATURES rather than DG2_FEATURES 
MTL will want this set as well.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19447>
 2022-11-02 20:00:08 +00:00