AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
168,506 Commits 1 Branch 0 Tags
415b824bc6dc8f0fce517f8fa1e38df94de15502
Commit Graph

168506 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Lionel Landwerlin aa18d52728 anv: make sure mi_memcpy lands before push constant loads 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e2dc32d755 ("anv: move functions around to plan for generated draws")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin e68615aeaa anv: fix indirect draws VF cache tracking of index buffer 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e2dc32d755 ("anv: move functions around to plan for generated draws")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin 1454b789b1 anv: fix 3DSTATE_PS emission in generation shaders 
We have to use the helper and also were missing the vector mask
programming.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c950fe97a0 ("anv: implement generated (indexed) indirect draws")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin 8f16ca8741 anv: remove commented code 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c950fe97a0 ("anv: implement generated (indexed) indirect draws")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin f5dc88910f anv: remove pre hasvk split assert 
With softpin we should not always expect a BO in addresses.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin ae398284c9 anv: limit push constant dirtyness with generation shaders 
We only use the fragment shader push constants.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c950fe97a0 ("anv: implement generated (indexed) indirect draws")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin 2ea106e758 anv: correctly program 3DSTATE_SF in generation shaders 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c950fe97a0 ("anv: implement generated (indexed) indirect draws")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin e698040061 anv: remove BTI related flush in generation shaders 
Earlier versions of the generation shaders were using the binding
table. We since switch to A64 messages. So the flush can be removed.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c950fe97a0 ("anv: implement generated (indexed) indirect draws")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin 1dcb536acd anv: remove copied code from generation shader 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c950fe97a0 ("anv: implement generated (indexed) indirect draws")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin 63fa6d9f49 anv: fix generated forward jump with more than 67M draws 
The issue here is that for draw indirect count variants, we want to
jump after the last generated draw call to the next location where
commands are. But if we have more than 67M draws (8k * 8k chunks), we
only know the location once we've generated each of the 8k * 8k
chunks.

This change adds a CPU side pointer in the push constant struct so
that we can create a single linked list of chunks to edit and go
through to write the correct jump address after all the generated
space has been allocated.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c950fe97a0 ("anv: implement generated (indexed) indirect draws")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin c1c680c08b anv: correctly reset generation address on command buffer reset 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin 4246a519f3 anv: fix incorrect parameter 
cmd_buffer_update_dirty_vbs_for_gfx8_vb_flush takes a value RANDOM/SEQUENTIAL. Not a boolean.
Fortunately this worked okay because true == RANDOM

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin 234505f013 util/glsl2spirv: add support for include directive 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Eric Engestrom eae5aa943a panfrost/ci: add EGL tests 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21504>
 2023-03-03 10:14:29 +00:00
Lionel Landwerlin 6ee7a2ecfa anv: pull Wa_14016118574 out of some loop not changing state 
The WA is meant to be here to apply some state that is not propagated
properly inside the HW. But if you have a loop like :

for ( ... ) {
  emit(3DPRIMITIVE, some param);
}

You're not really changing any state, just push more draws into the
pipeline.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: f2645229c2 ("anv: implement Wa_14016118574")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21660>
 2023-03-03 09:34:16 +00:00
Lionel Landwerlin d82e8e01c8 anv: fixup condition for Wa_14016118574 
We don't want the WA to kick-in if it's not point/line topology.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: f2645229c2 ("anv: implement Wa_14016118574")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21660>
 2023-03-03 09:34:16 +00:00
Samuel Pitoiset 3e4541bb56 radv/ci: adjust timeouts for Vega10 and Renoir 
With latest CTS it takes much more time.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21390>
 2023-03-03 08:23:22 +00:00
Samuel Pitoiset f775873f81 ci: uprev CTS to 1.3.5.0 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21390>
 2023-03-03 08:23:21 +00:00
Samuel Pitoiset 3b9937c85e radv: stop allocationg the attr ring BO for compute queues on GFX11 
Only needed for graphics. This saves ~8Mib of 32-bit VRAM per compute
queue.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21632>
 2023-03-03 07:27:21 +00:00
José Roberto de Souza 23f8b5b7a2 iris: Add initial skeleton of kmd backend 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21369>
 2023-03-03 05:57:05 +00:00
José Roberto de Souza cebffb404f iris: Use DRM_IOCTL_I915_GEM_CREATE_EXT in all supported kernels 
As we start to refactor the iris code base to support Xe KMD here I'm
dropping DRM_IOCTL_I915_GEM_CREATE usage as much as possible and
unifying all graphics memory allocation calls to
DRM_IOCTL_I915_GEM_CREATE_EXT.

The kernel version that implemented DRM_I915_QUERY_MEMORY_REGIONS uAPI
also implemented DRM_IOCTL_I915_GEM_CREATE_EXT so we can use that
to safely call DRM_IOCTL_I915_GEM_CREATE_EXT.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21369>
 2023-03-03 05:57:05 +00:00
José Roberto de Souza 65d129ec15 iris/bufmgr: Add i915_gem_set_domain() 
Avoids code duplication.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21369>
 2023-03-03 05:57:05 +00:00
José Roberto de Souza d6754c1e04 iris: Convert drm_i915_gem_memory_class_instance to intel_memory_class_instance 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21369>
 2023-03-03 05:57:05 +00:00
José Roberto de Souza a24d93aa89 intel/dev: Query and compute hardware topology for Xe 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21368>
 2023-03-03 05:25:35 +00:00
José Roberto de Souza 4b81a80f55 intel/dev: Implement Xe functions to handle hwconfig 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21368>
 2023-03-03 05:25:35 +00:00
José Roberto de Souza bc24091c52 intel/dev: Implement Xe functions to fill intel_device_info 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21368>
 2023-03-03 05:25:35 +00:00
José Roberto de Souza 545d7e07ca intel/dev: Add INTEL_KMD_TYPE_XE 
As mentioned in the previous patch, if intel-xe-kmd is disabled
it will fail to detected in run time but it will still compile all
Xe files.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21368>
 2023-03-03 05:25:35 +00:00
José Roberto de Souza 7d34ec4691 intel: Add Meson parameter to enable Xe KMD support 
The plan is to compile all the Xe files but in run time it will fail
to detect the KMD loaded and it will fall back to software
rendering(if build).

Compiling Xe files makes sure newer commits don't break Xe even if
developers don't have Xe enabled in their build folder.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21368>
 2023-03-03 05:25:35 +00:00
José Roberto de Souza ee510e2c50 intel: Pull in xe_drm.h 
This is the uapi of the new Xe kernel driver.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21368>
 2023-03-03 05:25:35 +00:00
Mark Janes 276f4a9d8c intel/dev: Print required workarounds with intel_dev_info 
With the addition of workarounds, the output from this tool is more
verbose than some users will want.  Provide optional parameters for
enabling hwconfig and workaround details.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21639>
 2023-03-03 04:55:08 +00:00
Hans-Kristian Arntzen b7926303e6 radv: Expose VK_EXT_swapchain_maintenance1. 
Passes dEQP-VK.wsi.*.maintenance1.*.

Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20235>
 2023-03-03 03:59:13 +00:00
Hans-Kristian Arntzen 3d0258c679 wsi/win32: Implement VK_EXT_swapchain_maintenance1. 
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Jesse Natalie <jenatalie@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20235>
 2023-03-03 03:59:13 +00:00
Hans-Kristian Arntzen 1b047ceac2 wsi/display: Implement EXT_swapchain_maintenance1. 
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20235>
 2023-03-03 03:59:13 +00:00
Hans-Kristian Arntzen 07ac177c3f wsi/wayland: Implement EXT_swapchain_maintenance1. 
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20235>
 2023-03-03 03:59:13 +00:00
Hans-Kristian Arntzen ad71d584cf wsi/common: Add function to modify present mode. 
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20235>
 2023-03-03 03:59:13 +00:00
Hans-Kristian Arntzen d79fa8a03a wsi/common: Add comment about DEFERRED_ALLOCATION_BIT_EXT. 
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20235>
 2023-03-03 03:59:13 +00:00
Hans-Kristian Arntzen ae920c8420 wsi/common: Implement swapchain present fence. 
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20235>
 2023-03-03 03:59:13 +00:00
Hans-Kristian Arntzen be0dcbdfa2 wsi/x11: Implement EXT_swapchain_maintenance1. 
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20235>
 2023-03-03 03:59:13 +00:00
Hans-Kristian Arntzen 8ece1ade5b wsi/common: Add common implementation of vkReleaseSwapchainImagesEXT. 
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20235>
 2023-03-03 03:59:13 +00:00
Marek Olšák c1fa7fe785 lavapipe/ci: add a new flake 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19399>
 2023-03-03 03:27:40 +00:00
Marek Olšák 4f7e353237 amd: lower multi-component subdword SSBO loads in NIR 
because the hw and LLVM only support subdword single-component SSBO loads,
and ac_nir_to_llvm splits multi-component loads because of that, which is
inefficient.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19399>
 2023-03-03 03:27:40 +00:00
Marek Olšák 82919e2dcb amd: lower subdword UBO loads in NIR 
This fixes broken subdword UBO loads with LLVM.

It's only needed for LLVM, but it's done for both LLVM and ACO because
the pass can be fully validated only with ACO and the Vulkan CTS right now.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19399>
 2023-03-03 03:27:40 +00:00
Marek Olšák 1a424fee4a ac/llvm: implement nir_op_unpack_32_4x8 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19399>
 2023-03-03 03:27:40 +00:00
Marek Olšák 6aee999131 aco: implement nir_op_unpack_32_4x8 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19399>
 2023-03-03 03:27:40 +00:00
Marek Olšák 09005e6dfc ac/nir: add ac_nir_lower_subdword_loads to lower 8/16-bit loads to 32 bits 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19399>
 2023-03-03 03:27:40 +00:00
Marek Olšák b80bd58265 nir: skip nir_op_unpack_32_4x8 in nir_lower_alu_width 
The pass can't handle it just like the other unpack opcodes and generates
invalid NIR.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19399>
 2023-03-03 03:27:40 +00:00
Marek Olšák ec38758e86 nir: return progress from nir_lower_io_to_scalar 
oversight?

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19399>
 2023-03-03 03:27:40 +00:00
Faith Ekstrand 9a4641cf6b intel/nir: Limit unaligned loads to vec4 
This probably doesn't affect Vulkan or GL because they can't have
anything bigger than a vec4 anyway unless it's a u64vec4 and those have
to be at least 8B aligned.  This may affect CL apps if they use
__attribute__((packed)) on something with big vectors, depending on how
LLVM decides to translate that.

Fixes: f8aa83f0c8 ("intel/nir: Use nir_lower_mem_access_bit_sizes()")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21524>
 2023-03-03 02:00:39 +00:00
Faith Ekstrand c11ac5e446 nir: Handle wider unaligned loads in lower_mem_access_bit_size 
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21524>
 2023-03-03 02:00:39 +00:00
Faith Ekstrand 7e8a10be67 nir: Make chunk_align_offset const in lower_mem_load() 
This should make things more clear than changing the value from earlier
in the loop.  Also, rename chunk_offset to load_offset so they match.

Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21524>
 2023-03-03 02:00:39 +00:00