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Author SHA1 Message Date
Tapani Pälli 889c3ee6b8 anv: fix sends_count_expectation assert on simd32 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21758>
 2023-03-07 14:37:31 +00:00
Yogesh Mohan Marimuthu 347a5b79f9 ac/surface: only adjust pitch if surf_pitch was modified 
Modifying pitch for all LINEAR surface isn't correct;
the original change that modified surf_pitch was only
intended for YUV textures.

This fixes vkGetImageSubresourceLayout rowPitch return value
for VK_FORMAT_BC3_UNORM_BLOCK + VK_IMAGE_TILING_LINEAR.

Fixes: fcc499d5 (ac/surface: adjust gfx9.pitch[*] based on surf->blk_w)

v2: add check for UYVY format (Pierre-Eric)
v3: move blk_w division to above if check (Pierre-Eric)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21595>
 2023-03-07 13:50:31 +00:00
David Heidelberg f72774f13f ci/lavapipe: fixes typo 
Fixes: 5ee724e180 ("ci/lavapipe: add recent occasional flake")

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21759>
 2023-03-07 13:26:52 +00:00
Georg Lehmann de4805f25f aco: use bitfield array helpers for valu modifiers 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>
 2023-03-07 11:53:23 +00:00
Georg Lehmann e7559da757 aco: add bitfield array helper classes 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>
 2023-03-07 11:53:23 +00:00
Georg Lehmann 097a97cc42 aco: remove VOP[123C]P? structs 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>
 2023-03-07 11:53:23 +00:00
Georg Lehmann 08542318e7 aco/optimizer: simplify using VALU instruction 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>
 2023-03-07 11:53:23 +00:00
Georg Lehmann 4591703e79 aco/print_ir: simplify using VALU instruction 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>
 2023-03-07 11:53:23 +00:00
Georg Lehmann 17ff2e8c52 aco: validate VALU modifiers 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>
 2023-03-07 11:53:23 +00:00
Georg Lehmann fc193ab4db aco/ra: set opsel_hi to zero when converting to VOP2 
Otherwise the new modifier validation will fail.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>
 2023-03-07 11:53:23 +00:00
Georg Lehmann 366cf4efaa aco/ir: rework IR to have one common valu instruction struct 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>
 2023-03-07 11:53:23 +00:00
Georg Lehmann 77afe7d960 aco: treat VINTERP_INREG as VALU 
It's just v_fma with fixed DPP8 and builtin s_waitcnt_expcnt, so it can mostly
be handled as a pure VALU instruction.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>
 2023-03-07 11:53:23 +00:00
Samuel Pitoiset c119b19f98 radv: fix incorrect stride for primitives generated query with GDS 
When the query pool uses GDS (for NGG), the stride is 40.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8412
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21650>
 2023-03-07 10:15:35 +01:00
Lionel Landwerlin a278eeb719 nir: fix nir_ishl_imm 
Both GLSL & SPIRV have undefined values for shift > bitsize. But SM5
says :

   "This instruction performs a component-wise shift of each 32-bit
    value in src0 left by an unsigned integer bit count provided by
    the LSB 5 bits (0-31 range) in src1, inserting 0."

Better to not hard code the wrong behavior in NIR.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e227bb9fd5 ("nir/builder: add ishl_imm helper")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@colllabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21720>
 2023-03-07 08:14:34 +00:00
Samuel Pitoiset 5ec80ab37c radv: do not add descriptor BOs on update when the global BO list is used 
It's unnecessary and already checked elsewhere like in
vkCmdBindDescriptorSets(). This improves performance of vkoverhead
test #76 (descriptor_1image) by +18%. It's the same performance as
PRO on my Threadripper 1950X now. This should also slightly improve
texel and buffer descriptors.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20699>
 2023-03-07 07:30:29 +00:00
Karol Herbst 1aca36815e gallivm: fix lp_vec_add_offset_ptr for 32 bit builds 
The function assumed ptrs are always 64 bit sized.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8267
Fixes: 442d1fe5ad ("gallivm: use masked intrinsics for global and scratch access.")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21604>
 2023-03-07 04:17:15 +00:00
Karol Herbst 4c24ff0a34 rusticl/kernel: Images arg sizes also have to match the host pointer size 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8267
Fixes: b0d698c532 ("rusticl: correctly check global argument size")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21604>
 2023-03-07 04:17:15 +00:00
Alyssa Rosenzweig 66f806d01d agx: Assert that memory index is 32-bit reg 
Semantics will be wrong otherwise (reading garbage).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>
 2023-03-07 02:58:35 +00:00
Alyssa Rosenzweig 2a174f0019 agx/lower_address: Handle 16-bit offsets 
These need to be upconverted for correctness.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>
 2023-03-07 02:58:35 +00:00
Alyssa Rosenzweig 9f5a4a9604 agx/lower_address: Fix handling of 64-bit immediates 
We can't add a 64-bit immediate with the hardware iadd, that won't work. What we
can do is add a 32-bit immediate, derived as the low 32-bits of a 64-bit
nir_ssa_def.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>
 2023-03-07 02:58:35 +00:00
Alyssa Rosenzweig 4bd0e1d097 agx/lower_address: Handle 8-bit load/store 
Should work ok with the implicit up-conversion that the backend does.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>
 2023-03-07 02:58:35 +00:00
Alyssa Rosenzweig 5865e23a07 agx/lower_address: Handle large shifts 
If we manage to fold in a left shift that's bigger than the hardware can do, we
should at least avoid generating a useless right shift to feed the hardware
rather bailing completely.

For motivation, this form of address arithmetic is encountered when indexing
into arrays with large power-of-two element sizes (array-of-structs).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>
 2023-03-07 02:58:35 +00:00
Alyssa Rosenzweig 6203503196 agx/lower_address: Optimize "shift + constant" 
Optimize address arithmetic of the form

   base + u2u64((index << shift) + const)

into hardware operands

   base, index << (shift - format_shift) + const'

which (if format_shift = shift) can be simply

   base, index + const'

rather than the current naive translation

   base, ((index << shift) + const) >> format_shift

This saves at least one pointless shift. We can't do this optimization with
nir_opt_algebraic, because explicitly optimizing "(a << #b) >> #b" to "a" isn't
sound due to overflow. But there's no overflow issue here, which is what this
whole pass is designed around.

For motivation, this address arithmetic implements "dynamically indexing into an
array inside of a C structure", where the const is the offset of the array
relative to the structure.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>
 2023-03-07 02:58:35 +00:00
Alyssa Rosenzweig dccf6f569b agx/lower_address: Break on match 
Once we've matched a summand, commit to it. This avoids needlessly checking the
second source if the first matched, and removes some indentation/funny control
flow.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>
 2023-03-07 02:58:35 +00:00
Sergi Blanch Torne 36f6eb88cb Revert "ci: disable Collabora's LAVA lab for maintance" 
This reverts commit https://gitlab.freedesktop.org/mesa/mesa/-/commit/6be7469df1e12bd57c697ff7e34bbda8286d67a2

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21356>
 2023-03-07 02:23:00 +00:00
Mike Blumenkrantz b5fc941f2f zink: always set batch usage for descriptors after barrier 
this otherwise breaks unordered promotion calc

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>
 2023-03-07 01:57:41 +00:00
Mike Blumenkrantz afb56bad1c zink: set dynamic pcp for unordered cmdbuf 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>
 2023-03-07 01:57:41 +00:00
Mike Blumenkrantz c5f901dbc6 zink: bind descriptor buffers to unordered cmdbuf 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>
 2023-03-07 01:57:41 +00:00
Mike Blumenkrantz 20c9cfb30f zink: always set color writes on the unordered cmdbuf 
this state has to be set, so ensure it is

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>
 2023-03-07 01:57:41 +00:00
Mike Blumenkrantz 8e3ee9aad6 zink: explicitly flush src clears when u_blittering 
this otherwise relies on set_framebuffer_state flushing them,
which may or may not be accurate/desired

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>
 2023-03-07 01:57:41 +00:00
Mike Blumenkrantz 1aa62912b7 zink: don't unset existing access when adding resource binds 
this breaks barrier calcs, but it was fine since there was a pre-barrier

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>
 2023-03-07 01:57:41 +00:00
Mike Blumenkrantz a0f3d171f6 zink: eliminate pre barrier for adding resource binds 
this will automatically be handled by the copies below

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>
 2023-03-07 01:57:41 +00:00
Mike Blumenkrantz d133f95084 zink: check for layout updates when unbinding samplerviews 
not sure if it's a bug, but it should be consistent with shader image
unbinding, so here it is

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>
 2023-03-07 01:57:41 +00:00
Mike Blumenkrantz a4b1ae1f03 zink: propagate valid_buffer_range when replacing buffer storage 
this is otherwise unreliable

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>
 2023-03-07 01:57:41 +00:00
Mike Blumenkrantz 7145ccfa05 zink: fix descriptor update flagging on null ssbo set 
this could unset the update flag if the last ssbo was null, which would
be a bug if it could ever be triggered

found by inspection

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>
 2023-03-07 01:57:41 +00:00
Mike Blumenkrantz e0dfe058c4 zink: only add deferred barrier on fb unbind when layout needs to change 
this otherwise may have been a surface that was never drawn to or
already had its layout corrected, in which case a deferred barrier
is not only unnecessary, it might be broken

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>
 2023-03-07 01:57:41 +00:00
Mark Janes bc04e2daca intel/fs: use generated helpers for Wa_1209978020 / Wa_18012201914 
Wa_1209978020 is a clone of Wa_18012201914.  Update references to
refer to the originating bug, and use generated helpers to ensure it
is applied to future platforms as needed.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21741>
 2023-03-07 01:41:53 +00:00
Caio Oliveira c92d589597 intel/compiler: Drop non-scoped barrier handling 
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21634>
 2023-03-07 00:41:13 +00:00
Alyssa Rosenzweig 02eef8ca98 gallivm: Drop non-scoped barrier handling 
Now unreachable.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21634>
 2023-03-07 00:41:13 +00:00
Alyssa Rosenzweig c8147e69d3 ir3: Drop non-scoped barrier handling 
Now unreachable.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21634>
 2023-03-07 00:41:13 +00:00
Alyssa Rosenzweig fc93e8e537 pan/mdg: Drop control_barrier handling 
Now unreachable.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21634>
 2023-03-07 00:41:13 +00:00
Alyssa Rosenzweig cb0f4b8146 pan/bi: Drop control_barrier handling 
Now unreachable.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21634>
 2023-03-07 00:41:13 +00:00
Alyssa Rosenzweig f47ea3f992 glsl/nir: Use scoped_barrier for control barrier 
Rather than control_barrier. This avoids the need to handle control_barrier at
all for backends that set use_scoped_barrier. This effectively matches what
spirv_to_nir emits, so Vulkan-capable compilers should be ok.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21634>
 2023-03-07 00:41:13 +00:00
Caio Oliveira 07de034791 intel/compiler: Drop brw_nir_lower_scoped_barriers 
Now that we handle scoped barriers with execution scope during
NIR -> Backend IR translation, this lowering is not needed anymore.

Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21634>
 2023-03-07 00:41:13 +00:00
Caio Oliveira dfc34b1a65 intel/vec4: Handle scoped barriers with execution scope 
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21634>
 2023-03-07 00:41:13 +00:00
Caio Oliveira db0a09c9e2 intel/fs: Handle scoped barriers with execution scope 
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21634>
 2023-03-07 00:41:13 +00:00
Yiwei Zhang ae6eb3229e venus: revert back the warn order 
This reverts
- commit 4ae4e4362c
- commit f54aa49c14

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21542>
 2023-03-07 00:25:07 +00:00
Yiwei Zhang 28bdf8db18 venus: vn_relax to abort on ring fatal status upon warn order 
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21542>
 2023-03-07 00:25:07 +00:00
Yiwei Zhang adb51eeba5 venus: propagate vn_ring to vn_relax 
This is to prepare for vn_relax to check ring status as well as pinging
renderer.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21542>
 2023-03-07 00:25:07 +00:00
Yiwei Zhang 15a55198ec venus: abort ring submit when ring is in fatal status 
This change also migrates to use the protocol defined status enums.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21542>
 2023-03-07 00:25:07 +00:00