Commit Graph

58335 Commits

Author SHA1 Message Date
Ilia Mirkin
3fa384db0c mesa/program: add new derivative unops to the unexpected list
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-14 20:25:32 -04:00
Ilia Mirkin
f80c6847e9 glsl: add ARB_derivative control support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-08-14 20:25:32 -04:00
Ilia Mirkin
4a9c36c985 mesa: add ARB_derivative_control extension bit
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-14 20:25:32 -04:00
Ilia Mirkin
e474cb4027 mesa: add ARB_texture_barrier support
This extension is identical to NV_texture_barrier. Alias
glTextureBarrier to the existing glTextureBarrierNV and use the existing
NV_texture_barrier extension bit.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-08-14 20:25:32 -04:00
Glenn Kennard
f23ee74791 r600g: Implement BPTC texture support
Requires Evergreen/Cayman

Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2014-08-15 01:55:13 +02:00
Kristian Høgsberg
221d9c3e9c i965: Rename intelValidateState to intel_update_state
This matches the name of the dd hook.  Also convert a couple of nearby
dd implementations to lowercase + underscore as is now the standard.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-14 13:57:26 -07:00
Kristian Høgsberg
416dd873e8 i965: Assign PS kernel start pointers when we decide which kernels to use
Right now we decide which kernels to use and the GRF start offsets in
one place and emit the kernel pointers later.  The logic of how to map
8, 16 and 32 kernels to kernel start pointers follows the same logic as which
GRF start offsets to use, so lets figure out these two things in one place.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2014-08-14 13:57:26 -07:00
Grigori Goronzy
d7d8260f70 radeonsi: implement BPTC texture support
Passes all piglit tests.

v2: rebased

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2014-08-14 20:45:03 +02:00
Marek Olšák
87a8ed9389 radeonsi: fix buffer invalidation of unbound texture buffer objects
This maintains a list of all TBOs in a pipe_context.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-14 20:45:03 +02:00
Marek Olšák
79f28cdb98 r600g: implement invalidation of texture buffer objects
This fixes piglit spec/ARB_texture_buffer_object/data-sync.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-14 20:45:03 +02:00
Marek Olšák
da9c3ed304 r600g: fix constant buffer fetches
Somebody forgot to do this. It was uncovered by recent st/mesa changes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82139

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Andreas Boll <andreas.boll.dev@gmail.com>
2014-08-14 20:45:03 +02:00
Marek Olšák
d52202141e r600g: clear constant buffer sizes at the beginning of CS
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-14 20:45:03 +02:00
Pekka Paalanen
08264e5dad egl_dri2: fix EXT_image_dma_buf_import fds
The EGL_EXT_image_dma_buf_import specification was revised (according to
its revision history) on Dec 5th, 2013, for EGL to not take ownership of
the file descriptors.

Do not close the file descriptors passed in to eglCreateImageKHR with
EGL_LINUX_DMA_BUF_EXT target.

It is assumed, that the drivers, which ultimately process the file
descriptors, do not close or modify them in any way either. This avoids
the need to dup(), as it seems we would only need to just close the
dup'd file descriptors right after.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76188
Signed-off-by: Pekka Paalanen <pekka.paalanen@collabora.co.uk>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-14 21:30:57 +03:00
Pekka Paalanen
972e87ca30 i965: fix compiler error in union initiliazer
gcc 4.6.3 chokes with the following error:

brw_vec4.cpp: In member function 'int brw::vec4_visitor::setup_uniforms(int)':
brw_vec4.cpp:1496:37: error: expected primary-expression before '.' token

Apparently C++ does not do named initializers for unions, except maybe
as a gcc extension, which is not present here.

As .f is the first element of the union, just drop it. Fixes the build
error.

Signed-off-by: Pekka Paalanen <pekka.paalanen@collabora.co.uk>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-14 21:30:57 +03:00
Anuj Phogat
9b9dd22f44 i965: Bail on FS copy propagation for scratch writes with source modifiers
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-14 11:03:00 -07:00
Anuj Phogat
7c1ea00eaf i965: Bail on vec4 copy propagation for scratch writes with source modifiers
Fixes Khronos GLES3 CTS test:
dynamic_expression_array_access_vertex

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-14 11:03:00 -07:00
Aras Pranckevicius
2b837576eb glsl: Fixed vectorize pass vs. texture lookups.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82574
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-14 09:40:33 -07:00
Brian Paul
088106fa79 ra: move declarations before code to fix MSVC build
Trivial.
2014-08-14 08:53:45 -06:00
Brian Paul
bfb6b76665 svga: remove some unneeded INLINE qualifiers
Trivial.
2014-08-14 08:53:45 -06:00
Neil Roberts
2c50212b14 i965: Store uniform constant values in a gl_constant_value instead of float
The brw_stage_prog_data struct previously contained an array of float pointers
to the values of parameters. These were then copied into a batch buffer to
upload the values using a regular assignment. However the float values were
also being overloaded to store integer values for integer uniforms. This can
break if x87 floating-point registers are used to do the assignment because
the fst instruction tries to fix up invalid float values. If an integer
constant happened to look like an invalid float value then it would get
altered when it was copied into the batch buffer.

This patch changes the pointers to be gl_constant_value instead so that the
assignment should end up copying without any alteration. This also makes it
more obvious that the values being stored here are overloaded for multiple
types.

There are some static asserts where the values are uploaded to ensure that the
size of gl_constant_value is the same as a float.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81150
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-14 11:54:48 +01:00
Christian König
6fb42ee7a6 st/vdpau: add device reference counting
This fixes an issue with flash where it tries to destroy a decoder
after already destroying the device associated with the decoder.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=82517

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-08-14 11:57:07 +02:00
Chris Forbes
c1df492d03 mesa: Make ARB_gpu_shader5 core-profile-only
Requires GLSL 1.50 or higher, which we only support in the core profile.

V2: Fix broken alignment

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-14 21:32:33 +12:00
Ilia Mirkin
a89353381a nouveau: force luminance clear colors to have the same g/b values as r
Fixes the LUMINANCE_ALPHA formats of fbo-clear-formats piglit test.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-08-14 02:05:06 -04:00
Kenneth Graunke
c66d928f2c i965: Enable INTDIV in SIMD16 mode.
All we need to do is decompose this to two SIMD8 instructions, like we
do in many other cases.  We even already have code for that.

I apparently just botched this last time I tried, and it was easy.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-13 21:19:07 -07:00
Kenneth Graunke
24878f31c4 i965/fs: Drop "do dual source blending" generator parameter.
When dual source blending, the visitor already stores a flag in
brw_wm_prog_data (dual_src_blend) for the state upload code to use.
The generator also receives this, so there's no need to pass an
additional flag.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-13 21:19:07 -07:00
Jason Ekstrand
a8379a405a mesa/texstore: Don't use the _mesa_swizzle_and_convert if we need transfer ops
The _mesa_swizzle_and_convert path can't do transfer ops, so we should bail
if they're needed.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-08-13 19:43:33 -07:00
Dave Airlie
1cfcd0164e hud: don't overrun malloced arrays
==17630== Invalid read of size 4
==17630==    at 0x400AE10: memcpy (in /usr/lib/valgrind/vgpreload_memcheck-x86-linux.so)
==17630==    by 0x49024A2: u_upload_data (u_upload_mgr.c:253)
==17630==    by 0x49050E1: u_vbuf_draw_vbo (u_vbuf.c:980)
==17630==    by 0x487DE29: cso_draw_vbo (cso_context.c:1425)
==17630==    by 0x487DEA0: cso_draw_arrays (cso_context.c:1445)
==17630==    by 0x48A3B0E: hud_draw_colored_prims.constprop.6 (hud_context.c:123)
==17630==    by 0x48A4810: hud_draw (hud_context.c:266)
==17630==    by 0x48763F7: dri_flush (dri_drawable.c:483)
==17630==    by 0x4057510: dri2Flush.constprop.4 (dri2_glx.c:559)
==17630==    by 0x405789E: dri2SwapBuffers (dri2_glx.c:851)
==17630==    by 0x402C531: glXSwapBuffers (glxcmds.c:842)
==17630==    by 0x8049716: ??? (in /usr/bin/glxgears)
==17630==  Address 0x4426b2c is 4 bytes after a block of size 1,008 alloc'd
==17630==    at 0x4006B11: malloc (in /usr/lib/valgrind/vgpreload_memcheck-x86-linux.so)
==17630==    by 0x48A4CE7: hud_pane_add_graph (hud_context.c:625)
==17630==    by 0x48A68F0: hud_pipe_query_install (hud_driver_query.c:175)
==17630==    by 0x48A6A30: hud_driver_query_install (hud_driver_query.c:207)
==17630==    by 0x48A5835: hud_create (hud_context.c:791)
==17630==    by 0x48756CB: dri_create_context (dri_context.c:165)
==17630==    by 0x4871CD4: driCreateContextAttribs (dri_util.c:435)
==17630==    by 0x4871E06: driCreateNewContext (dri_util.c:464)
==17630==    by 0x4056A22: dri2_create_context (dri2_glx.c:223)
==17630==    by 0x402CF68: CreateContext (glxcmds.c:299)
==17630==    by 0x402D265: glXCreateContext (glxcmds.c:430)
==17630==    by 0x804B136: ??? (in /usr/bin/glxgears)

This is due to second vertex element being specified, and the upload
tries to fetch over the end. However the pane rendering only requires
a single vertex element, so specify only one.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-08-14 10:46:32 +10:00
Roland Scheidegger
b6d29de2c4 mesa: fix texstore with GL_COLOR_INDEX data
This got broken by 3dbf5bf657.
GL_COLOR_INDEX data is still supported (in legacy contexts), but the new
texstore_swizzle path cannot handle it (and didn't detect this).
Unfortunately there's no piglit test trying to specify textures with a
GL_COLOR_INDEX source format, and I don't really understand how all the color
map stuff which is used by this works, but this caused conform failures
(with a reported mesa implementation error when trying to figure out the color
mapping).

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-08-14 02:16:23 +02:00
Andreas Boll
64c379a3a8 winsys/radeon: fix hawaii accel_working2 comment
accel_working2 returns 3 if the new firmware is used.

The comment wasn't updated in v3 of commit:
36771dc winsys/radeon: fix nop packet padding for hawaii

Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-13 23:28:23 +02:00
Tom Stellard
866dae85c8 r300g: Fix bug in build_loop_info()/compiler v2
Fixes piglit glean "do-loop with continue and break" on RS690

It's based on Tom Stellard patch and improved to handle CMP instruction.

[v2] handle CMP instruction

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: David Heidelberger <david.heidelberger@ixit.cz>
2014-08-13 14:37:03 -04:00
Tom Stellard
ed3f7eadad clover: Flush the command queue in clReleaseCommandQueue()
This is required by the spec.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

CC: "10.2" <mesa-stable@lists.freedesktop.org>
2014-08-13 14:20:22 -04:00
Tom Stellard
a15088338e radeonsi/compute: Stop leaking the input buffer
We were leaking the input buffer used for kernel arguments and since
we were allocating it using si_upload_const_buffer() we were leaking
1 MB per kernel invocation.

CC: "10.2" <mesa-stable@lists.freedesktop.org>
2014-08-13 14:18:35 -04:00
Tom Stellard
38fccc37c1 radeonsi/compute: Whitespace fixes
CC: "10.2" <mesa-stable@lists.freedesktop.org>
2014-08-13 14:17:02 -04:00
Tom Stellard
1e2e550671 radeonsi/compute: Call si_pm4_free_state() after emitting compute state
This will decrement the reference count for buffers referenced in the
command stream will prevent us from leaking them.

CC: "10.2" <mesa-stable@lists.freedesktop.org>
2014-08-13 14:17:02 -04:00
Tom Stellard
05e9681d55 radeonsi/compute: Update reference counts for buffers in si_set_global_binding()
CC: "10.2" <mesa-stable@lists.freedesktop.org>
2014-08-13 14:17:02 -04:00
Tom Stellard
72969e0efb radeon/compute: Report a value for PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
CC: "10.2" <mesa-stable@lists.freedesktop.org>
2014-08-13 14:11:44 -04:00
Tom Stellard
77ea58ca81 radeon/compute: Fix reported values for MAX_GLOBAL_SIZE and MAX_MEM_ALLOC_SIZE
There is a hard limit in older kernels of 256 MB for buffer allocations,
so report this value as MAX_MEM_ALLOC_SIZE and adjust MAX_GLOBAL_SIZE
to statisfy requirements of OpenCL.

CC: "10.2" <mesa-stable@lists.freedesktop.org>
2014-08-13 14:11:43 -04:00
Connor Abbott
e78a01d5e6 ra: optimistically color only one node at a time
Before, when we encountered a situation where we had to optimistically
color a node, we would immediately give up and push all the remaining
nodes on the stack in the order of their index - which is a random, and
potentially not optimal, order. Instead, choose one node to
optimistically color in ra_select(), and then once we've optimistically
colored it, keep on going as normal in the hopes that we've opened up
more avenues for the normal select phase to make progress. In cases with
high register pressure, this helps make the order we push things on the
stack much better, and therefore increase the chance that we can allocate
successfully.

total instructions in shared programs: 4545447 -> 4545401 (-0.00%)
instructions in affected programs:     1353 -> 1307 (-3.40%)
GAINED:                                124
LOST:                                  6

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-08-13 11:43:37 -07:00
Connor Abbott
03f4084d28 ra: don't consider nodes for spilling we don't need to
Previously, we would consider any optimistically colored nodes for
spilling. However, spilling any optimistically colored nodes below the
node that we failed to color on the stack wouldn't help us make
progress, since it wouldn't help with allowing us to find a color for
the node currently failing to get colored. Only consider nodes
which were above the failing node on the stack for spilling, which
simplifies the logic, and comment the code better so people know what's
going on here.

No shader-db changes with BRW_MAX_GRF reduced to 90 (or with the normal
number of GRF's).

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-08-13 11:43:30 -07:00
Connor Abbott
567e2769b8 ra: make the p, q test more efficient
We can store the q total that pq_test() would've calculated in the node
itself, updating it when we add a node to the stack. This way, we only
have to walk the adjacency list when we push a node on the stack (i.e.
when the p, q test succeeds) instead of every time we do the p, q test.

No difference in shader-db run times, but I'm keeping this in because
the q total that it calculates will also be used in the next few commits.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-08-13 11:43:22 -07:00
Connor Abbott
9a0b52e7c1 ra: cleanup the public API
Previously, there were 3 entrypoints into parts of the actual allocator,
and an API called ra_allocate_no_spills() that called all 3. Nobody
would ever want to call any of the 3 entrypoints by themselves, so
everybody just used ra_allocate_no_spills(). So just make them static
functions, and while we're at it rename ra_allocate_no_spills() to
ra_allocate() since there's no equivalent "with spills," because the
backend is supposed to handle spilling.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-13 11:43:05 -07:00
Ilia Mirkin
d72d67832b nouveau: only try to get new storage if there are any levels
This would try to allocate 0-sized bo's when the max level was below the
base level.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-08-13 10:09:01 -04:00
Ilia Mirkin
ddcbea91f1 nouveau: add emacs dir-locals file for tabs/8-space indents
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-08-13 09:59:04 -04:00
Ilia Mirkin
8049e5a1f6 nvc0: increase GLSL level to 400 to enable ARB_gpu_shader5
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-08-13 09:59:04 -04:00
Ilia Mirkin
6f1edf3cbf mesa/st: enable ARB_gpu_shader5 if the reported GLSL version >= 400
The ARB_gpu_shader5 extension is made up of a lot of small sub-parts.
Instead of adding PIPE_CAP's for each of these, just rely on the GLSL
version reported by the pipe driver. The remaining extensions lend
themselves naturally to being checked through a single CAP.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-08-13 09:59:04 -04:00
Emil Velikov
38df9f8a06 android: megadriver_stub: prefix static libraries with libmesa_
Will make it easier on us as CleanSpec.mk comes along and improves
consistency across the Android build.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-13 00:46:57 +01:00
Emil Velikov
73121a34d4 android: loader: prefix static libraries with libmesa_*
Will make it easier on us as CleanSpec.mk comes along and improves
consistency across the Android build.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-13 00:46:57 +01:00
Emil Velikov
db4d7229bc android: dri/i9*5: remove used _INCLUDES variable
No longer needed as of last commit.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-13 00:46:57 +01:00
Emil Velikov
725373275c android: drivers/dri: add $(mesa_top)/src to the includes list
Will allow us to nuke an include or two from the drivers.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-13 00:46:56 +01:00
Emil Velikov
48307eb813 android: dri: use the installed libdrm headers
Saves us a few lines and brings us closer to the automake build.
Drop DRM_TOP as it's not longer used.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-13 00:46:56 +01:00