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Alyssa Rosenzweig 7434f31e09 pan/bi: Factor nir_function_impl out of the context 
Unnecessary and complicates unit testing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:44 +00:00
Alyssa Rosenzweig 114a0f9798 pan/bi: Stub out scheduler unit test 
Someone who understands meson and gtest could do something much nicer,
but for now let's just stuff some assertions into debug builds of the
standalone compiler and call it a day...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:44 +00:00
Alyssa Rosenzweig 81692b6d2c pan/bi: Add "word equivalence" relation for index 
Takes offset *but not swizzle* into account, so the scheduler can
predict whether indices will end up mapped to the same scalar register.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:44 +00:00
Alyssa Rosenzweig ab6f05eabd pan/bi: Move init_builder to common code 
Needs to take a cursor to be applicable outside NIR->BIR of course.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:44 +00:00
Alyssa Rosenzweig 60c0df2c3b pan/bi: Print multiple destinations if needed 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:44 +00:00
Alyssa Rosenzweig a7cc458dc4 pan/bi: Add CUBEFACE pseudoinstruction 
Abstracts over *CUBEFACE1/+CUBEFACE2, takes the sources of the former
and outputs two destinations.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:44 +00:00
Alyssa Rosenzweig 44726101d1 pan/bi: Don't fill garbage 
If an index is an SSA form and we haven't even written to it yet, there
is absolutely no value in filling it, it'd just be uninitialized garbage
that won't get used. Saves some fills in STK.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig ee7aaa27b8 pan/bi: Implement spilling at the clause-level 
We use essentially the same logic, but we need to treat entire clauses
as large instructions, and spill on clause boundaries instead of
instruction boundaries. So factor out the code a bit, using the new
iterators, removing bi_unwrap_singleton.

A few specific fixes are needed to adapt. One is simple: rewriting
destinations needs to preserve clamps and such. The other is a much more
subtle bug. Consider the clause

   {
      ADD 0, ...
      ---unrelated code---
      MUL 1, 0, ...
   }

Suppose we spill 0. The naive spill code would generate an SSA temporary to
spill to and another SSA temporary to fill from, generating:

   {
      LOAD.tl 10
   }
   {
      ADD 11, ...
      ---unrelated code---
      MUL 1, 10, ...
   }
   {
      STORE.tl 11
   }

But this is wrong; the MUL now reads stale (and for SSA, likely
undefined/uninitialized) data. The simplest fix, employed here, is to
spill/fill within a clause simultaneously, which means the temporary
can't be SSA, generating correct code:

   {
      LOAD.tl r0
   }
   {
      ADD r0, ...
      ---unrelated code---
      MUL 1, r0, ...
   }
   {
      STORE.tl r0
   }

This is suboptimal, since the LOAD is still likely reading garbage that
is unused. But it is still correct, and the next commit will avoid
generating the load in this case.

To make the bug even more subtle, if ADD/MUL are within 2-3 instructions
of each other, the scheduler will optimize the load to a
temporary/passthrough, so the bug isn't noticed. It only happens if they
are 3+ instructions apart yet still in the same clause (<=16
instructions).

Special thanks to macc24 for reporting this bug and to Jason Ekstrand
for allowing me to rubberduck.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig c578ca7393 pan/bi: Add interference per clause 
With new helpers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig 108e10f32a pan/bi: Permit multiple destinations in RA 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig 07b13647cb pan/bi: Don't open code bi_foreach_dest 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig 083a658ee8 pan/bi: Add destination iterator macro 
Convenience.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig eca516ebdb pan/bi: Add bi_foreach_instr_in_clause iterators 
These are convenient for post-sched passes, in particular register
allocation. They work by noting the underlying linked list of
instructions in the block must be preserved by scheduling. It isn't
necessary iterate the clause structure directly, it can simply be used
to bound a iteration within the block by recalling clauses are strictly
contained in a single block.

   <alyssa> I don't think I'm enough of a C ninja to write fancy iterator macros yet.
   <zmike> sometimes those can get pretty mind-bendy

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig 62239f68b7 pan/bi: Add bi_foreach_instr_in_tuple helper 
Written in a funny way but easy to convince yourself of correctness by
considering cases.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig 2f785ad9ac pan/bi: Add bi_foreach_clause_in_block_rev 
Trivial absense.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig ec0d0426d6 pan/bi: Add bi_{before,after}_clause cursors 
Will be needed to insert spill code after scheduling once we have
multiple instructions in a clause.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig 3ce67cb0d9 pan/bi: Add "soft" mode to DCE 
We would like to reuse the DCE logic to eliminate register writes
without eliminating instructions, as a post-sched pass. This type of
operation will eventually generalize to intrinsics that write a register
*and* have side effects (just atomics, I think).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig 623bd2127f pan/bi: Add dead branch elimination pass 
Ported from Midgard due to the same quirk of our code generation.
Additional validation, though.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig d0902aa2d4 pan/bi: Pass through wait_{6, 7} flags 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig 19b195d3bf pan/bi: Move bi_next_clause to bir.c 
Not really packing specific anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig 2492074d3d pan/bi: Pull out bi_count_read_registers helper 
I want to transition away from the ad hoc masks anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig a69c73988b pan/bi: Fix M1/M2 decoding in disassembler 
C's definition of the % operator has a footgun around sign conversion.
Avoid it and just use bitwise arithemtic instead like the hardware
would, fixing the disassembly and making buggy assembly more obvious.

Fixes: 08a9e5e3e8 ("pan/bi: Decode M values in disasm")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig 6f28a4449a pan/bi: Fix dependency wait calculation 
Unconditional branches have a successor in the first slot only.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig 6cb0a0ad63 pan/bi: Fix staging register packing 
Writes are from the previous tuple, not the current one, otherwise we
incorrectly write to "two" places at once and raise an INSTR_INVALID_ENC
fault. While we're at it, fix the weird spacing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig bca242c785 pan/bi: Fix IDLE register mode packing 
Was incorrectly returning zero. Special case like IDLE_1.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig f1d551ea9f pan/bi: Print disasm/stats with DEBUG=internal 
Arguably more important than the IR prints.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig d3c92d32ba pan/bi: Lint for infinite loops 
I would make this unconditional, but conditionally branching to the same
clause in a tight loop is (disturbingly) legal, as far as I know.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig 63c2ee2c4c pan/bi: Refactor PC-relative printing 
Let's get the offset in a named variable for validation.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig 24991d787f pan/bi: Print FAU index in verbose mode 
Even if we're not loading a uniform, this is useful information. The
uniform pretty-printing didn't correspond well to the hardware anyway so
this is a net win, although if somebody really wanted pretty-printing
could be added in here.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig 15d03ed783 pan/bi: Validate format 12 tuple count in disasm 
We were throwing away this information. Let's just use a lookup table
and add an assertion. Would have caught a bug in this series resulting
in INSTR_INVALID_ENC faults.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig 61af9cb76b pan/bi: Add internal debug flag 
Since 3186401751 ("pan/bi: Suppress disassembly for internal shaders"),
we haven't had a good way to debug blit shaders. I keep rewriting this
patch manually, let's just a debug flag for it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig b1ebe7a19b panfrost: Allow waiting on slots 6/7 during preload 
I don't understand the underlying uarch details but ATEST needs to wait
on slot 6 and BLEND needs to wait on both, so these bits are used if
ATEST/BLEND are in the first clause, which happens if e.g. a constant
colour is written, or if the input is preloaded.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Alyssa Rosenzweig a5780cdb9b panfrost: Fix TLS sizing if cores are missing 
I have no idea if there are any implementations we care about that have
missing shader cores (a mask of 1101 or something like that), but if one
crops up, this would be a royal pain to debug so let's just get it
right...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
 2021-01-29 16:55:43 +00:00
Mike Blumenkrantz 26b009b054 zink: move tess/geom shader info to vs shader key 
now that there exists a shader key for vertex stages, we can stop modifying
the zink_shader values and instead use this as a more reliable method of detecting
the state

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8682>
 2021-01-29 15:38:06 +00:00
Mike Blumenkrantz 9b8c121917 zink: flag shaders as needing update when clip_halfz changes 
this means we may or may not need to run the nir pass in the shader,
so force this to go back through the update path using the shader key

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8682>
 2021-01-29 15:38:06 +00:00
Mike Blumenkrantz 03971d8ddc zink: add shader key for vs shaders 
we're reusing these for tes/gs for now too

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8682>
 2021-01-29 15:38:06 +00:00
Mike Blumenkrantz 079f348a5c zink: flag previous vertex stages as dirty when toggling a later stage 
this ensures that the correct variant is used for streamout and halfz

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8682>
 2021-01-29 15:38:06 +00:00
Mike Blumenkrantz aedde2d60d zink: improve barrier helper for buffer resources and add check for barrier need 
now we've got the ability to add fine-grained barriers for buffer resources, so we
can also have a utility function to check whether we need to use barriers and
then skip them when we don't

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8669>
 2021-01-29 13:21:37 +00:00
Mike Blumenkrantz 49ee821eb9 zink: add helper function for checking if access flags include write access 
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8669>
 2021-01-29 13:21:37 +00:00
Mike Blumenkrantz 1077bd0c64 zink: add a stage param for buffer resource barriers 
it's useful to be able to set this more granularly when doing resource
barriers

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8669>
 2021-01-29 13:21:37 +00:00
Mike Blumenkrantz 37cd4070e8 zink: add barrier helper for buffer resources 
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8669>
 2021-01-29 13:21:36 +00:00
Samuel Pitoiset 718c4726f3 radv: fix centroid with VRS coarse shading 
Ported from RadeonSI.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8775>
 2021-01-29 12:53:15 +00:00
Samuel Pitoiset c092ff2f2f radv: re-disable TC-compat HTILE for D32S8 on all generations 
This actually introduced some VRS related regressions and some others.

Fixes: cc5b6a0e89 ("radv: enable TC-compat HTILE with D32S8 and MSAA on GFX9+")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8777>
 2021-01-29 13:29:32 +01:00
Marcin Ślusarz 97c3ec6116 intel/compiler: cache computed register pressure benefit 
This halves the number of calls to get_register_pressure_benefit
and decreases shader-db CPU time by ~1.5%.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8741>
 2021-01-29 11:31:39 +00:00
Pierre-Eric Pelloux-Prayer 5dc823304b radeonsi/sqtt: forward string markers to sqtt 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8746>
 2021-01-29 08:44:12 +00:00
Pierre-Eric Pelloux-Prayer 3bd5120a57 radeonsi/sqtt: allow AMD_THREAD_TRACE_TRIGGER to be a frame number 
This makes it easier to capture the exact same frame (for instance from an
apitrace replay).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8746>
 2021-01-29 08:44:11 +00:00
Pierre-Eric Pelloux-Prayer 80c3ed147b radeonsi/sqtt: fix SQTT bo size overflow 
Ported from c40ea24ee0

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8746>
 2021-01-29 08:44:11 +00:00
Pierre-Eric Pelloux-Prayer f2d57d28ed radeonsi/sqtt: use more event identifier 
Using event identifiers allows to add a bit more context to the RGP trace.
Without this all draw calls are identified as vkCmdDraw.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8746>
 2021-01-29 08:44:11 +00:00
Pierre-Eric Pelloux-Prayer a77834cecf ci: split src/mesa/**/* matching rule 
Split the rule to avoid running useless tests when touching the driver specific
sources.

v2: removed src/mesa/drivers/x11/**/*

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net> (v2)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8735>
 2021-01-29 09:18:24 +01:00
Kenneth Graunke 84a38ec133 iris: Enable PIPE_CAP_SHAREABLE_SHADERS. 
Now that we store shader variants in the objects themselves rather
than a per-context hash table, they are actually global across
contexts.  We can enable this feature.

This makes shaders shared across contexts, so apps can compile in
one and use it in another.  This has always been allowed by GL,
but in the past we've simply recompiled the shaders in every context,
which is slow and painful.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7668>
 2021-01-29 06:26:29 +00:00