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161321 Commits

Author SHA1 Message Date
Faith Ekstrand
39b5bb0809 intel/fs: Drop support for nir_register 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24104>
 2023-07-19 02:11:57 +00:00
Faith Ekstrand
ce75c3c3fe intel: Switch to intrinsic-based registers 
Results on HSW (vec4 only):

    total instructions in shared programs: 2978400 -> 2974135 (-0.14%)
    instructions in affected programs: 77870 -> 73605 (-5.48%)
    helped: 143
    HURT: 48
    helped stats (abs) min: 1 max: 100 x̄: 30.22 x̃: 9
    helped stats (rel) min: 0.03% max: 30.49% x̄: 8.02% x̃: 6.39%
    HURT stats (abs)   min: 1 max: 4 x̄: 1.19 x̃: 1
    HURT stats (rel)   min: 0.08% max: 16.67% x̄: 3.71% x̃: 3.23%
    95% mean confidence interval for instructions value: -26.69 -17.97
    95% mean confidence interval for instructions %-change: -6.24% -3.90%
    Instructions are helped.

    total cycles in shared programs: 45345924 -> 44742666 (-1.33%)
    cycles in affected programs: 29083466 -> 28480208 (-2.07%)
    helped: 4785
    HURT: 3879
    helped stats (abs) min: 2 max: 8072 x̄: 276.00 x̃: 24
    helped stats (rel) min: 0.02% max: 54.43% x̄: 7.78% x̃: 1.95%
    HURT stats (abs)   min: 2 max: 14736 x̄: 184.95 x̃: 20
    HURT stats (rel)   min: 0.02% max: 97.00% x̄: 7.69% x̃: 1.53%
    95% mean confidence interval for cycles value: -83.49 -55.77
    95% mean confidence interval for cycles %-change: -1.16% -0.55%
    Cycles are helped.

    total spills in shared programs: 1093 -> 539 (-50.69%)
    spills in affected programs: 772 -> 218 (-71.76%)
    helped: 74
    HURT: 0

    total fills in shared programs: 760 -> 757 (-0.39%)
    fills in affected programs: 66 -> 63 (-4.55%)
    helped: 3
    HURT: 0

Results on TGL (all stages):

    total instructions in shared programs: 21486982 -> 21488266 (<.01%)
    instructions in affected programs: 2245938 -> 2247222 (0.06%)
    helped: 1288
    HURT: 1385
    helped stats (abs) min: 1 max: 93 x̄: 4.05 x̃: 2
    helped stats (rel) min: 0.02% max: 3.82% x̄: 0.61% x̃: 0.46%
    HURT stats (abs)   min: 1 max: 134 x̄: 4.69 x̃: 2
    HURT stats (rel)   min: <.01% max: 5.59% x̄: 0.65% x̃: 0.44%
    95% mean confidence interval for instructions value: 0.13 0.83
    95% mean confidence interval for instructions %-change: <.01% 0.08%
    Instructions are HURT.

    total cycles in shared programs: 809326677 -> 809475669 (0.02%)
    cycles in affected programs: 447781659 -> 447930651 (0.03%)
    helped: 1924
    HURT: 1994
    helped stats (abs) min: 1 max: 74567 x̄: 1217.49 x̃: 10
    helped stats (rel) min: <.01% max: 38.44% x̄: 1.09% x̃: 0.17%
    HURT stats (abs)   min: 1 max: 76426 x̄: 1249.47 x̃: 8
    HURT stats (rel)   min: <.01% max: 137.11% x̄: 1.64% x̃: 0.17%
    95% mean confidence interval for cycles value: -125.61 201.67
    95% mean confidence interval for cycles %-change: 0.12% 0.48%
    Inconclusive result (value mean confidence interval includes 0).

    LOST:   4
    GAINED: 4

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24104>
 2023-07-19 02:11:57 +00:00
Faith Ekstrand
abb6188a04 intel/vec4: Add support for new-style registers 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24104>
 2023-07-19 02:11:57 +00:00
Faith Ekstrand
f783eb9ebd intel/vec4: Assume get_nir_dest() provides a sane write-mask 
It should be providing a write mask that is all the channels.  Drop the
one case for load_input where we stomp this for no good reason.  Also,
make ALU write-masking AND with the existing mask.  This prepares us for
the next patch where we convert to new-style registers.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24104>
 2023-07-19 02:11:57 +00:00
Faith Ekstrand
b8209d69ff intel/fs: Add support for new-style registers 
The old ones still work for now.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24104>
 2023-07-19 02:11:57 +00:00
Timothy Arceri
c64ad299e4 glsl: fix validation of ES vertex attribs 
From OpenGL ES 3.0 spec, page 56:

    "Binding more than one attribute name to the same location
     is referred to as aliasing, and is not permitted in OpenGL
     ES Shading Language 3.00 vertex shaders. LinkProgram will
     fail when this condition exists. However, aliasing is
     possible in OpenGL ES Shading Language 1.00 vertex shaders.
     This will only work if only one of the aliased attributes
     is active in the executable program, or if no path through
     the shader consumes more than one attribute of a set of
     attributes aliased to the same location. A link error can
     occur if the linker determines that every path through the
     shader consumes multiple aliased attributes, but implemen-
     tations are not required to generate an error in this case."

So here we make sure to allow the optimisations before validation
for earlier ES shader versions.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

Fixes: 80c001013c ("glsl: do vs attribute validation in NIR linker")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9342
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24205>
 2023-07-19 00:43:26 +00:00
Eric Engestrom
0f557ffa26 ci: move lavapipe files rules to src/gallium/drivers/lavapipe/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
Eric Engestrom
a15384383b ci: move softpipe files rules to src/gallium/drivers/softpipe/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
Eric Engestrom
14b9f460c2 ci: move llvmpipe files rules to src/gallium/drivers/llvmpipe/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
Eric Engestrom
96344c7b71 ci: move virgl files rules to src/gallium/drivers/virgl/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
Eric Engestrom
e9f2c4b4c2 ci: move intel files rules to src/intel/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
Eric Engestrom
c99f10eb54 ci: move virtio files rules to src/virtio/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
Eric Engestrom
5828d86c26 ci: move zink files rules to src/gallium/drivers/zink/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
Eric Engestrom
7aa9abe473 ci: move microsoft files rules to src/microsoft/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
Eric Engestrom
b7298836c5 ci: move amd files rules to src/amd/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
Eric Engestrom
58077c6add ci: move lima files rules to src/gallium/drivers/lima/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
Eric Engestrom
1625b5984a ci: move broadcom files rules to src/broadcom/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
Eric Engestrom
728ae85b5d ci: move panfrost files rules to src/panfrost/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
Eric Engestrom
8b8169f52e ci: move nouveau files rules to src/gallium/drivers/nouveau/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
Eric Engestrom
52528c7088 ci: move freedreno files rules to src/freedreno/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:51 +00:00
Eric Engestrom
6f176d2cf2 ci: move etnaviv files rules to src/etnaviv/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:51 +00:00
Rohan Garg
614efeeafe intel/genxml: set a default value for "Pixel Position Offset Enable" in genxml 
Set the default value for "Pixel Position Offset Enable" when emitting
3DSTATE_MULTISAMPLE in the genxml so that we can drop it from blorp
and genX_state.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23936>
 2023-07-18 22:25:38 +00:00
David Rosca
e6f0819806 radeonsi/vcn: Enable full/limited range support for H264/HEVC/AV1 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24174>
 2023-07-18 21:40:34 +00:00
David Rosca
756e5d6687 radeonsi/vcn: Set HEVC video signal parameters in bitstream 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24174>
 2023-07-18 21:40:34 +00:00
David Rosca
f44697239d radeonsi/vcn: Set H264 video signal parameters in bitstream 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24174>
 2023-07-18 21:40:34 +00:00
David Rosca
8a21efce3a frontends/va: Add postproc support for converting to full range 
Acked-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24174>
 2023-07-18 21:40:34 +00:00
David Rosca
8438d6363a frontends/va: Parse HEVC SPS for video signal parameters 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24174>
 2023-07-18 21:40:33 +00:00
David Rosca
2785d54b71 frontends/va: Parse H264 SPS for video signal parameters 
Since packed headers support is now advertised for H264,
it also fixes encoding into mkv with ffmpeg.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3524

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24174>
 2023-07-18 21:40:33 +00:00
David Rosca
cfd24047a1 radeonsi/vcn: Don't use chroma in AV1 encode with RGB input 
Fixes: 64eab1f3ae

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24170>
 2023-07-18 20:09:42 +00:00
David Rosca
2cb4c6aef0 frontends/va: Don't use EFC with scaling or filtering enabled 
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24170>
 2023-07-18 20:09:42 +00:00
David Rosca
b5fa9f992d frontends/va: Skip processing buffers already converted with EFC 
Since the EFC conversion reallocates the dst buffer with new format,
any subsequent VA postproc calls on the same surface will fall back
to vl_compositor conversion.

This is the case in ffmpeg where the postproc filter output
buffers are reused instead of allocated for each frame.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24170>
 2023-07-18 20:09:42 +00:00
Yiwei Zhang
0e9affd267 venus: reduce to use 4K mem suballoc align on platforms known to fit 
This is a workaround for low ram arm devices before fixing:
https://gitlab.freedesktop.org/mesa/mesa/-/issues/9351

Test: patch to prior higher limit 16384 and run
      dEQP-VK.api.object_management.max_concurrent.query_pool

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24219>
 2023-07-18 19:38:34 +00:00
Kenneth Graunke
283e3acd3a iris: Re-emit 3DSTATE_DS for each primitive (workaround 14019750404) 
Some platforms require us to re-emit 3DSTATE_DS before every 3DPRIMITIVE
when tessellation is enabled.  See workaround 14019750404.

Cc: 23.2 <mesa-stable>

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24150>
 2023-07-18 19:14:27 +00:00
Iván Briano
4ad19c8310 anv: implement Wa_14019750404 
Cc: 23.2 <mesa-stable>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8931

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24150>
 2023-07-18 19:14:27 +00:00
Iván Briano
7b0ded0b23 anv: ensure mesh is disabled on context init 
It turns out the hardware doesn't save the whole state on a context
switch, as the kernel expects when it creates the golden context.
For some HW units, only the state that was explicitly programmed will be
part of it, so we need to make sure mesh shading is disabled on context
creation, or we risk being context switched with an application that
uses mesh, and when ours gets to run again, the mesh state won't be
reset, and submitting a legacy 3D pipeline while the HW thinks mesh is
enabled causes us to hang.

Cc: 23.2 <mesa-stable>

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24150>
 2023-07-18 19:14:27 +00:00
Iván Briano
50d68f74b5 iris: ensure mesh is disabled on context init 
It turns out the hardware doesn't save the whole state on a context
switch, as the kernel expects when it creates the golden context.
For some HW units, only the state that was explicitly programmed will be
part of it, so we need to make sure mesh shading is disabled on context
creation, or we risk being context switched with an application that
uses mesh, and when ours gets to run again, the mesh state won't be
reset, and submitting a legacy 3D pipeline while the HW thinks mesh is
enabled causes us to hang.

Cc: 23.2 <mesa-stable>

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24150>
 2023-07-18 19:14:27 +00:00
Gert Wollny
f48aa460a2 r600/sfn: Print more info if scheduling fails 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24212>
 2023-07-18 17:51:47 +00:00
Gert Wollny
2a9348967a r600/sfn: Add some tests for proper register access 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24212>
 2023-07-18 17:51:47 +00:00
Gert Wollny
382e198503 r600/sfn: reorder the value factory class member declaration a bit 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24212>
 2023-07-18 17:51:47 +00:00
Gert Wollny
00417c216e r600/sfn: Add peephole optimization to move a dest to the previous op 
This is mostly tailored to the register store op where we get a sequence

   ALU OP S1.x : ...
   ALU MOV R1.x = S1.x

but it can help elsewhere too.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24212>
 2023-07-18 17:51:47 +00:00
Gert Wollny
197bc1ee07 r600/sfn: Increase LDS fetch schedule priority 
Otherwise we may end up scheduling the value read before the
value fetch.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24212>
 2023-07-18 17:51:47 +00:00
Gert Wollny
ddb167e81a r600/sfn: Handle indirect array load/store dependencies better 
Indirect access must depend on all writes to the array

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24212>
 2023-07-18 17:51:47 +00:00
Gert Wollny
d0beaf73d9 r600/sfn: Allow for larger ALU CF's 
We should get as close as possible to the limit the hardware and the
assembler backend allows for.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24212>
 2023-07-18 17:51:47 +00:00
Gert Wollny
d8291cc7ee r600/sfn/tests: add simple copy-prop test with register source 
Just to make sure the register intrinsic conversion doesn't need the helpers.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24212>
 2023-07-18 17:51:47 +00:00
Gert Wollny
10938cddd7 r600/sfn: Switch to register intrinsics 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24212>
 2023-07-18 17:51:47 +00:00
Alyssa Rosenzweig
886a7ae786 r600/sfn: Remove nir_register unit tests 
These tests will be obsolete soon and are just extra users of an API that will
be removed. Drop them.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24212>
 2023-07-18 17:51:47 +00:00
Samuel Pitoiset
f334d00a8a radv: make radv_get_pa_su_sc_mode_cntl() static 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24192>
 2023-07-18 17:07:19 +00:00
Samuel Pitoiset
9299a90cc1 radv: remove support for VK_INDIRECT_COMMANDS_TOKEN_TYPE_STATE_FLAGS_NV 
This isn't used by vkd3d-proton which is the only user of DGC, no need
to overcomplicate this.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24192>
 2023-07-18 17:07:18 +00:00
Marek Olšák
4b93ae7e7a util/u_queue: always enable UTIL_QUEUE_INIT_SCALE_THREADS, remove the flag 
It means that threads are created on demand except for the first one.
It reduces process startup time.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24173>
 2023-07-18 11:11:12 -04:00
Marek Olšák
bfdfe5aa82 util/u_queue: fix util_queue_finish deadlock by merging lock and finish_lock 
and by disabling the on-demand thread creation, which breaks the finish logic.

Fixes: 3713dc6b2a - util/u_queue: add UTIL_QUEUE_INIT_SCALE_THREADS flag
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8363

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24173>
 2023-07-18 11:11:12 -04:00