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6624 Commits

Author SHA1 Message Date
Marcin Ślusarz 3340d5ee02 intel: simplify is_haswell checks, part 1 
Generated with:

files=`git grep is_haswell | cut -d: -f1 | sort | uniq`
for file in $files; do
        cat $file | \
                sed "s/devinfo->ver <= 7 && !devinfo->is_haswell/devinfo->verx10 <= 70/g" | \
                sed "s/devinfo->ver >= 8 || devinfo->is_haswell/devinfo->verx10 >= 75/g" | \
                sed "s/devinfo->is_haswell || devinfo->ver >= 8/devinfo->verx10 >= 75/g" | \
                sed "s/devinfo.is_haswell || devinfo.ver >= 8/devinfo.verx10 >= 75/g" | \
                sed "s/devinfo->ver > 7 || devinfo->is_haswell/devinfo->verx10 >= 75/g" | \
                sed "s/devinfo->ver == 7 && !devinfo->is_haswell/devinfo->verx10 == 70/g" | \
                sed "s/devinfo.ver == 7 && !devinfo.is_haswell/devinfo.verx10 == 70/g" | \
                sed "s/devinfo->ver < 8 && !devinfo->is_haswell/devinfo->verx10 <= 70/g" | \
                sed "s/device->info.ver == 7 && !device->info.is_haswell/device->info.verx10 == 70/g" \
                > tmpXXX
        mv tmpXXX $file
done

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10810>
 2021-05-17 09:46:45 +00:00
Nanley Chery eef4c708b3 anv: Avoid sampling some MCS surfaces with clear 
Supposedly avoids GPU hangs in BF4. See HSD 1707282275 and 14013111325.

v2. Fix bug in WA implementation. (Sagar)

Cc: mesa-stable
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8755>
 2021-05-14 18:05:32 +00:00
Nanley Chery 608c131638 anv: Add clear_supported to anv_layout_to_aux_state 
This will be used for an MCS workaround.

Cc: mesa-stable
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8755>
 2021-05-14 18:05:32 +00:00
Lionel Landwerlin 938e52a6e8 anv: handle spirv parsing failure 
v2: don't leak spec_entries

v3: Also switch to VK_ERROR_UNKNOWN when parsing fails

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10790>
 2021-05-14 06:32:03 +00:00
Jordan Justen e435511b58 intel/dev: Add device info for ADL GT2 
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9465>
 2021-05-14 06:10:47 +00:00
Jordan Justen 89f3312625 intel/isl: Add Wa_22011186057 to disable CCS on ADL GT2 A0 
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9465>
 2021-05-14 06:10:47 +00:00
Caio Marcelo de Oliveira Filho c0dc6affdc intel/compiler: Clarify why VUE is recomputed by FS 
FS will get the last geometry VUE, but it still needs to recompute in
case the number of position slots assigned by geometry is larger than
one -- this happens when Primitive Replication is used.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10653>
 2021-05-13 12:10:26 -07:00
Lionel Landwerlin 2cebb1b5b3 anv: fix perf query pass with command buffer batching 
We've only considered the perf query pool change previously. But we
also need to pay attention to the pass index.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 0a7224f3ff ("anv: group as many command buffers into a single execbuf")
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10301>
 2021-05-13 17:02:41 +00:00
Lionel Landwerlin 2c2de4d60e intel/mi_builder: fix resolve call 
Giving NULL for anv_combine_address() triggers an assert in that
function.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 8525ebe6e3 ("intel/mi_builder: Return an address from __gen_get_batch_address")
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10301>
 2021-05-13 17:02:41 +00:00
Tapani Pälli 343d90b6ab isl: require hiz for depth surface in isl_surf_get_ccs_surf 
Fixes: 752eefdb ("intel/isl: Refactor isl_surf_get_ccs_surf")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10768>
 2021-05-13 17:18:54 +03:00
Lionel Landwerlin f46aa1b9d7 intel/fs: use the final destination type for regioning restrictions 
This is most likely a rebase mistake :(

Fixes: f3e5cd813a ("intel/fs: Handle regioning restrictions of split FP/DP pipelines.")
Ref: aa53665fda ("intel/fs/copy_prop: check stride constraints with actual final type")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10764>
 2021-05-12 21:19:11 +00:00
Jason Ekstrand b13d0eea12 anv: Allow storage on all formats that support typed writes 
In particular, this gives us B8G8R8A8_UNORM storage support which is
useful for writing WSI images from compute shaders.  These formats can
only be accessed in a spec-compliant way by decorating the variable
NonReadable in the SPIR-V (writeonly in GLSL).  If the client doesn't so
decorate the variable, it'll get the null surface state where reads
return 0 and writes are ignored.

Tested-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10624>
 2021-05-05 12:20:09 +00:00
Lionel Landwerlin df0580312a isl: document format fields 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10624>
 2021-05-05 12:20:09 +00:00
Jason Ekstrand 9301b637cf anv: Check offset instead of alloc_size for freeing surface states 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10624>
 2021-05-05 12:20:09 +00:00
Dave Airlie 922f71b819 intel/decoder: add gen4/5 geometry state decode 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10642>
 2021-05-05 07:28:34 +00:00
Dave Airlie d91d3613ad intel/decoder: fixup batch decoder for binding tables on gen4/5 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10642>
 2021-05-05 07:28:34 +00:00
Dave Airlie 4d80ec8fcf intel/genxml: fix raster op fields on gen4/5 
These should be unsigned integers

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>
 2021-05-05 02:56:20 +00:00
Dave Airlie e5169714ea intel/gemxml: move blitter command to render on gen4/5 
The blitter commands don't show up in INTEL_DEBUG=bat, but on
gen4/5 they are emitted on the render engine ring so just change
the XML to reflect that.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>
 2021-05-05 02:56:20 +00:00
Dave Airlie c6f34e9fda intel/genxml: rewrite the prefilterop xml to be more consistent. 
This uses a prefix at Ken's suggestion and aligns it across gens

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>
 2021-05-05 02:56:20 +00:00
Dave Airlie 04ed882046 intel/genxml: align gen4/5 xml for store data immediate 
Just align with the gen6 and later xml

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>
 2021-05-05 02:56:20 +00:00
Ilia Mirkin 10abc09a04 intel: fix MI builder for pre-gen7 
MI_LOAD_REGISTER_MEM is only available on gen7+, so avoid build errors
on earlier generations.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>
 2021-05-05 02:56:20 +00:00
Caio Marcelo de Oliveira Filho dd48683cfd nir: Move shared_memory_explicit_layout bit into common shader_info 
Move it out of the "cs" sub-struct, since the bit can be used for
other shader stages in the future.

This also removes a subtle issue in spirv_to_nir:
info.cs.shared_memory_explicit_layout was used without checking for
the CS shader stage.  It ended up being "harmless" since the effects
also depended on presence of shared variables.

Fixes: 5de6c5973a ("spirv: Implement SPV_KHR_workgroup_memory_explicit_layout")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10529>
 2021-05-04 20:54:58 +00:00
Caio Marcelo de Oliveira Filho caf9fb1a10 intel/compiler: Remove unused exported functions 
Now that all drivers are using brw_cs_get_dispatch_info() we can
remove one function (which is now unused) and reduce the scope of the
other.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>
 2021-05-04 08:15:19 -07:00
Caio Marcelo de Oliveira Filho 279acf1031 anv: Use brw_cs_get_dispatch_info() 
And since right_mask is already provided as part of dispatch_info,
just use that instead of storing it.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>
 2021-05-04 08:15:19 -07:00
Caio Marcelo de Oliveira Filho 5cc758558d intel/compiler: Add common function for CS dispatch info 
We have this small calculations repeated in each Intel driver, so move
them to a single place to be reused.  Also includes "right_mask" since
is always used in the same context and depends on the dispatch info
values.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>
 2021-05-04 08:15:19 -07:00
Dave Airlie 52e426fd8b intel/compiler: add support for compiling fixed function gs 
This is ported from i965, but the interface is cleaned up

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9721>
 2021-05-04 03:39:45 +00:00
Dave Airlie ac33e2b66b intel: move brw_ff_gs_prog_key/data to compiler. 
Step one to moving the ff_gs emitter to compiler for sharing,
move BRW_MAX_SOL_BINDINGS up so the keys are in same area

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9721>
 2021-05-04 03:39:45 +00:00
Jason Ekstrand 05a37e2422 intel/nir: Set lower txs with non-zero LOD 
There's a recently discovered HW bug affecting hardware at least as far
back as Skylake where, if the LOD is out-of-bounds for any SIMD lane,
then garbage may be returned in all SIMD lanes.  The easy solution is to
set lower_txs_lod so that we always have a constant LOD of 0 which we
know a priori is always in-bounds.  Fortunately, not many shaders
actually use textureSize() with LOD.

Shader-db results on Ice Lake:

    total instructions in shared programs: 19948537 -> 19948564 (<.01%)
    instructions in affected programs: 3859 -> 3886 (0.70%)
    helped: 0
    HURT: 7

One of the shaders is in Civilization: Beyond Earth, and the rest are
all in Civilization VI.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10538>
 2021-05-04 00:02:43 +00:00
Jason Ekstrand 3f36e027d3 intel/fs: Don't use pixel_z for Gen4-5 source_depth_to_render_target 
The source_depth_to_render_target flag can get set on old gen4-5 HW in a
few cases which are independent of the app writing gl_FragDepth.  It
should be safe to just use fetch_payload_reg in that case instead of
depending in interpolation setup.  This fixes a bug with certain very
simple shaders where we might end up not including the depth when we
should have.

While we're here, rework the logic around setting src_depth and add a
comment so it's more clear what's going on.

Fixes: 6d4070f3dd "intel/compiler: add support for fragment coordinate..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10596>
 2021-05-03 23:51:51 +00:00
Jason Ekstrand 94c1e65de9 intel/eu: Set message subtype properly for SIMD8 FB fetch 
There were two bugs which crep in here as part of 64551610d1:
forgetting that exec sizes in HW are in log2 space and having the
exec_size condition for the subtype backwards.

Fixes: 64551610d1 "intel/compiler: rework message descriptors..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10588>
 2021-05-03 15:30:41 +00:00
Lionel Landwerlin 231651fd89 anv: implement VK_KHR_fragment_shading_rate 
Available on Gen11+.

v2: Order shading rate in correct order (Samuel)

v3: Move CPS_STATE emission to genX_state.c

v4: Don't override various output structures (Jason)

v5: Rebase on top master (Lionel)

v6: Fix invalid VkPhysicalDeviceFragmentShadingRatePropertiesKHR
    (min|max)FragmentShadingRateAttachmentTexelSize values (Ken)
    Drop #endif comment

v7: Limit extension to Gfx11+ (Lionel)
    Support conservative raster (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Jason Ekstrand 34c560ae95 intel/fs: Stop using brw_dp_read/write_desc in Gen7+ only code 
Those helpers exist primarily to sort out some of the weirdness around
Gen4-6 dataport access.  On Gen5 and earlier, everything was called
"dataport" and, instead of the SFID we have today there was a "target
cache" parameter in the descriptor.  There are also some bits that moved
around on various gens depending on read vs. write.  Starting with Gen6,
most things which target one of the data cache SFIDs should use
brw_dp_desc() instead.

v2: Drop backward comment (Ken)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Jason Ekstrand 2e7656ae2f intel/eu: SVB writes only happen on Gen6 
It's a Gen6 XFB thing.  It's never used for anything else so there's no
point in having a target cache switch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin 0421690f83 intel/compiler: add restrictions related to coarse pixel shading 
v2: Update to BITSET_TEST()

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin 81f369c93b intel/compiler: add coarse pixel offset on Gfx12.5+ 
Gfx12.5 has a slightly different code path.

v2: Document the oddness

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin 6d4070f3dd intel/compiler: add support for fragment coordinate with coarse pixels 
v2: Drop new internal opcodes (Jason)
    Simplify code (Jason)

v3: Add Z computation for coarse pixels

v4: Document things a little

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin a297061524 intel/compiler: add support for fragment shading rate variable 
v2: Drop old register type initializers (Jason)
    Simplify instruction snippet (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin b6332fc4a8 intel/compiler: handle coarse pixel in render target writes descriptors 
v2: Use the new inst->ex_desc field (Jason)

v3: Drop CPS LoD compensation from sampler messages (Lionel)

v4: Drop useless uses_rate_shading (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin d665c2dcf0 intel/compiler: use existing helpers to pull bits of descriptors 
v2: Use new RT descriptor helper

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin 64551610d1 intel/compiler: rework message descriptors for render targets 
Render target message descriptors are slightly different from the
dataport ones. In particular the msg_type field is on bits 14:17 for
RT while bits 14:18 for DP.

v2: Drop unused send_commit_msg field in brw_fb_write_desc() (Ken)

v3: Rebase on top renaming (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin dabaaaf6c7 intel/compiler: make sure we keep the lowest dispatch limit 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin 4dcfb18a82 intel/decoder: decode CPS_STATE 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin b1622af394 intel/genxml: Add coarse pixel shading instructions 
v2: Add Gen12.5

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Lionel Landwerlin bbfc959d03 intel/dev: printout correct subslice/dualsubslice name 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Jason Ekstrand b80720acb1 intel/isl: Fix isl_color_value_unpack to match the prototype 
The prototype uses a pointer and the actual function definition had an
array.  For some reason, GCC never complained about this until GCC 11.
This fixes a compile warning when building with GCC 11.

Fixes: 09ced65420 "intel/isl: Add format conversion code"
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10537>
 2021-04-30 17:01:05 +00:00
Jordan Justen 3f04383521 intel/compiler: Fix INTEL_DEBUG=hex 
With the missing else, this prints the compacted hex followed by hex
for an uncompacted version of the compacted instruction. It also
doesn't print hex for instructions that are not compacted.

Fixes: bc4a127d6e ("intel/disasm: Label support in shader disassembly for UIP/JIP")
Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4245
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10535>
 2021-04-30 01:51:23 -07:00
Jason Ekstrand 656c30ac59 intel/isl: There are seven aux states 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10515>
 2021-04-28 23:16:03 -05:00
Rhys Perry 7a7838529a nir/lower_non_uniform: allow lowering with vec2 handles 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9523>
 2021-04-27 15:56:07 +00:00
Jason Ekstrand 3c8ac6a129 anv: Implement VK_EXT_provoking_vertex 
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10460>
 2021-04-26 15:13:19 +00:00
Jason Ekstrand 22b8bcda2c anv: Use the same re-order mode for streamout as for GS 
This makes the vertex order of TRISTRIP and TRISTRIP_ADJ primitves
consistent between XFB output and GS input.  Technically, the Vulkan
spec allows us to XFB out in whatever order we want but being consistent
with GS inputs is probably nicer to apps.

Fixes: 36ee2fd61c "anv: Implement the basic form of VK_EXT_transform_feedback"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10460>
 2021-04-26 15:13:19 +00:00