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11999 Commits

Author SHA1 Message Date
Jordan Justen 2217cff68a pci_ids/intel: Add LNL PCI IDs (with FORCE_PROBE set) 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29273>
 2024-05-28 18:45:49 +00:00
Jordan Justen 845ca72a14 intel/dev: Add LNL device info 
Reworks:
 * José: Disable has_integer_dword_mul support (BSpec 56800)
 * Rohan: Set has_indirect_unroll
 * José: Add PAT settings
 * Jianxun: Set has_flat_ccs

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Co-authored-by: José Roberto de Souza <jose.souza@intel.com>
Co-authored-by: Rohan Garg <rohan.garg@intel.com>
Co-authored-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29273>
 2024-05-28 18:45:49 +00:00
Jordan Justen 237d9e7c45 intel/dev: Support INTEL_FORCE_PROBE env-var 
This environment variable allows some Intel devices that are
unsupported to be forced to run. These devices have incomplete
support, and therefore might not work at all.

Reworks:
 * José: Simplify scan_for_force_probe() with strtok()

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29273>
 2024-05-28 18:45:49 +00:00
Jordan Justen c967b38c7c intel/dev: Allow setting FORCE_PROBE for intel PCI IDs 
For example:

CHIPSET(0x56a0, dg2_g10, "DG2", "Intel(R) Arc(tm) A770 Graphics", FORCE_PROBE)

For now if a PCI ID has FORCE_PROBE set, then we refuse to start the
device.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29273>
 2024-05-28 18:45:49 +00:00
Iván Briano 8d098ecfea anv: check cmd_buffer is on a transfer queue more properly 
The queueFlags of the associated queue may have more flags than just the
type of queue it is, based on what that queue supports, like sparse or
protected content. Check that the queue is a blitter engine instead.

Fixes a bunch of dEQP-VK.api.copy_and_blit.core.*_transfer on MTL with
ANV_SPARSE=0

Fixes: 17b8b2cffd ("anv: Add support for a transfer queue on Alchemist")

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29336>
 2024-05-28 18:25:16 +00:00
Rohan Garg 6fc6f95e90 intel/genxml: Update STATE_COMPUTE_MODE for Xe2 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Rohan Garg f5a5c35717 intel/genxml: update MI_SEMAPHORE_WAIT for Xe2 
Rework:
 * José: Restore "Register Poll Mode" default to "Memory Poll"
 * José: Other minor formatting changes to match other genxml

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Rohan Garg 569a037fb1 intel/genxml: Update XY_BLOCK_COPY_BLT 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Rohan Garg 26e78f83bb intel/genxml: update CFE_STATE for LNL 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Rohan Garg 7001134246 isl: enable compression for CPS buffers on xe2+ 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Rohan Garg b9c68883c4 intel/genxml: update 3DSTATE_CPSIZE_CONTROL_BUFFER for xe2+ 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Rohan Garg bd09649750 intel/genxml: add the new state byte stride instruction 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Jordan Justen 17b6db893b intel/genxml: Update 3DSTATE_BTD for xe2 
Reworks:
  - Rohan: 3DSTATE_BTD can also be emitted on the CCS

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Jordan Justen 5709bbe033 intel/genxml: Add XY_FAST_COLOR_BLT for xe2 
Reworks:
  - Rohan: Use a uint for the surface format since we're dropping the
    SURFACE_FORMAT enum from genxml

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Jordan Justen 92fa87f5bd blorp: Update programming for XY_FAST_COLOR_BLT on xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Tapani Pälli 6836118cd2 anv/android: enable emulated astc for applications 
This layer was blocking Android emulated ASTC support as it did not
take "emu_astc_ldr" in to account.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Mi, Yanfeng <yanfeng.mi@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29415>
 2024-05-28 08:11:49 +00:00
José Roberto de Souza a47c5c9eee intel/perf: Add intel_perf_stream_read_samples() 
Because of the differences between i915 and Xe KMD this function is
needed to abstract the special handling that Xe KMD needs while
reading perf stream.
This special handling will be implemented in the next patch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29421>
 2024-05-27 19:34:06 +00:00
José Roberto de Souza 9841aeb6ad intel/perf: Add a macro with header + sample length 
To be more explicit lets have 2 macros one with sample lenght other
with header and sample length.

This will also help add Xe KMD support as it don't have a header like
i915.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29421>
 2024-05-27 19:34:06 +00:00
José Roberto de Souza 2f128b2ba5 intel/perf: Replace drm_i915_perf_record_header by intel_perf_record_header 
drm_i915_perf_record_header requires i915_drm.h but we want to remove
all i915_drm.h includes from common code, so replacing it by
intel_perf_record_header.

No changes in behavior expected as the structs and enums are identical.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29421>
 2024-05-27 19:34:06 +00:00
José Roberto de Souza da43bf3f2e intel/perf: Allocate sseu in heap memory 
This is a i915 specific struct and Xe KMD will not need anything like
that so lets allocate it in heap memory.
This will help us remove the i915_drm.h includes from common code.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29421>
 2024-05-27 19:34:06 +00:00
José Roberto de Souza e1c2847b81 intel/perf: Move i915 specific code to load configurations to i915 file 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29421>
 2024-05-27 19:34:06 +00:00
José Roberto de Souza 30f97a7242 intel/perf: Move i915 specific code from common code 
More code will be moved to i915 specific files in the next patches.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29421>
 2024-05-27 19:34:06 +00:00
José Roberto de Souza 8ad56247c3 intel/perf: Move code that will be shared by both KMDs 
More code will be shared in the next patches.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29421>
 2024-05-27 19:34:06 +00:00
José Roberto de Souza b601e4a18f intel/perf: Replace I915_OA_FORMAT_* usage by platform check 
Removing more i915_drm.h usage from common code.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29421>
 2024-05-27 19:34:06 +00:00
José Roberto de Souza 3d2c3dc62b anv: Nuke perf_query_pass from anv_execbuf 
It is set but not read.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29421>
 2024-05-27 19:34:06 +00:00
José Roberto de Souza 0442803eee intel/perf: Fix return of read_oa_samples_until() 
read_oa_samples_until() was returning OA_READ_STATUS_ERROR even
if already read samples, then it tried again and KMD returned 0/empty
or EAGAIN(as the read would block).

This is not causing any issue because read_oa_samples_for_query()
FALLTHROUGH OA_READ_STATUS_ERROR to OA_READ_STATUS_FINISHED
but that I think it is worthy to fix it.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29421>
 2024-05-27 19:34:06 +00:00
Lionel Landwerlin 2c65d90bc8 intel/brw: ensure find_live_channel don't access arch register without sync 
Another architecture register that requires some care before reading.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 49ee3ae9e8 ("intel/compiler: Lower FIND_[LAST_]LIVE_CHANNEL in IR on Gfx8+")
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29319>
 2024-05-24 07:26:17 +00:00
Lionel Landwerlin 5f2288095b anv: fix shader identifier handling 
When compilation is required, we should return
VK_PIPELINE_COMPILE_REQUIRED. The spec prevents the application from
passing a module or SPIR-V code so we have nothing to compile if the
cache lookup fails :

VUID-VkPipelineShaderStageCreateInfo-stage-06844:
   If a shader module identifier is specified for this stage, a
   VkShaderModuleCreateInfo structure must not be present in the pNext
   chain

VUID-VkPipelineShaderStageCreateInfo-stage-06848:
   If a shader module identifier is specified for this stage, module
   must be VK_NULL_HANDLE

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11208
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29340>
 2024-05-23 19:05:05 +00:00
Renato Pereyra 51d6162c80 anv: Attempt to compile all pipelines even after errors 
Per the Vulkan Spec section 10.1, the implementation is supposed to
attempt to create all pipelines even if creation of any one pipeline
in a create call fails. If more than one error occur, any one error
is valid as a return value.

Signed-off-by: Renato Pereyra <renatopereyra@chromium.org>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29315>
 2024-05-22 17:46:34 +00:00
Lionel Landwerlin 3584fc6482 anv: use weak_ref mode for global pipeline caches 
So that as soon as pipelines are freed, they're removed from the
cache.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11185
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Tested-by: Brian Paul <brian.paul@broadcom.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29283>
 2024-05-22 15:22:56 +00:00
Dylan Baker 46644ba371 meson: use glslang --depfile argument when possible 
This reduces the amount of manual dependency tracking developers need to
do. This is turned on if glslang >= 11.3.0 is used, or 11.9.0 on
Windows, but otherwise the status quo is maintained. This means I have
not removed any use of `depend_files`. We could make make these hard
requirements and remove the use of `depend_files` too.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28329>
 2024-05-20 17:34:17 +00:00
Lionel Landwerlin a31996ce5a anv: switch to vk_device::mem_cache field for default cache 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11175
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29258>
 2024-05-20 08:23:48 +00:00
David Heidelberg 782f2b3dea ci/intel: add new jsl flake 
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29207>
 2024-05-16 22:50:09 +00:00
David Heidelberg 49760b6af6 ci: Revert "ci: update failures list with angle for jsl, tgl" 
MesaCI has new ANGLE, we can revert this one.

This reverts commit 197f99dc70.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29207>
 2024-05-16 22:50:09 +00:00
Danylo Piliaiev 72326e15f3 anv: Use current_frame from vk device to delimit u_trace frames 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29220>
 2024-05-16 18:12:31 +00:00
Danylo Piliaiev 4510350d55 util/u_trace: Pass explicit frame_nr argument to delimit frames 
Otherwise u_trace has to think that each submission is a frame,
and that's not great if we want to gather statistics on per real
frame basis.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29220>
 2024-05-16 18:12:30 +00:00
Francisco Jerez eebc4ec264 intel/brw/xe2+: Round up spill/unspill data size to nearest reg_size multiple. 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:52 +00:00
Francisco Jerez 50daf161f4 intel/brw/xe2+: Lower 64-bit integer uadd_sat. 
Fixes failures of CTS tests that currently end up emitting 64-bit
integer ADDs with saturation, which isn't supported by the hardware.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:52 +00:00
Francisco Jerez 4bb5b25e53 intel/xe2+: Enable native 64-bit integer arithmetic. 
Note that some previously-supported 64-bit integer operations have
been removed from the hardware, so we need to instruct NIR to lower
them.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Francisco Jerez 8be9f00d84 intel/brw/xe2+: Lower 64-bit SHUFFLE and CLUSTER_BROADCAST. 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Francisco Jerez 6261f4d361 intel/brw/xe2+: Fix 64-bit subgroup scan intrinsics not to rely on SEL instructions. 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Francisco Jerez 1bf93ee4ec intel/brw/xe2+: Don't use SEL peephole on 64-bit moves. 
64-bit SEL isn't supported by the INT pipeline on this platform.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Francisco Jerez b18e68fc25 blorp: Allocate fixed amount of space for blend state. 
According to the simulator a cacheline of the blend state cache
corresponds to 3 cachelines of L3 that are always filled regardless of
the number of render targets in use.  Allocate enough space to avoid
pagefaults under simulation, since a scratch page isn't bound by
default.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Francisco Jerez 8f798cc911 intel/brw/xe2+: Fix indirect extended descriptor setup for scratch space. 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Francisco Jerez 0d92ec44e5 intel/brw: Don't emit Z coordinate interpolation if CPS isn't in use. 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Rohan Garg 475fb68726 intel/brw: We no longer have atomic fmin/fmax ops for fp64 in xe2 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Rohan Garg 8d8d3666c6 intel/brw: Advertise fp64 atomic add's when we have 64 bit float support and a LSC 
Rework:
 * Lionel: Simplify to just checking ver >= 20.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Francisco Jerez 7c129d9365 intel/brw/xe2+: Keep PS sample mask in the f1.0 register whether or not kill is used. 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Rohan Garg 7668de019b intel/eu/xe2+: Fix src1 length bits of SEND instruction with UGM target. 
Rework:
 * Francisco Jerez: Specify the src1 length value in the correct
   units. Don't break earlier platforms.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
 2024-05-15 17:16:51 +00:00
Lionel Landwerlin 0daf5e243f anv: shader printf example 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
 2024-05-15 13:13:38 +00:00